KR101266270B1 - Wafer inspection system and wager inspection method thereof - Google Patents
Wafer inspection system and wager inspection method thereof Download PDFInfo
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- KR101266270B1 KR101266270B1 KR1020120019688A KR20120019688A KR101266270B1 KR 101266270 B1 KR101266270 B1 KR 101266270B1 KR 1020120019688 A KR1020120019688 A KR 1020120019688A KR 20120019688 A KR20120019688 A KR 20120019688A KR 101266270 B1 KR101266270 B1 KR 101266270B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
Abstract
The present invention relates to a wafer inspection system and method thereof.
In the present invention, the wafer inspection system for inspecting the surface defects of the wafer can automatically perform sequential inspection by driving the stage based on a predetermined macro, and the cell determined as the defect using the wafer map image. With respect to the coordinate information can be automatically obtained.
Description
The present invention relates to a wafer inspection system and a method thereof, and more particularly, to a wafer inspection system and method for inspecting the surface defect of the wafer in a semiconductor process.
As the degree of integration of semiconductor devices increases recently, patterns formed on wafers become more and more fine, and the wafer diameter is large due to the development of wafer manufacturing technology. Increasing the integration density of the semiconductor device and the large diameter of the wafer also increase the defect inspection for improving the yield.
After semiconductor processing, surface defect inspection is performed to check for surface defects that may occur on the surface of the wafer during the process. The surface defect inspection is an inspection for checking scratches, particles, pattern abnormalities, and the like on the wafer surface.
As a method of inspecting the surface defect of a wafer, there exist an automatic inspection method using expensive automated equipment, and the manual inspection method which an operator visually inspects. In general, when the surface defect of the wafer is manually inspected after the semiconductor process, it is not necessary to have expensive automation equipment, and thus the equipment cost is relatively reduced. However, in the case of manual inspection, the user manually operates the microscope's manual stage and visually checks the defects of each cell, and in order to check the coordinates of the cells identified as defective, the number of cells must be counted one by one. The inspection process takes a lot of time. In addition, this results in a problem that results in an increase in the price of the semiconductor chip.
Disclosure of Invention An object of the present invention is to provide a wafer inspection system and method for minimizing time delay and improving inspection reliability in inspecting wafer defects.
A wafer inspection system according to an aspect of the present invention, the input unit; A stage on which the wafer is seated; A stage driver which controls the movement of the stage; A microscope mounted on top of the wafer to inspect the wafer; A camera for photographing at least one cell identified through the microscope; An image processor for image-processing and outputting an image of the at least one cell photographed through the camera; A memory that stores path information for sequentially moving the stage and a wafer map corresponding to the wafer; A display unit configured to display an image of the at least one cell photographed through the camera and an image of the wafer map; And controlling the stage driving unit to sequentially move the stage based on the path information when the macro is selected through the input unit, and when the specific cell of the image of the wafer map is selected as defective through the input unit, the wafer map. And a controller for storing the specific cell as defective.
According to the present invention, in the wafer inspection method, the inspection path is set to a macro in advance, and the surface defect inspection of the wafer is performed by using the set macro, so that the user conducting the inspection does not need to manually operate the stage for the inspection progress. In addition, since the coordinate information of the cell to be inspected is already registered in the macro, even if a bad cell occurs, there is no need to count the cells one by one to check the position of the cell, thereby reducing the delay time during the inspection process. This reduces the cost of inspection.
1 is a block diagram illustrating a wafer inspection system according to an exemplary embodiment of the present invention.
2 illustrates an example of arranging a calibration switch in a wafer inspection system according to an exemplary embodiment.
3 is a flowchart illustrating a wafer inspection method of the wafer inspection system according to an exemplary embodiment.
4 illustrates an example of displaying a wafer map image in a wafer inspection system according to an exemplary embodiment.
5 to 6 illustrate examples of a user interface that supports a user to directly select an inspection target cell in a wafer inspection system according to an exemplary embodiment.
7 is a flowchart illustrating a method of selecting an inspection target cell using a macro in a wafer inspection system according to an exemplary embodiment.
8 illustrates an example of a user interface for controlling macro execution in a wafer inspection system according to an embodiment of the present disclosure.
9 is a flowchart illustrating a macro generation method of the wafer inspection system according to an exemplary embodiment.
10 illustrates an example of a user interface for generating a macro in a wafer inspection system according to an embodiment of the present invention.
11 illustrates examples of macros generated by a user in a wafer inspection system according to an embodiment of the present invention.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.
Throughout the specification, when a part is said to "include" a certain component, it means that it can further include other components, except to exclude other components unless otherwise stated.
It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.
In addition, the suffix "module" and " part "for constituent elements used in the following description are given or mixed in consideration of ease of specification, and do not have their own meaning or role.
Hereinafter, a wafer inspection system and a method thereof according to an embodiment of the present invention will be described with reference to the accompanying drawings.
In this document, a wafer inspection system refers to a system for inspecting surface defects of a wafer in a semiconductor process.
Hereinafter, an operation of a wafer inspection system for performing a wafer inspection method according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.
1 is a block diagram illustrating a wafer inspection system according to an exemplary embodiment of the present invention. 2 illustrates an example of arranging a calibration switch in a wafer inspection system according to an exemplary embodiment.
Referring to FIG. 1, the
The
Meanwhile, according to an embodiment of the present disclosure, a plurality of
Each
To this end, the wafer needs to be seated correctly at a predetermined position on the
Referring back to FIG. 1, the
In addition, when the correction switch is recognized while driving the
The
The
In the following, for convenience of description, the area of the wafer which can be acquired through the microscope by being positioned at the inspection position is referred to as an 'inspection region'. In addition, a cell included in the inspection area and capable of acquiring an image through a microscope is referred to as a 'test cell'. On the other hand, when the inspection area that can be inspected at one time is larger than one cell, one or more cells may be included in the inspection area.
The
The
In addition, the
In addition, the
Here, each macro includes path information for automatically moving the
The
The
Meanwhile, when the
The
The
Here, the specific area of the wafer to be placed at the inspection position may be directly selected by the user through the
Meanwhile, when the correction switches 211, 212, 213, and 214 are recognized by the
In addition, the
In addition, the
On the other hand, the
Hereinafter, the wafer inspection method of the wafer inspection system will be described in detail with reference to FIGS. 3 to 11.
3 is a flowchart illustrating a wafer inspection method according to an embodiment of the present invention. 4 illustrates an example of displaying a wafer map image.
Referring to FIG. 3, a wafer to be subjected to a surface defect inspection is seated on an upper stage of the stage 110 (S101).
Thereafter, the
Referring to FIG. 4, the
On the other hand, when an electro die sorting (EDS) test that inspects electrical characteristics of each semiconductor chip implemented on the wafer prior to the wafer surface defect inspection is performed, the wafer map image may reflect the EDS test result. . That is, the cells determined to be defective through the EDS inspection may be marked and displayed as defective cells on the wafer map image. In this case, the cell determined as defective through the surface defect inspection may be further marked on the wafer map image on which the defective cell by the EDS inspection is marked.
Referring again to FIG. 3, the
When the driving of the
For example, the
Also, for example, the
Accordingly, the user can intuitively grasp where the cell being inspected is located on the wafer.
Referring back to FIG. 3, when the user inputs a specific cell currently being inspected as a defective cell using the wafer map image (S105), the
In addition, based on the obtained coordinate information, the corresponding cell is registered as a defective cell in the wafer map (S106).
For example, the
In addition, the
In addition, in step S106, the
Meanwhile, the steps S103 to S107 may be repeatedly performed until the surface defect inspection on the wafer currently seated on the
When the surface defect inspection on the wafer currently seated on the
Hereinafter, a method of selecting an inspection region from a wafer in step S103 of FIG. 3 will be described in detail with reference to FIGS. 5 through 8.
According to an embodiment of the present disclosure, the inspection area may be directly selected by the user through the
When the user selects a specific cell on the wafer map image displayed on the screen using a mouse, the
In addition, when the user directly inputs coordinate information of a specific cell through the
As described above, when the inspection region is selected using the coordinates of a specific cell, the inspection region may be set such that the selected cell is located at the center of the inspection region.
If the user inputs a moving direction through the
5 through 6 illustrate examples of a user interface for directly selecting a test area by a user.
Referring to FIG. 5, the
Referring to FIG. 6, the
In addition, according to an embodiment of the present disclosure, the inspection region may be automatically selected by a predetermined macro in step S103.
When the user selects any one of the macros previously stored in the
7 is a flowchart illustrating a method of selecting an inspection area using a macro.
Referring to FIG. 7, the
Thereafter, when the execution of the selected macro is requested (S202), the
According to an embodiment of the present disclosure, each macro includes path information for automatically moving the
Therefore, in step S203, the
On the other hand, in step S203, the
Again, referring to FIG. 7, if the execution stop is requested through the
8 illustrates an example of a user interface for controlling macro execution.
Referring to FIG. 8, the
As described above, when inspecting a wafer using a macro, a user may automatically move the
Meanwhile, according to one embodiment of the present invention, a macro for wafer inspection may be set by a user.
Hereinafter, a method of generating a macro will be described in detail with reference to FIGS. 9 to 11.
9 is a flowchart illustrating a macro generation method according to an embodiment of the present invention. In addition, FIG. 10 illustrates an example of a user interface for generating a macro, and FIG. 11 illustrates examples of a macro generated by a user.
Referring to FIG. 9, the
Using FIG. 10 as an example, the
9, when the macro setting is started by the user (S302), the
The
When the end of the macro setting is requested, the macro setting is terminated and a macro including cells added up to now is stored in the memory 150 (S306).
In step S303, the user can select a cell added to the macro by various methods.
For example, a user may sequentially register at least one cell to a macro by using
Also, for example, the user may select cells added to the macro by sequentially selecting at least one cell on the wafer map image using a mouse or the like.
11 shows examples of macros set by a user based on the above-described methods.
According to the wafer inspection method according to an embodiment of the present invention described above, by setting the inspection path to a macro in advance and performing a surface defect inspection of the wafer using the set macro, the user performing the inspection stages for the inspection progress. There is no need to manipulate it manually. In addition, since the coordinate information of the inspection target cell is already registered in the macro, even if a bad cell occurs, it is not necessary to count the cell one by one to check the position of the corresponding cell.
Therefore, there is an effect of reducing the delay time in the inspection process, thereby reducing the inspection cost.
The embodiments of the present invention described above are not only implemented by the apparatus and method but may be implemented through a program for realizing the function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded, The embodiments can be easily implemented by those skilled in the art from the description of the embodiments described above.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. The present invention is not limited to the drawings, and all or some of the embodiments may be selectively combined so that various modifications may be made.
Claims (8)
A stage on which the wafer is seated;
A stage driver which controls the movement of the stage;
A microscope mounted on top of the wafer to inspect the wafer;
A camera for photographing at least one cell identified through the microscope;
An image processor for image-processing and outputting an image of the at least one cell photographed through the camera;
A memory that stores path information for sequentially moving the stage and a wafer map corresponding to the wafer;
A display unit configured to display an image of the at least one cell photographed through the camera and an image of the wafer map; And
When the macro is selected through the input unit, the stage driving unit is controlled to sequentially move the stage based on the path information, and when the specific cell of the image of the wafer map is selected as defective through the input unit, Control unit for storing the specific cell as defective
Wafer inspection system comprising a.
The path information includes coordinate information of a plurality of cells for moving the stage,
When the controller enters the macro generation mode, the controller generates the macro based on the coordinate information and the selection order of a plurality of cells sequentially selected from the image of the wafer map.
The stage has a plurality of correction switches respectively corresponding to different X-axis coordinates or Y-axis coordinates,
The controller may be further configured to recognize the correction switch of any one of the plurality of correction switches through the stage driver, and compare the wafer with a cell located at a current test position and an X-axis coordinate or a Y-axis coordinate corresponding to the correction switch. Wafer inspection system, characterized in that to correct the coordinate information of a plurality of cells implemented on the image.
The control unit is a wafer inspection system, characterized in that for marking the image of the wafer map in a different color than the other cells recognized as a normal normal input cell.
And the control unit controls the display unit to enlarge and display only an area corresponding to the at least one cell in the image of the wafer map in synchronization with at least one cell identified through the microscope.
And the control unit controls the stage driving unit to move the selected cell to an inspection position when one cell is selected from the image of the wafer map through the input unit.
And the controller controls the stage driver to move a cell corresponding to the input coordinate information to a test position when coordinate information is input through the input unit.
When the moving direction is selected through the input unit, the control unit controls the stage driving unit to move a cell corresponding to the selected moving direction to a test position among a plurality of cells neighboring a cell currently being inspected. system.
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KR1020120019688A KR101266270B1 (en) | 2012-02-27 | 2012-02-27 | Wafer inspection system and wager inspection method thereof |
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KR1020120019688A KR101266270B1 (en) | 2012-02-27 | 2012-02-27 | Wafer inspection system and wager inspection method thereof |
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