JP3808320B2 - Pattern inspection apparatus and pattern inspection method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an inspection apparatus and a pattern inspection method for inspecting patterns on a large number of chips formed on a substrate such as a semiconductor wafer.
[0002]
[Prior art]
In a large number of chips formed on a semiconductor wafer, for example, a repeated pattern region in which a pattern having the same shape is repeatedly formed like a charge storage portion in a memory, and a random pattern region in which other patterns are formed And exist. When such a pattern in the chip is inspected, different inspection methods are used for the repeated pattern region and the random pattern region, respectively.
[0003]
That is, for the random pattern region, a chip comparison inspection is adopted in which a pattern defect is detected by comparing corresponding patterns between a plurality of adjacent or adjacent chips. This chip comparison inspection is an inspection method called a die comparison inspection or a random comparison inspection. In this chip comparison inspection, since the patterns arranged at two relatively spaced positions on the semiconductor wafer are comparatively inspected, it is necessary to take a relatively large tolerance.
[0004]
On the other hand, for the repetitive pattern region, a cell comparison inspection is adopted in which a pattern defect is detected by comparing repetitive patterns adjacent or close to each other in the same chip (see Japanese Patent Publication No. 6-56293). ). This cell comparison inspection is an inspection method also called an array comparison inspection. In this cell comparison inspection, since the patterns to be compared are close in distance, it is possible to execute a highly accurate inspection.
[0005]
For this reason, in the case where pattern inspection is performed on both the repeated pattern region and the random pattern region on a chip formed on a semiconductor wafer, a pattern inspection apparatus that performs die comparison inspection and a pattern that performs cell comparison inspection Both pattern inspection apparatus and inspection apparatus are used. In some cases, an inspection apparatus having inspection modes for both die comparison inspection and cell comparison inspection is used, and inspection is performed by switching the mode corresponding to each of the repeated pattern region or the random pattern region.
[0006]
In Japanese Patent No. 2976550, a cell comparison is performed on an image obtained by imaging a chip, thereby setting a cell-comparable portion and a cell-noncomparable portion in the image region. Discloses a pattern defect inspection method in which cell comparison inspection is performed and chip comparison inspection is performed on a portion where cell comparison is impossible.
[0007]
[Problems to be solved by the invention]
FIG. 4 is an explanatory diagram showing an operation of detecting a defect using cell comparison inspection.
[0008]
When performing the cell comparison inspection, the repeated pattern A and the repeated pattern B are compared, and the repeated pattern B and the repeated pattern C are compared. The defect 100 unique to the repetitive pattern B is detected by ANDing the comparison result 101 between the repetitive pattern A and the repetitive pattern B and the comparison result 102 between the repetitive pattern B and the repetitive pattern C.
[0009]
According to this cell comparison inspection, it is possible to obtain a highly accurate inspection result for a minute defect formed in a repeated pattern, but it is impossible to detect a defect over two cycles or more of the repeated pattern. There's a problem.
[0010]
For example, when relatively large particles are present on the repetitive pattern, as shown in FIG. 5, when both the repetitive pattern B and the repetitive pattern C are defective, the repetitive pattern A and the repetitive pattern B Even if the comparison result 103 of AND and the comparison result 104 of the repeated pattern B and the repeated pattern C are ANDed, it is recognized that there is no defect in the repeated pattern B.
[0011]
For this reason, in the cell comparison inspection, a relatively large defect over two cycles or more of the repeated pattern as shown in FIG. 5 cannot be detected.
[0012]
Such a problem is a phenomenon that occurs in the pattern defect inspection method described in the above-mentioned Japanese Patent No. 2976550 as well. That is, in the pattern defect inspection method described in the above-mentioned Japanese Patent No. 2976550, a relatively large defect such as a two or more periods of such a repetitive pattern sets a cell-comparable portion and a cell-comparable portion. If this occurs, this large defect portion is recognized as a cell-comparable portion, and a relatively large defect that extends over two cycles of such a repetitive pattern exists during the cell comparison inspection. In such a case, it is recognized that there is no defect.
[0013]
The present invention has been made to solve the above-described problems, and an object thereof is to provide a pattern inspection apparatus and a pattern inspection method capable of accurately detecting a relatively large defect that has occurred in a repeated pattern region.
[0014]
[Means for Solving the Problems]
The invention according to claim 1 is an inspection apparatus for inspecting a repetitive pattern of a repetitive pattern area in one chip in a large number of chips formed on a substrate , wherein the repetitive pattern area is repeated in the same chip. Pattern defects are detected by performing cell comparison for comparing patterns with each other and chip comparison for comparing corresponding patterns among a plurality of chips.
[0015]
The invention according to claim 2 is an inspection apparatus for inspecting patterns on a large number of chips formed on a substrate, and includes a substrate support means for supporting the substrate, and an imaging means for capturing an image of the chip. the substrate and the supporting means and the shooting moving means for relatively moving the shadow means, said image storage means for storing the image of the photographed chip by the imaging means, the region on one chip taken by the imaging means storing Oite, an area setting means for setting a random pattern region repetitive pattern area and random pattern repeating pattern is formed is formed and a repetitive pattern region and a random pattern region set by said region setting means The area storage means and the repeated pattern area stored in the area storage means are repeated in the same chip. Cell comparison inspection means for performing cell comparison to detect pattern defects by comparing patterns with each other, and between repeated pattern areas and random pattern areas stored in the area storage means, between a plurality of chips Chip comparison inspection means for executing chip comparison for detecting pattern defects by comparing corresponding patterns with each other.
[0016]
Invention of claim 3, there is provided an inspection method for inspecting a pattern in a large number of chips formed on a substrate, Oite the area on one chip, repeated pattern region and random repeating pattern is formed For the area setting process to set the random pattern area where the pattern is formed and the repeated pattern area set in the area setting process, the pattern defect is detected by comparing the repeated patterns in the same chip with each other. Performing both cell comparison and chip comparison to detect pattern defects by comparing corresponding patterns among multiple chips, and for the random pattern region set in the region setting step, A chip that detects pattern defects by comparing corresponding patterns between multiple chips. And a defect detection step for performing a loop comparison.
[0017]
According to a fourth aspect of the present invention, in the pattern inspection method according to the third aspect , in the area setting step, the pattern on the chip is enlarged and displayed by photographing the pattern on the chip, and the enlarged display is performed. A repeated pattern area in which a repeated pattern is formed using the formed pattern and a random pattern area in which a random pattern is formed are set.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic diagram of a pattern inspection apparatus according to the present invention.
[0019]
The pattern inspection apparatus includes a substrate support table 11 that supports a substrate W made of a semiconductor wafer, an actuator 12 that moves the substrate support table 11 in the X direction, and a substrate support table 11 that moves the substrate support table 11 in the Y direction. An actuator 13, a table driving unit 14 for driving the substrate support table 11 via these actuators 12, 13, and a camera 15 for taking an image of a chip formed on the substrate W supported by the substrate support table 11. And an image processing unit 20 to be described later, and a control unit 17 that controls the entire pattern inspection apparatus. The controller 17 is connected to a keyboard 18 that functions as an area setting unit and a CRT 19 that functions as an enlarged display unit when setting an area to be described later.
[0020]
The image processing unit 20 also includes a chip comparison inspection unit 21 that performs a chip comparison inspection, an image memory 22 that temporarily stores an image captured by the camera 15 during the chip comparison inspection, and a cell comparison that performs a cell comparison inspection. The inspection unit 23, the image memory 24 that temporarily stores an image taken by the camera 15 at the time of the cell comparison inspection, the inspection result by the chip comparison inspection unit 21 and the inspection result by the cell comparison inspection unit 23 are integrated into a final result. An integrated determination unit 25 that determines whether or not there is a defect, and an area memory 26 that stores a repetitive pattern area and a random pattern area set by using the keyboard 18 or the like. The chip comparison inspection unit 21, the image memory 22, the cell comparison inspection unit 23, and the image memory 24 in the image processing unit 20 are connected to the camera 15 via the A / D converter 16.
[0021]
Instead of separately providing an image memory 22 that temporarily stores an image captured by the camera 15 during chip comparison inspection and an image memory 24 that temporarily stores an image captured by the camera 15 during cell comparison inspection. An image may be temporarily stored using one image memory.
[0022]
When inspecting the pattern of the substrate W in the pattern inspection apparatus having such a configuration, first, a region setting step of setting a repetitive pattern region in which a repetitive pattern is formed and a random pattern region in which a random pattern is formed Execute.
[0023]
In this area setting process, the camera 15 captures a pattern on the chip formed on the surface of the substrate W, and displays an enlarged image of the pattern on the chip on the CRT 19.
[0024]
FIG. 2 is an explanatory diagram schematically showing an image of the pattern on the chip 31 enlarged and displayed on the CRT 19 in this way.
[0025]
In this embodiment, it is assumed that a region 32 in which a random pattern is formed and regions 33 and 34 in which a repeated pattern is formed are formed on the chip 31.
[0026]
Next, using this enlarged screen, the operator confirms this enlarged display screen, and sets these areas as a random pattern area 32 in which a random pattern is formed and repeated pattern areas 33 and 34 in which a repeated pattern is formed. To do. In this area setting step, the area is set using the keyboard 18 connected to the control unit 17. The random pattern region 32 and the repeated pattern regions 33 and 34 set in this region setting step are stored in the region memory 26 in the image processing unit 20.
[0027]
This region setting step may be executed by the operator using the keyboard 18 or a mouse (not shown). For example, the control unit 17 may use a method described in Japanese Patent No. 2976550. May be configured to execute automatically.
[0028]
Based on the random pattern area 32 and the repeated pattern areas 33 and 34 stored in the area memory 26, an area to be subjected to chip comparison inspection and an area to be subjected to cell comparison inspection are determined. That is, as shown in FIG. 3A, in this inspection method determination step, first, a flag (reference numeral 1 shown in FIG. 3) for performing the chip comparison inspection is set for the random pattern region 32. A flag (reference numeral 1 shown in FIG. 3) for performing cell comparison is set for the repeated pattern areas 33 and 34. Then, as shown in FIG. 3B, a flag for performing chip comparison corresponding to the repeated pattern regions 33 and 34 is set by copying a flag to be subjected to cell comparison inspection. These pieces of information are stored in the area memory 26 in the image processing unit 20.
[0029]
The inspection method determination step may be configured to be automatically executed by the control unit 17 or may be executed by the operator using the keyboard 18 or a mouse (not shown).
[0030]
When the above steps are completed, pattern inspection is executed. In this pattern inspection process, the chip comparison inspection unit 21 and the cell comparison are set based on the information of the area to be subjected to the chip comparison inspection and the area to be subjected to the cell comparison inspection which are set in the inspection method determination process and stored in the area memory 26. The inspection unit 23 is controlled, and both the cell comparison inspection and the chip comparison inspection are executed for the repeated pattern regions 33 and 34, and the chip comparison inspection is executed for the random pattern region 32.
[0031]
In this pattern inspection process, the chip comparison inspection unit 21 performs a chip comparison inspection on the random pattern region 32 and the repeated pattern regions 33 and 34. In this chip comparison inspection unit 21, an image of a pattern of a certain area in the previous chip 31 photographed by the camera 15 and stored in the image memory 22, and a corresponding area in the current chip 31 photographed by the camera 15. The presence / absence of a defect is inspected by sequentially and sequentially comparing the pattern with the image.
[0032]
In the pattern inspection process, the cell comparison inspection unit 23 performs cell comparison inspection on the repeated pattern regions 33 and 34. In this cell comparison inspection unit 23, the comparison between the previous repetitive pattern image captured by the camera 15 and stored in the image memory 24 and the current repetitive pattern image captured by the camera 15 are successively performed successively. Execution is inspected for defects.
[0033]
Here, in the case where a relatively large defect has occurred in the repeated pattern regions 33 and 34, as shown in FIG. 5, the defect cannot be detected by the cell comparison inspection in the cell comparison inspection unit 23. However, such a relatively large defect is detected during the chip comparison inspection in the chip comparison inspection unit 21. At this time, such a relatively large defect can be reliably detected even at the time of a chip comparison inspection that requires a relatively large tolerance, and no detection error occurs.
[0034]
In the above-described chip comparison inspection and cell comparison inspection, the table driving unit 14 drives the substrate support table 11 via the actuators 12 and 13 and moves the substrate W supported thereon relative to the camera 15. Thus, the process is performed on the entire region where the chip 31 is formed on the surface of the substrate W.
[0035]
Thereafter, the inspection result by the chip comparison inspection unit 21 and the inspection result by the cell comparison inspection unit 23 are integrated by the integration determination unit 25, and the inspection result for the entire chip formed on the substrate W is determined. In the integration determination unit 25, the results are integrated by ORing the inspection result by the chip comparison inspection unit 21 and the inspection result by the cell comparison inspection unit 23.
[0036]
Then, the inspection result is displayed on the CRT 19 via the control unit 17.
[0037]
As described above, according to the pattern inspection apparatus of this embodiment, both the cell comparison inspection and the chip comparison inspection are performed on the repeated pattern regions 33 and 34, and the chip is applied to the random pattern region 32. Since the comparative inspection is performed, even when a relatively large defect has occurred in the repeated pattern regions 33 and 34, this defect can be accurately detected.
[0038]
In the embodiment described above, in the region setting step, both the random pattern region 32 in which the random pattern is formed and the repeated pattern regions 33 and 34 in which the repeated pattern is formed are set. Only the repeated pattern areas 33 and 34 may be set, and all other areas may be recognized as random pattern areas. In the case of adopting such a configuration, the chip comparison inspection is executed for the entire area on the chip 31, and the cell comparison inspection is executed for the repeated pattern areas 33 and 34 in the chip 31. Become.
[0039]
【The invention's effect】
According to the first aspect of the present invention, a cell comparison for comparing repeated patterns in the same chip with each other and a chip comparison for comparing corresponding patterns among a plurality of chips are performed on the repeated pattern region. Thus, since the defect of the pattern is detected, it is possible to accurately detect a relatively large defect that has repeatedly occurred in the pattern area.
[0040]
According to the second and third aspects of the invention, both the cell comparison and the chip comparison are performed for the repeated pattern region, and the chip comparison is performed for the random pattern region. When inspecting defects in the repeated pattern region and the random pattern region, it is possible to accurately detect a relatively large defect generated in the repeated pattern region.
[0041]
According to the fourth aspect of the present invention, the pattern is enlarged and displayed on the display device by photographing the pattern on the chip, and the repeated pattern area is formed by using the enlarged and displayed pattern. Since the random pattern area in which the random pattern is formed is set, the repeated pattern area and the random pattern area can be easily set.
[Brief description of the drawings]
FIG. 1 is a schematic diagram of a pattern inspection apparatus according to the present invention.
FIG. 2 is an explanatory diagram schematically showing an image of a pattern on a chip 31 enlarged and displayed on a CRT 19;
FIG. 3 is an explanatory diagram showing a region to be subjected to chip comparison inspection and a region to be subjected to cell comparison inspection;
FIG. 4 is an explanatory diagram showing an operation of detecting a defect using cell comparison inspection.
FIG. 5 is an explanatory diagram showing an operation for detecting a defect using cell comparison inspection;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 Board | substrate support table 12 Actuator 13 Actuator 14 Table drive part 15 Camera 16 A / D converter 17 Control part 18 Keyboard 19 CRT
20 Image processing unit 21 Chip comparison inspection unit 22 Image memory 23 Cell comparison inspection unit 24 Image memory 25 Integrated determination unit 26 Area memory W Substrate

Claims (4)

An inspection apparatus for inspecting a repetitive pattern of a repetitive pattern area in one chip in a large number of chips formed on a substrate,
Pattern defects are detected by performing cell comparison for comparing repeated patterns in the same chip with each other and chip comparison for comparing corresponding patterns among a plurality of chips with respect to the repeated pattern area. Pattern inspection device. An inspection apparatus for inspecting patterns on a large number of chips formed on a substrate,
Substrate support means for supporting the substrate;
Photographing means for photographing an image of the chip;
Moving means for relatively moving the shadow unit shooting the substrate and the support means,
Image storage means for storing an image of the chip photographed by the photographing means;
An area setting means for setting fraud and mitigating risk and random pattern region repetitive pattern repeated pattern region and a random pattern formed is formed in the region on one chip taken by the imaging means,
Area storage means for storing the repeated pattern area and the random pattern area set by the area setting means;
Cell comparison inspection means for performing cell comparison for detecting a pattern defect by comparing the repeated patterns in the same chip with each other for the repeated pattern area stored in the area storage means;
Chip comparison inspection means for performing chip comparison to detect pattern defects by comparing corresponding patterns between a plurality of chips against the repeated pattern area and random pattern area stored in the area storage means;
A pattern inspection apparatus comprising: An inspection method for inspecting patterns on a large number of chips formed on a substrate,
An area setting step of setting fraud and mitigating risk and random pattern region repetitive pattern repeated pattern region and a random pattern formed is formed in the region on one chip,
For the repeated pattern region set in the region setting step, cell comparison for detecting pattern defects by comparing repeated patterns in the same chip with each other, and corresponding patterns among a plurality of chips are compared. In addition to performing both chip comparison to detect pattern defects, and for random pattern areas set in the area setting step, pattern defects are compared by comparing corresponding patterns among a plurality of chips. A defect detection step of performing chip comparison to detect
A pattern inspection method comprising: The pattern inspection method according to claim 3 ,
In the region setting step, the pattern is enlarged on the display device by photographing the pattern on the chip, and the repetitive pattern region and the random pattern in which the repetitive pattern is formed using the enlarged display pattern are obtained. A pattern inspection method for setting a formed random pattern region.

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