KR101264708B1 - Light quantity detecting circuit for liquid crystal display device and a method for fabricating the same - Google Patents

Abstract

The present invention relates to a light amount detection circuit of a liquid crystal display device and a method of manufacturing the same that can prevent the light amount detection signal from being distorted to improve reliability of light amount detection. A light detecting element for generating a light quantity detection signal, a supply line for supplying the plurality of clock signals, a detection signal output line for outputting the light quantity detection signal to the outside, and at least one line of the supply line and the detection signal output line; And a first dummy metal pattern formed by overlapping the first insulating layer therebetween.

A light amount detecting circuit, a light detecting element, first and second dummy metal patterns,

Description

Light quantity detecting circuit for liquid crystal display device and a method for fabricating the same

1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram showing the light quantity detecting circuit shown in FIG.

3 is a process sectional view showing the manufacturing method of the light quantity detecting circuit according to the first embodiment of the present invention;

4 is a process sectional view showing the manufacturing method of the light quantity detecting circuit according to the second embodiment of the present invention;

＊ Description of symbols for main parts of the drawings ＊

12: light quantity detection circuit 32, 42: gate electrode

40, 51: first dummy metal pattern 35, 45: source electrode

50b: second dummy metal pattern 32, 46: drain electrode

33,43: first insulating film 39,49: second insulating film

CLK1, CLK2: first and second clock signals VS: light quantity detection signal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a light amount detection circuit of a liquid crystal display device and a method of manufacturing the same, which can prevent the light amount detection signal from being distorted to improve reliability of the light amount detection.

Recently, various flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have emerged. Examples of such flat panel display devices include a liquid crystal display, a field emission display, a plasma display panel, and a light emitting display.

Among the flat panel display devices, the liquid crystal display device displays an image by adjusting light transmittance of the liquid crystal cells according to a video signal. An active matrix type liquid crystal display device in which switching elements are formed for each liquid crystal cell is suitable for displaying moving images. In this case, a thin film transistor is mainly used as the switching element. Such a liquid crystal display includes a back light unit that irradiates light of constant brightness to a liquid crystal cell in order to display an image.

In the conventional liquid crystal display, power consumption is increased due to the backlight which generates light having a constant brightness. In other words, the liquid crystal display maintains the brightness of the liquid crystal cell constant regardless of the brightness of the surrounding environment, thereby increasing the power consumption of the backlight. Accordingly, in order to reduce the power consumption of the backlight, a light amount detection circuit may be provided to adjust brightness of the backlight according to the light amount detection signal.

However, a problem arises in that the light quantity detection signal generated by the light quantity detection circuit is distorted by other signals in the vicinity in the process of being transmitted to the backlight unit. For example, when the light amount detection circuit is provided in the liquid crystal panel in which the liquid crystal cells are formed, the light amount detection reliability is deteriorated because the light amount detection signal is distorted by interference due to a gate signal, a data signal, or a common voltage.

An object of the present invention is to provide a light amount detection circuit of a liquid crystal display device and a method of manufacturing the same, which can improve the reliability of light amount detection by preventing the light amount detection signal from being distorted.

The light amount detecting circuit of the liquid crystal display according to the embodiment of the present invention for achieving the above object is a light detecting element for generating a light amount detection signal corresponding to the amount of light incident from the outside in accordance with a plurality of clock signals, A first dummy metal formed by overlapping a supply line for supplying a clock signal, a detection signal output line for outputting the light quantity detection signal to the outside, and at least one of the supply line and the detection signal output line with a first insulating film interposed therebetween It characterized in that it comprises a pattern.

In addition, the method for manufacturing a light amount detection circuit of a liquid crystal display according to an embodiment of the present invention for achieving the above object is a light detection element for generating a light amount detection signal corresponding to the amount of light incident from the outside in accordance with a plurality of clock signals Forming a plurality of clock signals; forming a supply line for supplying the plurality of clock signals; forming a detection signal output line for externally outputting the light quantity detection signal; and at least one of the supply line and the detection signal output line. And forming a first dummy metal pattern such that the first dummy metal pattern overlaps with the line of the first insulating film.

Hereinafter, a light amount detecting circuit of the liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

The liquid crystal display shown in FIG. 1 includes a liquid crystal panel 2 including a liquid crystal cell formed for each region defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, and a gate line ( A gate driver 4 for sequentially supplying scan pulses to the GL1 to GLn, a data driver 6 for supplying an image signal to the data lines DL1 to DLm in synchronization with the scan pulse, and input data from the outside ( A timing controller 8 for aligning and supplying the RGB to the data driver 6 and controlling the gate and the data drivers 4 and 6, a backlight 10 for irradiating light to the liquid crystal panel 2, The backlight 10 is driven in accordance with the light amount detection circuit 12 that generates the light amount detection signal VS corresponding to the external brightness of the liquid crystal panel 2, and the backlight 10 is driven to the liquid crystal panel 2 by the light amount detection signal VS. Back light driver 14 for adjusting the brightness of the irradiated light .

The liquid crystal panel 2 includes a transistor array substrate and a color filter array substrate bonded to each other, a spacer for maintaining a constant cell gap between the two array substrates, and a liquid crystal layer filled in the liquid crystal space provided by the spacer.

The color filter array substrate includes a color filter, a common electrode, a black matrix, and the like. Here, the common electrode may be formed on the transistor array substrate.

The transistor array substrate is formed in a region defined by m data lines DL1 through DLm and n gate lines GL1 through GLn, and is connected to a gate line and a data line, and a liquid crystal cell connected to the thin film transistor. It includes.

The thin film transistor supplies an image signal from the data line DL to the liquid crystal cell in response to a scan pulse from the gate lines GL1 to GLn.

Since the liquid crystal cell is composed of a common electrode and a pixel electrode connected to the thin film transistor, the liquid crystal cell may be equivalently represented as a liquid crystal capacitor Clc. In addition, the liquid crystal cell includes a storage capacitor Cst for maintaining the image signal charged in the liquid crystal capacitor Clc until the next image signal is charged.

The timing controller 8 arranges the input data RGB from the outside so as to be suitable for driving the liquid crystal panel 2, and supplies the input data RGB to the data driver 6. In addition, the timing controller 8 receives the gate and data control signals GCS and DCS by using a dot clock DCLK, a data enable signal DE, and horizontal and vertical synchronization signals Hsync and Vsync. It generates and controls the driving timing of each of the gate and data driver 4,6.

The gate driver 4 sequentially generates scan pulses according to the gate control signal GCS from the timing controller 8 and supplies them to the gate lines GL1 to GLn.

The data driver 6 converts the data Data supplied from the timing controller 8 into an image signal according to the data control signal DCS supplied from the timing controller 8 to scan pulses to the gate lines GL1 to GLn. Each horizontal period to which is supplied is supplied an image signal for one horizontal line to the data lines DL1 to DLm. At this time, the data driver 6 inverts the polarity of the image signal supplied to the data lines DL1 to DLm in response to the polarity control signal from the timing controller 8.

The light quantity detecting circuit 12 is formed in the liquid crystal panel 2 together with the formation of the thin film transistor TFT of each liquid crystal cell to generate a light quantity detecting signal VS corresponding to the external brightness of the liquid crystal panel 2. The generated light amount detection signal VS is supplied to the backlight driver 14. In this case, all of the components of the light amount detection circuit 12 may be formed in the liquid crystal panel 2, or only some of the components may be formed in the liquid crystal panel 2. In addition, the light amount detection circuit 12 may be separately attached to the periphery of the liquid crystal panel 2.

The backlight driver 14 drives the backlight 10 in accordance with the light amount detection signal VS from the light amount detection circuit 12. More specifically, the backlight driver 14 generates the backlight driving voltage VL according to the light amount detection signal VS and uses the same to drive the backlight 10. Therefore, the backlight driver 14 may further include a backlight driving voltage generator that generates the backlight driving voltage VL.

The backlight 10 generates light according to the backlight driving voltage VL supplied from the backlight driver 14 and irradiates the liquid crystal panel 2. To this end, the backlight 10 includes at least one lamp that is turned on by the backlight driving voltage VL and generates light, or at least one that emits light by the backlight driving voltage VL and generates light. It includes a light emitting diode.

FIG. 2 is an equivalent circuit diagram illustrating the light amount detecting circuit shown in FIG. 1.

The light amount detection circuit 12 shown in FIG. 2 generates a light amount detection signal Tr that generates a light amount detection signal VS corresponding to the light amount from the outside according to the first clock signal CLK1 and the second clock signal CLK2. ), The first supply line CL1 for supplying the first clock signal CLK1 to the source electrode of the photodetecting device Tr, and the second clock signal CLK2 for supplying the gate electrode of the photodetecting device Tr. And a detection signal output line VSSL for transmitting the light quantity detection signal VS from the second supply line CL2 and the light detection element Tr to the outside.

The first clock signal CLK1 is a reference signal for detecting the amount of light and supplies a constant reference voltage and current to the source electrode of the photodetecting element Tr. For example, the first clock signal CLK1 may be supplied with a different voltage size depending on the channel size of the photodetecting device Tr, but may be set to have a voltage size of 5V to 25V. In addition, the first clock signal CLK1 may be supplied such that the high level voltage and the low level voltage are periodically inverted to prevent deterioration of the photodetector Tr or to prevent the formation of a cap. For example, it may be repeatedly supplied with the same pulse width so that the high period for supplying the high level voltage of 20V and the low period for supplying the low level voltage of 0V are the same. In this case, the high period and the low period may be periodically supplied to have different periods.

The second clock signal CLK2 is a switching signal for setting the light amount detection period to switch the light detection element Tr in the light amount detection period. The second clock signal CLK2 is supplied to the gate electrode of the light detecting element Tr such that the high level voltage and the low level voltage are inverted in accordance with the light amount detection period. For example, the light detection element Tr is turned on by supplying a voltage having a level set to any one of 5V to 25V between the light quantity detection period, that is, the light quantity detection signal VS generator, to turn on the photodetecting element Tr. The light quantity detection signal VS is outputted. The second clock signal CLK2 may be supplied periodically so that the high period and the low period have the same pulse width, or may be supplied such that the high period and the low period have different pulse widths.

The photodetecting element Tr is an element for detecting the amount of light. Specifically, when the first clock signal CLK1, which means a reference voltage, is input to the source electrode, the photodetector Tr generates an optical voltage or a photocurrent corresponding to an external light amount. The light voltage or the light current generated corresponding to the light amount during the turn-on period according to the second clock signal CLK2 is output to the drain electrode as the light amount detection signal VS. Here, the light detecting element Tr may be formed of a thin film transistor of N-MOS or PMOS having a wide channel portion, but only a case of forming the thin film transistor of the N-MOS thin film transistor will be described below. If the thin film transistor is formed of a P-MOS, the light amount may be detected by supplying the first and second clock signals CLK1 and CLK2 to be inverted from the case of the N-MOS. In addition, the amount of light may be detected by the amount of current or voltage depending on the driving characteristics of the photodetecting element Tr.

The channel portion of the photodetecting device Tr is provided with a semiconductor layer whose activation degree changes depending on the amount of light applied from the outside. Depending on the degree of activation of the semiconductor layer, the amount of light current or the amount of light voltage changes when a reference voltage or current is supplied. Accordingly, the amount of light is detected by detecting a change in the light voltage or the light current generated differently according to the degree of activation of the semiconductor layer. In other words, the first clock signal CLK1 input to the source electrode is used to generate an optical voltage or a photocurrent corresponding to the external light amount, and the photodetecting device Tr is generated according to the second clock signal CLK2. When turned on, it outputs an optical voltage or photocurrent. Therefore, the light amount detection signal VS represents the light voltage or the light current output at the turn-on of the light detection element Tr.

Since the light amount detection circuit 12 described above is formed in the liquid crystal panel 2 and outputs the light amount detection signal VS, a dummy metal pattern is provided to prevent the light amount detection signal VS from being distorted. Specifically, dummy metal patterns are further formed on the first and second supply lines CL1 and CL2 and the detection signal output line VSL. When the light amount detection circuit 12 is formed in the peripheral portion or the non-display area of the liquid crystal panel 2 together with the plurality of liquid crystal cells, the light amount detection signal VS is applied to signals such as a gate, a data signal, and a common voltage. This is to prevent distortion caused by interference. The dummy metal pattern will be described below in detail with reference to the accompanying drawings.

The light quantity detection circuit 12 may further include an amplification circuit (not shown) for amplifying the light quantity detection signal VS. In detail, an amplifying circuit using an operational amplifier or the like may be provided at the output terminal of the light quantity detection signal VS or the output line VSL to amplify the light quantity detection signal VS and supply it to the backlight driver 14.

3 is a process sectional view showing the manufacturing method of the light quantity detecting circuit according to the first embodiment of the present invention.

The photodetecting element Tr of the light amount detecting circuit shown in FIG. 3 is formed on the insulating substrate 31 by the gate electrode 32, the first insulating film 33, the semiconductor layer 34, the source and drain electrodes 35 and 36. And the like, and the first supply line CL1 is integrally formed with the source electrode 35 and the semiconductor layer 34 of the photodetecting element Tr. It is formed between. The detection signal output line VSL is formed between the first insulating film 33 and the second insulating film 39 integrally with the drain electrode 36 and the semiconductor layer 34 of the photodetecting device Tr. The dummy metal pattern 40 is formed with the second insulating layer 39 therebetween so as to overlap the detection signal supply line VSL. Here, the first insulating film 33 may mean a gate insulating film, and the second insulating film 39 may also mean a protective film.

Since the degree of activation of the semiconductor layer 34 of the photodetecting device Tr varies depending on the amount of external light, in response to the first clock signal CLK1 supplied through the first supply line CL1 and the source electrode 35. Generates an optical voltage or photocurrent. When the second clock signal CLK2 is supplied to the gate electrode 32 through the second supply line CL2, the photovoltage or the photocurrent is detected through the drain electrode 36 and the semiconductor layer 34. Output to (VSL).

The detection signal output line VSL is integrally formed with the semiconductor layer 34 and the drain electrode 36, and the dummy metal pattern 40 has the protection signal 39 therebetween with the detection signal output line VSL and the source electrode. It is formed so as to overlap with (36). Here, the dummy metal pattern 40 is to prevent the light amount detection signal VS outputted through the detection signal output line VSL from being distorted by interference from external signals, and thus voltage and current are not supplied. It also maintains the floating state. The dummy metal pattern 40 may be formed to overlap the detection signal output line VSL except for the source electrode 36.

Hereinafter, a method of manufacturing the light amount detection circuit according to the first embodiment of the present invention will be described in more detail with reference to FIG. 3.

First, the gate metal layer is formed and patterned on the insulating substrate 31 using a deposition method such as sputtering to form the second supply line CL2 and the gate electrode 32. That is, the gate electrode 32 is formed integrally with the second supply line CL2, and chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are used as the gate metal in a single layer or a double layer structure.

Thereafter, the first insulating layer 33, the semiconductor layer 34, the n + active layer 37, and the source / drain metal layer are sequentially stacked by a deposition method such as plasma enhanced chemical vapor deposition (PECVD) or sputtering. The first insulating layer 33 may be formed of an inorganic insulating material or an organic insulating material such as an acrylic organic compound having a low dielectric constant, a silicon nitride film (SiN), a silicon oxide film (SiO ₂ ), or the like. The semiconductor layer 34 is made of a material such as amorphous silicon (a-Si).

Subsequently, a photoresist pattern is formed on the source / drain metal layer by a photolithography process using a mask. Here, a diffraction exposure mask or the like having a diffraction section is used as the mask so as to correspond to the channel section of the photodetecting element Tr, that is, the region to which light is applied. In addition, the n + active layer 37 and the semiconductor layer 34 are simultaneously patterned by an etching process using a photoresist pattern to form the n + active layer 37 and the semiconductor layer 34 in the photodetecting device (Tr) region. Here, after the photoresist pattern having a relatively low height in the channel portion of the photodetecting device Tr is removed by an ashing process, a portion of the source / drain pattern and the n + active layer 37 are etched by the etching process. do. Accordingly, a portion of the semiconductor layer 34 of the photodetecting device Tr is exposed to separate the source electrode 35 and the drain electrode 36. Here, an inorganic or organic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the gate insulating film 33. As the source / drain electrodes, chromium (Cr), titanium (Ti), tantalum (Ta), and the like are used.

Next, a second insulating film 39 is formed on the entire surface where the source / drain electrodes 35 and 36 and the semiconductor layer 34 are exposed by a deposition method such as PECVD. As the material of the second insulating film 39 as the protective film, an inorganic or organic insulating material such as the first insulating film 33 may be used.

Thereafter, a conductive metal such as ITO (Imdium-Tin-Oxide), IZO, ITZO, TO, or the like is deposited and patterned to form a dummy metal pattern 40. In this case, the dummy metal pattern 40 is formed to overlap the source electrode 36 and the detection signal output line VSL of the photodetecting device Tr.

The dummy metal pattern 40 may be formed to overlap only the detection signal output line VSL except for the source electrode 36. In addition, although not shown in the drawings, a width wider than that of the detection signal output line VSL may be formed to cover all of the peripheral area of the detection signal output line VSL including the detection signal output line VSL.

As described above, the light quantity detecting circuit according to the first embodiment of the present invention includes a dummy metal pattern 40 overlapping the detection signal output line VSL with the passivation layer 39 therebetween. Here, the dummy metal pattern 40 may be formed to overlap not only the detection signal output line VSL but also each of the first supply line CL1 and the second supply line CL2, and the detection signal output line VSL. It may be formed on at least one of the first supply line (CL1) and the second supply line (CL2). Of course, the width of the dummy metal pattern 40 may be formed to have a width wider than that of each of the detection signal output line VSL, the first supply line CL1, and the second supply line CL2.

Next, a method of manufacturing the light quantity detecting circuit according to the second embodiment of the present invention will be described in more detail with reference to FIG. 4 as follows.

First, as shown in FIG. 4, a gate metal layer is formed on the insulating substrate 41 using a deposition method such as sputtering, and a patterning process using a photoresist is performed to perform a second supply line CL2 and a gate electrode 42. And the detection signal output line VSL. That is, the gate electrode 42 is integrally formed with the second supply line CL2, and the detection signal output line VSL is also formed by using the gate metal at the same time as the gate electrode 42. Here, as the gate metal, chromium (Cr), molybdenum (Mo), aluminum-based metal, or the like is used in a single layer or double layer structure.

Thereafter, the first insulating layer 43, the semiconductor layer 44, the n + active layer 47, and the source / drain metal layer are sequentially stacked by a deposition method such as PECVD or sputtering. Here, the first insulating film 43 as the gate insulating film is formed of an inorganic insulating material or an organic insulating material such as an acrylic organic compound having a low dielectric constant, a silicon nitride film (SiN), a silicon oxide film (SiO ₂ ), or the like. The semiconductor layer 44 is made of a material such as amorphous silicon (a-Si).

Subsequently, a photoresist pattern is formed on the source / drain metal layer by a photolithography process using a mask. As the mask, a diffraction exposure mask having a diffraction portion in the channel portion of the photodetecting element Tr, that is, the region to which light is applied, is used. The n + active layer 47 and the semiconductor layer 44 are simultaneously patterned by an etching process using a photoresist pattern to form the n + active layer 47 and the semiconductor layer 44 in the photodetecting device (Tr) region.

Next, after the photoresist pattern having a relatively low height in the channel portion of the photodetecting device Tr is removed by an ashing process, a portion of the source / drain pattern and the n + active layer 47 are removed by an etching process. Etched. Accordingly, a part of the semiconductor layer 44 of the photodetecting element Tr is exposed to separate the source electrode 45 and the drain electrode 46.

In this case, a first dummy metal pattern 51 overlapping the detection signal output line VSL is formed. Specifically, the first dummy metal pattern 51 is formed at the same time when the source and drain electrodes 45 and 46 are formed. In other words, the semiconductor layer 44, the n + active layer 47, and the source / drain metal layer are formed by patterning the gate insulating film 43 so as to overlap the detection signal output line VSL. Here, chromium (Cr), titanium (Ti), tantalum (Ta), or the like is used as the source / drain electrode.

Next, the second insulating layer 49 is formed on the entire surface where the source / drain electrodes 45 and 46, the first dummy metal pattern 51, and the semiconductor layer 44 are exposed by a deposition method such as PECVD. As the material of the second insulating film 49 as the protective film, an inorganic or organic insulating material such as an acrylic organic compound having a low dielectric constant, such as the first insulating film 43, a silicon nitride film (SiN), or a silicon oxide film (SiO ₂ ) It can be formed as.

Thereafter, first and second contact holes 52 and 53 are formed to partially expose the source electrode 45 and the detection signal output line VSL. The first and second contact holes 52 and 53 may be formed through a photolithography process and an etching process.

In addition, after depositing a conductive material such as ITO (Imdium-Tin-Oxide), IZO, ITZO, TO, etc. on the entire surface including the first and second contact holes 52 and 53, the contact electrode 50a and the second are patterned. The dummy metal pattern 50b is formed. In this case, the contact electrode 50a electrically connects the drain electrode 46 and the detection signal output line VSL through the first and second contact holes 52 and 53. The second dummy metal pattern 50b may be formed to be separated from the contact electrode 50a so as to overlap the first dummy metal pattern 51.

The first dummy metal pattern 51 and the second dummy metal pattern 50b overlap each other with the passivation layer 49 interposed therebetween. Of course, the first and second dummy metal patterns 51 and 50b may maintain a floating state and may not partially overlap as shown in FIG. 4 because they do not supply voltage or current.

 The first and second dummy metal patterns 51 and 50b according to the second embodiment of the present invention preferably overlap the detection voltage output line VSL formed of the gate metal. In addition, although not shown in the drawings, the first and second dummy metal patterns 51 and 50b are formed to have a wider width than the detection signal output line VSL to include the detection signal output line VSL. It may also be formed to cover all the peripheral area of the).

The first and second dummy metal patterns 51 and 50b may be formed to overlap both the first supply line CL1 and the second supply line CL2 as well as the detection signal output line VSL. It may be formed on any one or more lines of the output line VSL, the first supply line CL1, and the second supply line CL2. Of course, the widths of the first and second dummy metal patterns 51 and 50b are wider than the widths of the detection signal output line VSL, the first supply line CL1, and the second supply line CL2, respectively. It may be formed.

In addition, the first and second dummy metal patterns 51 and 50b may be formed to overlap with other lines, respectively. For example, when the first dummy metal pattern 51 overlaps the detection signal output line VSL with the first insulating layer 33 interposed therebetween, the second dummy metal pattern 50b is formed of the first and the second. Each of the supply lines CL1 and CL2 and the first and second insulating layers 43 and 49 may be formed to overlap each other.

As described above, the signal lines of the light amount detection circuit 12 according to the first and second embodiments of the present invention, that is, the first and second supply lines CL1 and CL2, are provided on the signal lines. And second dummy metal patterns 51 and 50b. Accordingly, interference from signals from the outside, for example, gate and data signals, a common voltage, and the like is prevented, thereby preventing the light quantity detection signal VS from being distorted.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The light amount detecting circuit of the liquid crystal display according to the present invention includes first and second dummy metal patterns for preventing interference from external signals. Accordingly, the light quantity detection signal can be prevented from being distorted, thereby improving the reliability of the light quantity detection circuit.

In addition, the present invention can reduce the power consumption of the backlight by detecting the external light amount of the liquid crystal panel by using the light amount detection circuit and by driving the backlight according to the external light amount to adjust the brightness of the liquid crystal panel.

Claims (20)

A light detecting element generating a light amount detecting signal corresponding to the amount of light incident from the outside according to the plurality of clock signals; A supply line supplying the plurality of clock signals; A detection signal output line configured to output the light quantity detection signal to the outside; A first dummy metal pattern overlapping at least one of the supply line and the detection signal output line with a first insulating layer interposed therebetween; And And a second dummy metal pattern formed by overlapping the first dummy metal pattern with the second insulating layer interposed therebetween. The method of claim 1, The supply line A first supply line integrally formed with the source electrode of the photodetecting device; And a second supply line integrally formed with the gate electrode of the photodetecting device. The method of claim 2, The detection signal output line And a light amount detecting circuit of the liquid crystal display device, wherein the light amount detecting circuit is formed at the same time as the gate electrode or the source electrode of the photodetecting device. The method of claim 3, wherein The second dummy metal pattern is And at least one of the first and second supply lines overlapping the first and second insulating layers therebetween. 5. The method of claim 4, And a contact electrode electrically connecting the detection signal output line formed simultaneously with the gate electrode and the source electrode through a plurality of contact holes. delete 6. The method of claim 5, Each of the first and second dummy metal patterns And a first and a second insulating film interposed therebetween so as to overlap at least one of the first and second supply lines and the detection signal output line. The method of claim 7, wherein The first and second dummy metal patterns And a width wider than that of the first and second supply lines and the detection signal output line. 9. The method of claim 8, The first and second dummy metal patterns A light amount detection circuit of a liquid crystal display device, characterized by maintaining a floating state. The method of claim 1, The plurality of clock signals A first clock signal periodically generated such that the high period has a longer period than the low period, And a second clock signal periodically generated such that the high period and the low period have the same period. Forming a light detecting element for generating a light amount detecting signal corresponding to the amount of light incident from the outside according to the plurality of clock signals; Forming a supply line for supplying the plurality of clock signals; Forming a detection signal output line for outputting the light quantity detection signal to the outside; Forming a first dummy metal pattern to overlap at least one of the supply line and the detection signal output line with a first insulating layer interposed therebetween; And And forming a second dummy metal pattern to overlap the first dummy metal pattern with the second insulating layer interposed therebetween. The method of claim 11, Forming the supply line Forming a first supply line integrally with a source electrode of the photodetecting device, And forming a second supply line integrally with the gate electrode of the photodetecting device. 13. The method of claim 12, Forming the detection signal output line And a gate electrode or a source electrode of the photodetecting device at the same time. The method of claim 13, The second dummy metal pattern is And overlapping at least one of the first and second supply lines with the first and second insulating layers interposed therebetween. 15. The method of claim 14, And forming a contact electrode which electrically connects the detection signal output line and the source electrode, which are formed simultaneously with the gate electrode, through a plurality of contact holes. delete 16. The method of claim 15, Forming the first and second dummy metal patterns And a first insulating film and a second insulating film interposed therebetween so as to overlap at least one of the first and second supply lines and the detection signal output line, respectively. The method of claim 17, The first and second dummy metal patterns And a width wider than that of the first and second supply lines and the detection signal output line. The method of claim 18, The first and second dummy metal patterns A method for manufacturing a light amount detection circuit of a liquid crystal display device, which maintains a floating state. The method of claim 11, The plurality of clock signals A first clock signal periodically generated such that the high period has a longer period than the low period, and And a second clock signal periodically generated such that the high period and the low period have the same period.

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