KR101240896B1 - Bus arbitration scheme for atsc-m/h multiplexer for mobile broadcasting service - Google Patents

Abstract

PURPOSE: A bus arbiter of a multiplexer for a digital broadcasting service is provided to efficiently use a shared memory of a hardware based multiplexer for the digital broadcasting service. CONSTITUTION: A WPU(Writing Process Unit)(212) and an RPU(Reading Process Unit)(214) are sequentially arranged for a memory(220) according to a priority of a bus for access to the memory. If the RPU or the WPU in a relatively higher priority requests use of a bus, the RPU or the WPU in a relatively lower priority waits until the RPU and the WPU in a relatively high priority complete the use of a bus. [Reference numerals] (200) Function block; (216) MUX selection signal generating unit

Description

Bus Arbitration Scheme for ATSC-M / H Multiplexer for Mobile Broadcasting Service

The present invention relates to a bus arbiter of a multiplexer for a digital broadcast service, and more particularly, to a memory interface technique for efficiently using a common memory by a hardware-based multiplexer.

The transmission system for the digital broadcasting service includes a video and audio encoder for compressing audio and video service data for digital broadcasting, an error correction encoding and a training sequence insertion, and a multiplexer for multiplexing service broadcasts. ), A modulator and a transmitter for wirelessly transmitting digital broadcast data. The multiplexer has the advantage that it can be implemented quickly and easily with PC-based software, but it has the disadvantage that the system stability is deteriorated during long time operation. Hardware-based multiplexers can be quickly recovered by simple switch toggle operations in case of system failure. In addition, the hardware-based multiplexer can be implemented at a lower cost than the software-based multiplexer, and has the advantage of fast processing time.

1 illustrates a hardware-based multiplexer for a conventional digital broadcasting service. Hereinafter, a hardware-based multiplexer for a conventional digital broadcasting service will be described in detail with reference to FIG. 1.

Referring to FIG. 1, a hardware based multiplexer for a digital broadcast service includes a processor, a hardware engine, a memory, an Ethernet interface, an ASI, and an SMPTE 310 interface circuit. It goes without saying that other configurations other than the above-described configuration may be further included.

Video data or audio data for digital broadcasting is transmitted in an IP packet through Ethernet or in an MPEG-2 TS packet through ASI / SMPTE 310. The digital broadcast service data input through the IP packet is preprocessed by the processor and then delivered to the hardware engine through the memory. The digital broadcast service data input through the MPEG-2 TS packet is delivered to the hardware engine through the ASI / SMPTE 310 interface block.

The hardware engine performs a multiplexing function such as error correction encoding or training sequence insertion on the IP packet or the MPEG-2 TS packet, and generates a packet for delivery to a transmitter. The packet generated by the hardware engine is transmitted to the transmitter through the ASI / SMPTE 310 interface block.

Since the digital broadcast service data moves between the processor, the hardware engine, and the ASI / SMTPE 310 interface block through the common memory, an efficient memory interface method is required. In general, conventional bus arbitration techniques for memory usage require more than three clocks such as Request, Grant, and Read / Wirte Operation to use the memory, and the interface circuit is also complicated. In addition, the conventional bus arbitration technique of allocating fixed blocks for using the memory to each functional block has a disadvantage in reducing the efficiency of the memory use.

The problem to be solved by the present invention relates to a memory interface technique for efficiently using a common memory of a hardware-based multiplexer for a digital broadcasting service, more specifically a large amount of terrestrial and mobile digital television (DTV) service data We propose a simple bus arbitration scheme for efficient processing of data through common memory.

To this end, the bus arbiter of the present invention includes at least one write process unit for reading data from a connected write function block and writing the data to a bus-connected memory; At least one read process unit which reads data written in the memory connected by a bus and provides the read function block to a read function block connected thereto; The read process unit and the write process unit are sequentially arranged in parallel with respect to the memory in accordance with the priority of the bus for accessing the memory. In this case, the read process unit or the write process unit having a relatively low priority may wait until the read process unit or the write process unit having a relatively high priority is finished using the bus.

To this end, the bus arbiter of the present invention includes a write FIFO memory for temporarily storing data to be stored in a memory, a write control signal generator for generating a control signal for writing data stored in the write FIFO memory to the memory, and the data. A write process unit including a write address generator for generating an address of a memory to be written; A read FIFO memory for reading and temporarily storing data stored in the memory, a read control signal generator for generating a control signal for writing data stored in the read FIFO memory to an associated read function block, and retrieving the data. A read process unit including a read address generator for generating an address of a memory; A multiplexer connected to the write process unit and the read process unit, and the other end connected to the memory; And a multiplexer selection signal generator configured to control one of a write process unit connected to the one side and a signal input from the read process unit to be transferred to the memory.

The bus arbitration scheme proposed by the present invention requires two clocks such as a request and a read / write operation to use a memory, and has an advantage that it can be implemented using a simple interface circuit. In particular, functional blocks having different frequencies of using the memory have an advantage when the memory is used irregularly.

1 illustrates a hardware-based multiplexer for a digital broadcasting service according to an embodiment of the present invention.
2 is a block diagram illustrating a bus arbitration unit according to an embodiment of the present invention.
3 is a block diagram showing the structure of a WPU according to an embodiment of the present invention.
4 is a block diagram illustrating a structure of an RPU according to an embodiment of the present invention.
5 illustrates an operation of a bus arbiter for a memory according to an embodiment of the present invention.

The foregoing and further aspects of the present invention will become more apparent through the preferred embodiments described with reference to the accompanying drawings. Hereinafter will be described in detail to enable those skilled in the art to easily understand and reproduce through this embodiment of the present invention.

The present invention requires two clocks consisting of a request procedure and an operation procedure in order for a plurality of blocks to use one common memory, and an interface between the plurality of blocks has a simple advantage.

2 is a block diagram illustrating a bus arbitration unit according to an embodiment of the present invention. Hereinafter, the bus arbitration unit according to an embodiment of the present invention will be described in detail with reference to FIG. 2.

According to FIG. 2, the bus arbitration unit includes a write processing unit (WPU), a read processing unit (RPU), a multiplexer (MUX), and a multiplexer selection signal generator. Of course, in addition to the above-described configuration, other configurations may be included in the bus arbitration unit. That is, the multiplexer selector includes a multiplexer configured to store data received from any one of the plurality of WPUs and RPUs in a memory, or to transfer data stored in the memory to either the WPU or the RPU according to a selection signal generated by the multiplexer selector signal generator.

In FIG. 2, the functional blocks 200 for using the memory access the memory 220 via the bus arbitration unit 210 composed of the WPU and the RPU, and each of the WPUs and the RPUs accesses the memory according to the connected order. Has a priority.

For example, the first WPU 212 may have the highest priority, and the third RPU connected last may have the lowest priority. Alternatively, the WPU (or RPU) using the memory at a low frequency may be arranged to have a high priority, and the WPU (or RPU) using the memory at a high frequency may be arranged to have a low priority.

WPUs (or RPUs) contain FIFO memory internally. WPUs (or RPUs) with higher priorities have more FIFO memory than WPUs (or RPUs) with lower priorities. If the high priority WPU (or RPU) is using memory, the low priority WPU (or RPU) uses memory until the high priority WPU (or RPU) has finished using the memory. can not do.

Specifically, according to FIG. 2, when the first WPU requests memory use, the output of busy_o is 1. When the first RPU receives 1 as the input of busy_i, the output of busy_o is 1. That is, when the first WPU requests memory use, the first RPU with a lower priority cannot use the memory. In addition, when the input of busy_i connected to the high priority WPU (or RPU) is 1, the busy_o output of the WPU (or RPU) becomes 1. If the input of busy_i connected to a high priority WPU (or RPU) is 0, the busy_o output will be 1 if the WPU (or RPU) requests memory usage. If the input of busy_i connected to a high priority WPU (or RPU) is 0, the busy_o output is 0 if the WPU (or RPU) does not request memory usage.

3 is a block diagram showing the structure of a WPU according to an embodiment of the present invention. Hereinafter, the structure of the WPU according to an embodiment of the present invention will be described in detail with reference to FIG. 3.

According to FIG. 3, the WPU includes an address generator, a first-in first-out (FIFO) memory, and a control signal generator. Of course, in addition to the above-described configuration, other configurations may be included in the WPU.

The address generator 300 generates an absolute address of a corresponding region of a memory to be used by a functional block connected to the WPU. The FIFO memory 304 temporarily stores data, and the control signal generator 302 generates a write enable signal for the memory.

If a high priority WPU requests to use memory, the Busy input signal Busy_i will be 1, while if a WPU with high priority does not use memory, the Busy input signal Busy_i will be 0. do. If the data is not stored in the FIFO memory, the Empty signal is 1, and if the data is stored in the FIFO memory, the Empty signal is 0.

The operation of the WPU is as follows. The WPU is in a waiting state until a function block connected to the WPU generates data (Data_In) and Write_Enable signals to write data to memory. When the WPU is in the standby state, if the Busy input signal Busy_i is 1, it makes the Busy output signal Busy_o 1 and prevents the WPU (or RPU) with lower priority from using the memory. In addition, when the WPU is in a standby state, if the Busy input signal Busy_i is 0, the Busy output signal Busy_o is set to 0 so that the WPU (or RPU) having a lower priority can use the memory.

When the WPU is in the standby state, if a function block connected to the WPU generates data (Data_In) and Write_Enable signals to write data to memory, the data (Data_in) is stored in FIFO memory, and the empty signal of the FIFO memory is 0. Will change to If the Empty signal is 0 and the Busy input signal Busy_i is 0, the WPU sets the Busy output signal Busy_o to 1 to prevent the low priority WPU (or RPU) from using memory. At the next clock, the data stored in the FIFO is written to memory. If the Empty signal is 0 and the Busy input signal Busy_i is 1, the WPU makes the Busy output signal Busy_o 1, which prevents the low priority WPU (or RPU) from using memory, and the Busy input signal. Wait until (Busy_i) becomes 0. When the busy input signal Busy_i becomes 0, data stored in the FIFO memory at the next clock is written into the memory.

4 is a block diagram illustrating a structure of an RPU according to an embodiment of the present invention. Hereinafter, the structure of the RPU according to an embodiment of the present invention will be described in detail with reference to FIG. 4.

According to Fig. 4, the RPU includes an address generator, a FIFO memory, and a control signal generator. The address generator 400 generates an absolute address of a corresponding region of a memory to be used by a function block connected to the RPU. The FIFO memory 404 temporarily stores data, and the control signal generator 402 generates a read enable signal for the memory.

If the high priority WPU (or RPU) requests to use the memory, the Busy input signal Busy_i becomes 1, and if the high priority WPU (or RPU) does not use the memory, the Busy input The signal Busy_i becomes zero. Also, when there is no more space for data to be stored in the FIFO memory, the full signal of the FIFO memory becomes 1.

The operation of the RPU is as follows. If the busy input signal is 1, it is in standby until the busy input signal becomes 0. If the busy input signal is zero, the data is read in advance from the memory and stored in the FIFO memory. This process is repeated until there is no more space in the FIFO memory to store the data. If a function block connected to the RPU reads data from the FIFO memory while performing a function operation, the FIFO memory has a space for storing the data therein. At this time, the data block is read in advance and stored in the FIFO memory. The Busy output signal is 1 only when the Busy input signal is 1 and while the RPU is reading data from memory.

The RPU sets the Busy output signal Busy_o to 1 if the Full signal of the FIFO memory is 1 and the Busy input signal Busy_i is 1, preventing the low priority WPU (or RPU) from using the memory. Also, if the full signal of the FIFO memory is 1 and the busy input signal Busy_i is 0, the busy output signal Busy_o is set to 0 so that the low priority WPU (or RPU) can use the memory.

If the full signal of the FIFO memory is 0 and the busy input signal Busy_i is 0, the WPU makes the busy output signal Busy_o 1 so that the low priority WPU (or RPU) does not use the memory. At the next clock, the data stored in the FIFO memory is written to the function block. If the full signal of the FIFO memory is 0 and the busy input signal (Busy_i) is 1, the WPU makes the busy output signal (Busy_o) 1, which prevents the low priority WPU (or RPU) from using the memory. Wait until the Busy input signal Busy_i becomes zero. When the busy input signal Busy_i becomes zero, the data stored in the FIFO memory at the next clock is written to the function block.

5 illustrates an operation of a bus arbiter for a memory according to an embodiment of the present invention. Hereinafter, the operation of the bus arbiter for the memory according to an embodiment of the present invention will be described in detail with reference to FIG. 5.

In FIG. 5, it is assumed that functional block 0 has a higher priority on memory usage than functional block 1. In the first clock, function block 0 with high priority request (Req. 1) to use memory, and in the second clock, memory read or write operation (Op. 1) of function block 0 is performed. . In addition, the third clock shows an example in which the high priority function block 0 and the low priority function block 1 request memory use (Req. 3 and Req. 4) at the same time. In this case, the memory read or write operation (Op. 3) of function block 0 with high priority is performed at the fourth clock, and the read or write operation (Op. 4) of function block 1 with low priority is performed. It is held. The memory Read or Write operation (Op. 4) of function block 1 held at the fourth clock is performed at the sixth clock.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present invention .

200: function block 210: bus arbiter
220: memory 300, 400: address generator
302, 402: control signal generator 304, 404: FIFO

Claims (8)

At least one write process unit for reading data from the connected write function block and writing the data to a bus-connected memory;
At least one read process unit which reads data written in the memory connected by a bus and provides the read function block to a read function block connected thereto;
The read process unit and the write process unit are arranged in parallel to the memory in accordance with the priority of the bus for accessing the memory,
When a read process unit or write process unit with a relatively high priority requests a bus use, the read process unit or write process unit with a lower priority has a higher priority than that of the read or write process unit with a higher priority. Wait for it to end
The write process unit
A first gate circuit configured to receive a signal indicating whether a bus of a relatively high priority read process unit or a write process unit is used and a signal indicating whether a bus is used;
A second gate circuit configured to receive a signal indicating whether a bus of a read process unit or a write process unit having a higher priority is output from the output signal of the first gate;
And a control signal generator including a delay unit for receiving an output signal of the first gate circuit.
The method of claim 1, wherein the write process unit,
A FIFO memory for temporarily storing data to be stored in the memory;
And an address generator for generating an address of a memory for recording the data.
delete At least one write process unit for reading data from the connected write function block and writing the data to a bus-connected memory;
At least one read process unit which reads data written in the memory connected by a bus and provides the read function block to a read function block connected thereto;
The read process unit and the write process unit are arranged in parallel to the memory in accordance with the priority of the bus for accessing the memory,
When a read process unit or write process unit with a relatively high priority requests a bus use, the read process unit or write process unit with a lower priority has a higher priority than that of the read or write process unit with a higher priority. Wait for it to end
The read process unit,
A first gate circuit configured to receive a signal indicating whether a bus of a relatively high priority read process unit or a write process unit is used and a signal indicating whether a bus is used;
A second gate circuit configured to receive a signal indicating whether a bus of a read process unit or a write process unit having a higher priority is output from the output signal of the first gate;
And a control signal generator including a delay unit for receiving an output signal of the first gate circuit.
The method of claim 4, wherein the read process unit,
A FIFO memory for retrieving and temporarily storing data stored in the memory;
And an address generator for generating an address of a memory into which the data is to be loaded.
A write FIFO memory for temporarily storing data to be stored in a memory, a write control signal generator for generating a control signal for writing data stored in the write FIFO memory to the memory, and generating an address of a memory to write the data A write process unit including a write address generator;
A read FIFO memory for reading and temporarily storing data stored in the memory, a read control signal generator for generating a control signal for writing data stored in the read FIFO memory to an associated read function block, and retrieving the data. A read process unit including a read address generator for generating an address of a memory;
A multiplexer connected to the write process unit and the read process unit, and the other end connected to the memory;
And a multiplexer selection signal generator configured to control one of the write process unit connected to the one side and the signal input from the read process unit to be transferred to the memory.
The write control signal generator,
A first gate circuit configured to receive a signal indicating whether a bus of a relatively high priority read process unit or a write process unit is used and a signal indicating whether a bus is used;
A second gate circuit configured to receive a signal indicating whether a bus of a read process unit or a write process unit having a higher priority is output from the output signal of the first gate;
And a delayer receiving an output signal of the first gate circuit.
delete A write FIFO memory for temporarily storing data to be stored in a memory, a write control signal generator for generating a control signal for writing data stored in the write FIFO memory to the memory, and generating an address of a memory to write the data A write process unit including a write address generator;
A read FIFO memory for reading and temporarily storing data stored in the memory, a read control signal generator for generating a control signal for writing data stored in the read FIFO memory to an associated read function block, and retrieving the data. A read process unit including a read address generator for generating an address of a memory;
A multiplexer connected to the write process unit and the read process unit, and the other end connected to the memory;
And a multiplexer selection signal generator configured to control one of the write process unit connected to the one side and the signal input from the read process unit to be transferred to the memory.
The read control signal generator,
A first gate circuit configured to receive a signal indicating whether a bus of a relatively high priority read process unit or a write process unit is used and a signal indicating whether a bus is used;
A second gate circuit configured to receive a signal indicating whether a bus of a read process unit or a write process unit having a higher priority is output from the output signal of the first gate;
And a delayer receiving an output signal of the first gate circuit.

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