KR101233825B1 - Apparatus and method for forward error correction in optical communication - Google Patents

Abstract

Disclosed are an optical transmission apparatus and method for performing error correction encoding and decoding. An optical transmission apparatus according to an embodiment of the present invention may convert a parallel signal into a form capable of error correction signal processing by using a signal conversion technique when error correction of signals transmitted in parallel in an optical transmission network. As a result, error correction can be smoothly and accurately performed on the parallel signal transmitted optically, and an appropriate operation speed necessary for signal processing can be obtained.

Optical transmission, error correction

Description

Optical transmission apparatus and method for performing error correction encoding and decoding {Apparatus and method for forward error correction in optical communication}

The present invention relates to an optical transmission network, and more particularly, to an error correction technique in signal transmission using an optical transmission layer.

The present invention is derived from a study conducted as part of the IT source technology development project of the Ministry of Knowledge Economy and ICT. [Task Management No.: 2008-F017-02, Title: Development of 100Gbps Ethernet and Optical Transmission Technology]

In the optical transmission system, a time division multiplexing method of multiplexing multiple low speed electric signals into one high speed electric signal and transmitting the same may be used. This method can be used not only for synchronous optical transmission but also for transmission in an optical transport network (OTN). OTU3 signal, one of the OTN ranks, is a high-speed signal with a transmission speed of 43 Gbps, and an error correction code that can correct an error on a transmission path is used.

However, since there is no way to directly process 43 Gbps or more signals inside the FPGA, it is possible to divide and process a plurality of parallel signals to operate in the FPGA. For example, when processing a 43Gbps signal in 256-bit parallel, the operation speed is about 168Mbps, and logic can be implemented in an FPGA that is currently commercially available. In this case, error correction code processing existing in OTU3 frame must be processed in 256-bit parallel.

However, the above-described parallel signal is a signal obtained by simply demultiplexing a 43Gbps signal, which is not suitable for processing an error correction code. Furthermore, in a parallel signal of 128 bits or more, error correction code processing is not easy to process on a 256 bit parallel signal simply because the position of a signal processed in an error correcting code is not accurately divided.

According to an aspect, an optical transmission apparatus and a method thereof capable of smoothly and accurately performing error correction on a parallel signal that is optically transmitted are provided.

An optical transmission apparatus according to an aspect includes an optical transmitter configured to perform error correction encoding by converting an input signal into optically corrected error correction encoding signals divided into bit parallel units through data selection, and input of a frame detection upon optical reception. And an optical receiver for converting the signal into a signal capable of error correction decoding and performing error correction decoding.

At this time, the optical transmitter is a first input signal converter for converting an input signal mapped to the optical transport layer signal frame into an error correction coding conformance signal through data selection on a parallel signal in units of bits in a parallel manner with respect to the converted signal. An error correction encoder for performing error correction encoding and a first output signal converter for converting the signal subjected to error correction encoding to a signal at the time of mapping through data selection and outputting the converted signal may be included.

Meanwhile, an optical transmission method according to another aspect includes mapping an input signal to an optical transmission layer signal frame, and converting the mapped signal into an error correcting encoding conformance signal divided in bit parallel units through data selection on a parallel signal in bit units. Performing error correction encoding on the converted signal in a parallel manner; converting the signal subjected to error correction encoding to a signal at mapping through data selection; and generating and outputting a frame for the converted signal It includes a step.

On the other hand, the optical transmission method according to another aspect, the step of detecting a data frame of the input signal, converting the frame detected signal into an error correction decoding suitable signal divided in bit parallel units by selecting data on the parallel signal in bits Performing error correction decoding on the converted signal in a parallel manner; converting the signal from which the error correction decoding is performed to a signal at the time of frame detection through data selection; and demapping the converted signal Restoring the signal.

An optical transmission apparatus according to an embodiment of the present invention may convert a parallel signal into a form capable of processing error correction signals by using a signal conversion technique when error correction of signals transmitted in parallel in an optical transmission network. Accordingly, error correction can be smoothly and accurately performed on the parallel signal transmitted through the optical transmission, and further, an appropriate operation speed required for signal processing can be obtained.

In particular, the optical transmission apparatus according to the exemplary embodiment may process the error correction signal by using the conventional parallel code and the decoding apparatus as it is without change, regardless of the number of bits of the input parallel signal. That is, the 128-bit parallel RS (255,239) code and decoder can be reused as it is to implement 256-bit or more parallel RS (255,239) code and decoder. Furthermore, an appropriate operating speed required for signal processing of 43 Gbps or more and 100 Gbps or more can be obtained.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention; In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the terms described below are defined in consideration of the functions of the present invention, and this may vary depending on the intention of the user, the operator, or the like. Therefore, the definition should be based on the contents throughout this specification.

1 is a diagram illustrating a configuration of an optical transmitter 10 of an optical transmission apparatus according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating a configuration of an optical receiver 20 of an optical transmission apparatus according to an embodiment. .

1 and 2, an optical transmission apparatus according to an embodiment may include an optical transmitter 10 and an optical receiver configured to perform error correction encoding and decoding when transmitting and receiving an optical signal in an optical transport network (OTN). And 20. An error correcting code used for error correction encoding is a code that can find an error and restore it to its original value when an error occurs during data transmission.

The optical transmitter 10 performs error correction encoding by converting an input signal into an error correction encoding conformance signal divided in bit parallel units during optical transmission. The optical receiver 20 performs error correction decoding by converting an input signal detected at the time of optical reception into an error correction decoding conformance signal divided in bit parallel units.

In the transmission signal processing of the optical transmission apparatus according to an embodiment, the transmission signal is controlled in the form of a low speed parallel signal in accordance with the limitation of the operation speed inside the FPGA. Here, the optical transmission device according to an embodiment of the present invention can convert the parallel signal in the form that can be error correction signal processing using a signal conversion technique in the error correction of the signal transmitted in parallel in the optical transmission network. Accordingly, error correction can be smoothly and accurately performed on the parallel signal transmitted through the optical transmission, and further, an appropriate operation speed required for signal processing can be obtained. In particular, the optical transmission device of the present invention can process the error correction signal by using the conventional parallel code and the decoding device as it is without change, regardless of the number of bits of the parallel signal input.

Referring to FIG. 1, the optical transmitter 10 may include an input signal mapping unit 100, a first input signal converter 110, an error correction encoder 120, a first output signal converter 130, and a frame. Generation unit 140 is included.

The input signal mapping unit 100 maps a client signal to an Optical Transport Unit (OTN) frame using an Optical Transport Hierarchy (OTH) in an optical transport network. The client signal includes both packet signals such as Ethernet layer signals and continuous signals such as synchronous digital hierarchy (SDH) signals and video signals.

The first input signal conversion unit 110 converts the signal mapped by the first input signal mapping unit 100 into an error correction encoding conformance signal through data selection on a bit parallel signal. In this case, the error correction coding conformance signal may have a form in which the same frame structure is repeated on the bit parallel signal, and data allocation areas between row units of the frame structure do not overlap each other in a predetermined area. An embodiment of an error correction conformance signal frame type will be described later with reference to FIGS. 5 and 8.

The error correction encoder 120 performs error correction encoding on the signal converted by the first input signal converter 110 in a parallel manner. Here, a Reed Solomon code for inserting information data and a parity byte for error correction into a frame of an optical transport layer signal for error correction encoding, or a super forward error correction (FEC) having superior performance may be used. . The Reed Solomon code is a code that additionally generates and inserts parity to determine the location of the error and converts the value of the error in order to perform correction to remove the error. According to an embodiment, the error correction encoder 120 may perform error correction encoding on parallel signals of 256 bits or more through the 128-bit parallel Reed Solomon code.

The first output signal converter 130 converts the signal on which the error correction encoding is performed into a signal at the time of mapping through data selection. That is, the first output signal converter 130 converts the input signal into a signal form input to the first input signal converter 110. On the other hand, the frame generation unit 140 generates and outputs a frame for the signal converted into a signal at the time of mapping, and this signal is converted into a serial signal through a serial-to-parallel converter and then transmitted as an optical signal.

Hereinafter, an implementation operation of the above-described optical transmitter 10 using an OTU3 signal having a 43 Gbps transmission rate among the OTN signals will be described below. First, an input signal having a transmission rate of about 40 Gbps is mapped to an OTU3 signal having a transmission rate of 43 Gpbs through the input signal mapping unit 100. Thereafter, the mapped signal is converted into a form in which an error correction code is possible by the first input signal converter 110, and then an error correction parity bit is inserted in the error correction encoder 120. Subsequently, the first output signal converting unit 130 is converted into a signal at the time of mapping and output through the frame generating unit 140. The signal is converted into a 43Gbps signal through a serial / parallel converter and transmitted as an optical signal.

2, the optical receiver 20 includes a frame detector 200, a second input signal converter 210, an error correction decoder 220, a second output signal converter 230, and a digital signal. It includes a mapping unit 240.

The frame detector 200 receives a signal converted into a plurality of parallel signals through a serial-to-parallel converter and finds a starting point of the frame for frame detection. The second input signal converter 210 converts the frame detected signal into a signal capable of error correction decoding through data selection on a bit parallel signal. Subsequently, the error correction decoding unit 220 performs error correction decoding on the signal converted by the second input signal conversion unit 210 in a parallel manner. Subsequently, the second output signal converter 230 converts the signal on which the error correction decoding is performed into a signal at the time of frame detection through data selection, and the demapping unit 240 demaps the converted signal to the original signal. Restore to. Since the configuration of the optical receiver 20 corresponds to the reverse process of the optical transmitter 10 described with reference to FIG. 1, detailed description thereof will be omitted.

According to an embodiment, through an error correction code and decoding method using the input signal conversion and output signal conversion techniques of the present invention, the optical transmission device uses a 128-bit parallel RS (255,239) Reed Solomon code and a decoder to perform a 256-bit parallel. Function equivalent to RS (255,239) Reed Solomon code and decoder can be implemented. The RS (255,239) Reed Solomon code indicates that the error is corrected by appending 16 bytes when the input is 239 bytes.

In another embodiment, through an error correction code and decoding scheme using the input signal conversion and output signal conversion techniques of the present invention, the optical transmission device uses 256-bit parallel Super-FEC (Super FEC) code and decoder. Functions equivalent to parallel Super FEC (Super FEC) codes and decoders can be implemented.

Super-FEC is a powerful FEC code that has better error correction than the RS (255,239) code. In this case, the super-FEC may be a combined form of the FEC code, such as [RS code + RS code], [BCH code + BCH code] or [RS code + BCH code]. The Bose-Chaudhuri-Hocquenghem (BCH) code is one of the powerful multiple error-correcting cyclic codes. According to one embodiment, the concatenated BCH code consisting of BCH 3860, 3824 and BCH 2040, 1930 codes is without additional redundancy compared to Reed-Solomon 255, 239. The error can be corrected.

By using the above-described input signal conversion and output signal conversion techniques, an appropriate operating speed required for OTU3 signal processing can be obtained in the case of 43Gbps OTU3 signal processing. In addition, since the above-described method is extensible, it can be applied as it is even at a higher operating speed. For example, it can be applied to OTU4-class signal processing having a transmission speed of 100 Gbps or more.

Hereinafter, an optimized error correction encoding and decoding technique according to various embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, in order to understand the invention, Reed Solomon code error correction encoding and decoding techniques optimized based on OTU3, which is one of the OTU ranks in the optical transmission network, will be described later. However, the present invention is applicable to not only OTU3 but also other OTU ranks. Of course, it also applies to super-FEC.

3 is a diagram illustrating an OTU3 signal frame structure according to an embodiment of the present invention.

Referring to FIG. 3, in the OTU3 signal type according to an embodiment of the present invention, one column is composed of 4080 bytes, and a total of four columns are added to form one OTU3 frame. According to one embodiment, the error correcting code applied to FIG. 3 is a (255,239) Reed Solomon code (hereinafter referred to as RS (255,239)), and the information signal is composed of 239 bytes and 16 bytes are parity bytes. In this case, the error correction code and the decoding are not processed in units of frames but independently in units of columns. RS (255,239) code is a non-binary code, one symbol corresponds to one byte. In the Forward Error Correction (FEC) region illustrated in FIG. 3, RS (255,239) codes may be inserted in a form of 16 bytes interleaving.

FIG. 4 is a diagram illustrating a detailed structure of an OTU3 signal frame of FIG. 3. Referring to FIG. 4, a part of each byte may be identified in the structure of the OTU3 signal frame shown in FIG. 3.

FIG. 5 illustrates the OTU3 signal frame of FIG. 4 in 128-bit parallel form.

Referring to FIG. 5, since each code is processed in units of 1 byte, that is, 8 bits, and there are 16 in total, the frame structure of FIG. 4 may be implemented in a 128 (= 8 × 16) bit parallel form shown in FIG. 5. According to an embodiment, the RS (255,239) code may be processed in 8-bit units on a 128-bit parallel signal, respectively. In the OTN, 16 Reed-Solomon codes are used as byte interleaving method and processed in byte unit, the 128-bit parallel signal is the best signal type for error correction signal processing.

FIG. 6 is a diagram for describing error correction encoding performed by the error correction encoder 120 in parallel according to an embodiment of the present invention. Referring to FIG. 6, 16 error correction encoders 120 may be used to operate in 8-bit parallel when the transmission signal is 128-bit parallel.

FIG. 7 illustrates the OTU3 signal frame of FIG. 3 in 256-bit parallel form.

When processing the 43Gbps-class OTU3 signal using the error correction encoder 120 illustrated in FIG. 6, an operation speed of about 43Gbps / 128 = 336Mbps is required. However, since a lot of combinational logic is used for error correction encoding and decoding, it is not easy to obtain the aforementioned operating speed with a commercially available FPGA. As a result, processing at 43 Gbps OTU3 signals at lower operating speeds has many advantages in practice. The frame form in the case of 256-bit parallel processing to reduce the operation speed to 1/2 is the frame form shown in FIG. 7. In this case, the operating speed is 43Gbps / 256 = 168Mbps, making it much easier to implement optical transmission.

However, when compared with the 128-bit parallel signal type shown in FIG. 5, it is not easy to perform error correction encoding and decoding in 8-bit units in the frame type shown in FIG. 7. In addition, the two columns overlap at the same time at the intermediate point, so a control signal for controlling them is required separately. That is, in a parallel signal of 128 bits or more, error correction code processing is not easy to process on a 256-bit parallel signal simply because the position of a signal processed in an error correcting code is not accurately divided. In the present specification, the 256-bit parallel signal shape of FIG. 7 will be referred to as A-format.

FIG. 8 illustrates a 256-bit parallel form in which an OTU3 signal frame is converted into a form capable of error correction encoding according to an embodiment of the present invention.

Referring to FIG. 8, in order to solve the above-described problem in FIG. 7, the optical transmission apparatus may perform error correction encoding and decoding by converting the frame form of FIG. 7 into the frame form of FIG. 8, which is a signal form capable of error correction code and decoding. Can be. Here, the frame form of FIG. 8 is a 256-bit parallel format, and the operation speed is the same as that of the frame shown in FIG. 7. In this specification, the form of FIG. 8 will be referred to as B_format.

Referring to the frame form illustrated in FIG. 8, two 128-bit parallel signals illustrated in FIG. 5 are stacked. That is, the same frame structure is repeated on the bit parallel signal, and data allocation areas between row units of the frame structure do not overlap each other in a predetermined area. Therefore, unlike the frame type shown in FIG. 7, error correction encoding and decoding may be performed in 256-bit parallel signals in 8-bit units, respectively.

9 is a diagram illustrating a configuration of an optical transmitter for performing error correction encoding on a 256-bit parallel signal according to an embodiment of the present invention.

Referring to FIG. 9, error correction encoding may be performed on a 256-bit parallel signal using the signal form B_format illustrated in FIG. 8. That is, a signal having the B_format shown in FIG. 8 through the first input signal conversion unit 110 through the signal output in A_format shown in FIG. 7 from the 256-bit output terminal of the input signal mapping unit 100 during optical transmission. Convert to Subsequently, after the error correction coding is performed by the error correction coding units 121 and 122 operating in 128-bit parallel, the first output signal converting unit 130 converts the converted signal into the A-format shown in FIG. It is connected to the generation unit 140. Since the reverse process of the above-described signal transmission is performed at the time of optical reception, detailed description thereof will be omitted.

The first input signal converter 110 shown in FIG. 9 is an apparatus for converting the A-format signal shown in FIG. 7 into the B-format signal shown in FIG. 8, and the first output signal converter 130 On the contrary, the B-format signal shown in FIG. 8 is converted into the A-format signal shown in FIG.

Accordingly, the existing 128-bit parallel RS (255,239) code and decoder can be reused as it is to implement a 256-bit parallel RS (255,239) code and decoder as well as to obtain an appropriate operating speed required for 43 Gbps OTU3 signal processing. .

10 is a diagram illustrating a configuration of the first input signal converter 110 according to an embodiment of the present invention.

Referring to FIG. 10, the first input signal converting unit 110 stores the memory A 111, the memory B 121, and each memory for each of the predetermined bit units for the client signal mapped to the optical transport layer signal frame. And input signal selectors 113 and 114 that receive signals output from the signals 111 and 112 and selectively control signal output according to the swap signal.

Specifically, the memory A 111 stores the upper 128 bits of the 256-bit A_format signal shown in FIG. 7. Memory B 112 stores the lower 128 bits in the 256-bit A_format signal shown in FIG. The output signals MemOut_A and MemOut_B of the memory A 111 and the memory B 112 are selected and controlled by the input signal selectors 113 and 114 according to the swap signal generated by the timing generator 115. In the above configuration, the final outputs (Upper OUT, Lower OUT) are output in the B_format format shown in FIG.

FIG. 11 is a timing diagram illustrating an input signal conversion process using the first input signal converter 110 of FIG. 10. Here, the reference numerals of the components shown in FIG. 10 are used as they are.

Referring to FIG. 11, the timing generator 115 generates a write address WA and a read address Ra (A) and Ra (B). The input signal is an A-format signal shown in FIG. 7, and the WA signal is generated from X''0 '' to X''FE '' as shown in FIG. 11 according to the input FrameStart signal. At this time, the input data is stored in the corresponding address. Subsequently, the timing generator 115 generates a ReadStart signal at a suitable time after the first column is stored in the A-format signal shown in FIG. 7. Using this signal, the timing generator 115 generates Ra (A) and Ra (B) signals, respectively. According to this address, the outputs of the memories 113 and 114 are determined, respectively, as shown in FIG. Finally, when the first input signal converter 110 selects the output MemOut A and MemOut B signals of the memory by using the swap signal generated by the timing generator 115, the B_format format shown in FIG. 8 is output.

12 is a diagram illustrating a configuration of a first output signal converter according to an embodiment of the present invention.

Referring to FIG. 12, the first output signal converter 130 receives an input signal converted into a form capable of error correction encoding through data selection and output signal selectors 131 and 132 to selectively control a signal output according to a swap signal. And memories 133 and 134 which store signals output through the output signal selectors 131 and 132, respectively.

When the 256-bit B_format signal shown in FIG. 8 is broken in 128-bit units and referred to as an upper signal and a lower signal, respectively, the memory A 133 outputs the output signal of the upper output signal selector 131 to the memory B 134. The output signal of the output signal selector 132 at the bottom is connected, respectively. The output signal selectors 131 and 132 receive a swap signal from the timing generator 135 to select an output signal. The selected signal is stored in the memories 133 and 134 by the WA signal, respectively.

FIG. 13 is a timing diagram illustrating an output signal conversion process using the first output signal converter 130 of FIG. 12. Here, the reference numerals of the components shown in FIG. 12 are used as they are.

Referring to FIG. 13, signals stored in the memories 133 and 134 are read and output to Ra (A) and Ra (B). The input signal is a B-format signal shown in FIG. 8, and the WA signal generates X''0 '' to X''FE '' as shown in FIG. 13 according to the input FrameStart signal. In this case, the swap signal is generated through the timing generator 135 to select an input signal. Subsequently, the timing generator 135 generates a ReadStart signal at a suitable time after the time at least half of the B-format signal shown in FIG. 8 is stored. This signal is used to generate Ra (A) and Ra (B) signals, respectively. According to this address, the outputs of the memories 133 and 134 are determined, respectively, as shown in FIG. Finally, the output MemOut A and MemOut B signals of the memories 133 and 134 are in the A_format format shown in FIG.

14 is a diagram illustrating a configuration of an optical transmitter for performing error correction encoding on a 512-bit parallel signal according to an embodiment of the present invention.

Referring to FIG. 14, when the transmission signal is not only a 256-bit parallel signal but also a 512 parallel signal, a sufficient operation speed of about 100 Gbps or more can be obtained when the operation speed of the FPGA is about 200 Mbps. Even in this case, error correction can be easily implemented by reusing the 128-bit parallel RS (255,239) encoders 123, 124, 125, and 126 as they are.

That is, the 128-bit parallel RS (255,239) code and decoder can be reused as it is to implement a parallel RS (255,239) code and decoder of 512 bits or more, and an appropriate operation speed required for signal processing of 100 Gbps or more can be obtained.

The embodiments of the present invention have been described above. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

1 is a view showing the configuration of an optical transmitter of an optical transmission apparatus according to an embodiment of the present invention;

2 is a view showing the configuration of an optical receiver of an optical transmission apparatus according to an embodiment of the present invention;

3 illustrates an OTU3 signal frame structure according to an embodiment of the present invention;

4 is a diagram illustrating a detailed structure of an OTU3 signal frame of FIG. 3;

5 is a diagram illustrating the OTU3 signal frame of FIG. 4 in 128-bit parallel form;

FIG. 6 is a diagram for describing error correction encoding performed by an error correction encoding unit in parallel according to an embodiment of the present invention; FIG.

7 illustrates the OTU3 signal frame of FIG. 3 in 256-bit parallel form;

8 illustrates a 256-bit parallel form in which an OTU3 signal frame is converted into a form capable of error correction encoding according to an embodiment of the present invention;

9 is a diagram showing the configuration of an optical transmitter for performing error correction coding on a 256-bit parallel signal according to an embodiment of the present invention;

10 is a diagram illustrating a configuration of a first input signal converter according to an embodiment of the present invention;

FIG. 11 is a timing diagram illustrating an input signal conversion process using the first input signal conversion unit of FIG. 10.

12 is a diagram illustrating a configuration of a first output signal converter according to an embodiment of the present invention;

FIG. 13 is a timing diagram illustrating an output signal conversion process using the first output signal conversion unit of FIG. 12. FIG.

14 is a diagram illustrating a configuration of an optical transmitter for performing error correction encoding on a 512-bit parallel signal according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10: light transmitting unit 20: light receiving unit

100: input signal mapping unit 110: first input signal conversion unit

120: error correction encoder 130: first output signal converter

140: frame generation unit 200: frame detection unit

210: second input signal converter 220: error correction decoder

230: second output signal converter 240: demapping unit

Claims (10)

In the optical transmission device of the optical transmission network, An optical transmitter for converting an input signal into an error correction coding conformation signal divided into bit parallel units through data selection and performing error correction encoding upon optical transmission; And And an optical receiver for converting an input signal detected by the frame at the time of optical reception into an error correction decoding suitability signal divided in bit parallel units through data selection and performing error correction decoding. The error correction coding conformance signal may be configured such that a frame structure having the same form is repeated on a parallel signal of 256 bits or more, and data allocation areas between row units of the frame structure do not overlap each other in a predetermined area. Optical transmission device. The method of claim 1, wherein the optical transmission unit, A first input signal conversion unit converting an input signal mapped to an optical transport layer signal frame into the error correction coding conformation signal on a parallel signal in units of bits; An error correction encoding unit performing error correction encoding on the converted signal in a parallel manner; And And a first output signal converting unit converting the signal on which the error correction encoding is performed into a signal at the time of mapping and outputting the converted signal. delete The method of claim 2, wherein the first input signal converter, A memory for storing the input signal mapped to the optical transmission layer signal frame for each preset bit unit; And And an input signal selector configured to receive a signal output from the memory and selectively control a signal output according to a swap signal. The method of claim 2, wherein the error correction encoder, And a reed-solomon encoding means for inserting information data and a parity byte for error correction into a frame of the optical transmission layer signal or a super FEC means which is a combination of FEC codes. The method of claim 5, wherein the error correction encoder, And the error correction encoding is performed on parallel signals of 256 bits or more through the 128-bit parallel Reed Solomon encoding means or the super FEC means. The method of claim 2, wherein the first output signal converter, An output signal selector configured to receive a signal converted into the error correcting encoding conformance signal and selectively control a signal output according to a swap signal; And And a memory for storing the signals output through the output signal selector, respectively. The method of claim 1, wherein the light receiving unit, A second input signal conversion unit converting the frame detected input signal into the error correction decoding conformance signal on a parallel signal in units of bits; An error correction decoding unit performing error correction decoding on the converted signal in a parallel manner; And And a second output signal converter configured to convert the signal from which the error correction decoding is performed into the frame detected signal form and output the converted signal. delete delete

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