KR101225544B1 - Multi-stack Mask layer silicon-oxide etching method using the Hybrid Plasma Source and ESC heater - Google Patents

Abstract

The present invention relates to an oxide etching method of a multi-stack layer mask structure in which a mask layer and an oxide layer are stacked, and an electrostatic chuck heating step and an ICP source for optimizing the temperature of an inner zone and an outer zone of an electrostatic chuck. A mask layer etching step of etching a mask layer using an inductive coil plasma source and a capacitively coupled plasma source, a chamber stabilization step of converting an electrostatic chuck to a normal mode, and the mask layer etching step It is composed of an oxide film etching step of etching the oxide film by using the mask pattern formed as an etching mask, thereby inducing stable temperature control of the electrostatic chuck heater through the application of a hybrid plasma source. Hybrid plastic with independent control of (Edge) CD (critical dimension, etching width) To provide an oxide etching method of a multi-layer mask stack using a town source and chuck structure.

Description

Multi-stack Mask layer silicon-oxide etching method using the Hybrid Plasma Source and ESC heater}

The present invention relates to an oxide film etching method of a multi-stack layer mask structure in which a mask layer of a composite layer is stacked, wherein the film quality of the stacked structure is sequentially etched, and a plasma is generated using a hybrid plasma source. By generating, it is possible to stably control the temperature of the heater installed in the electrostatic chuck, and the hybrid which can independently control the center of the wafer and the critical dimension (etch width) of the edge (Edge) An oxide etching method of a multi-stack layer mask structure using a plasma source and an electrostatic chuck heater.

In general, a wafer used in a semiconductor integrated circuit device has several thin film layers formed on a surface thereof, and only a part of the thin film is selectively removed, thereby forming a circuit or a pattern having a desired ultrafine structure on the surface.

The manufacture of such microcircuits or patterns is generally made through a number of manufacturing processes, such as a cleaning process, a deposition process, a photolithography process, a plating process, and an etching process.

Various treatment processes as described above are put into a chamber or a reactor capable of isolating the wafer or substrate from the outside and processed.

In particular, the etching process of the above processes is generally performed through the physical or chemical reaction in the plasma state by spraying the appropriate reaction gas (CxFx-based, SxFx-based, HBr, O₂, Ar, etc.) into the chamber or reactor A process of selectively removing a desired material from the wafer surface is a process of patterning a microcircuit on the surface by selectively removing a portion not covered with the photoresist using a photoresist pattern as a mask.

Recently, as the pattern of the semiconductor process is miniaturized to 30-40 nm or less, a mask having a multi-stack layer structure in which a mask layer is not a single photoresist layer but a hard mask layer is stacked (see FIG. 6A).

However, as semiconductor wafers gradually become larger in size from 200 mm to 300 mm or 450 mm, more control of process variables is required, and many efforts are being made to control them effectively.

In particular, as the difference between the center density of the wafer and the pattern density of the edge increases, the exhaustion of the local etching source caused by the difference in the consumption of the reaction gas causes the central and outer edge portions to be depleted. Due to the different etching speed (Microloading), the CD (Critical Dimension, etching width) of the edge portion and the CD of the central portion were different.

Conventionally, a method of controlling the temperature of an electrostatic chuck (ESC) has been used in order to remove the difference in the CD (Critical Dimension) at the center and edge of the wafer.

In general, during the etching process, a polymer layer, which acts as an obstacle to etching, accumulates on the wafer surface at the same time as the etching process proceeds, and the amount of the polymer layer is greatly increased depending on the temperature of the wafer. Will change.

In other words, if the wafer temperature is high, the polymer passivation action of the polymer deposited on the pattern side is reduced, and the etching speed to the side of the pattern is accelerated, which directly affects the CD.

Of course, if the wafer temperature is low, the opposite is true.

Therefore, in the related art, by controlling the temperature of the electrostatic chuck by applying an alternating current to a heater installed in the electrostatic chuck, the CD is controlled by controlling the temperature of the wafer.

However, the conventional wafer temperature control method as described above has the following problems.

During the actual etching process, since RF power (Radio Frequency Power) must be transmitted to the electrostatic chuck to generate plasma in the chamber, the heater system of the electrostatic chuck is severely subjected to RF interference.

In addition, to block this, a low pass filter (LPF) was added to the heater system to configure the system to filter the RF causing interference.

However, since oxide etching process is basically a process that applies high bias power, there is a limit in RF filtering, and it is very important to control the CD on the wafer surface by controlling the temperature of the electrostatic chuck heater. It becomes difficult.

Therefore, in the conventional oxide film etching process, the operation of controlling the temperature of the wafer using the heater of the electrostatic chuck is not performed.

As a result, it is impossible to accurately control the CD at the center and the edge of the wafer, so that it is impossible to maintain CD (Critical Dimension) or etching uniformity on the entire surface of the wafer, resulting in a significant decrease in chip yield. As the trend toward larger diameters of wafers and higher integration of semiconductor devices has progressed, CD control effects have become more difficult.

The present invention has been made to solve the above problems, an object of the present invention by generating a plasma using a hybrid plasma source (Hybrid Plasma Source), the temperature of the heater installed in the electrostatic chuck stably without interference of RF By precise control, the mask of the multi-stack structure can be etched effectively to finally control the CD of the oxide film, thereby compensating for the CD difference at the center and the edge of the wafer.

In order to achieve the above object, the present invention loads a wafer on an electrostatic chuck and applies an electric current to the heater of the electrostatic chuck and then optimizes the temperature of the inner zone and the outer zone of the electrostatic chuck, respectively. The chuck heating step, the mask layer etching step of generating plasma in the reaction chamber by turning on the hybrid plasma source, and the mask layer etching to etch the mask layer, blocking the current applied to the heater of the electrostatic chuck and cooling the electrostatic chuck. An oxide film which etches an oxide film using a mask pattern formed in the mask layer etching step as an etching mask by applying a high bias power to the electrostatic chuck and a chamber stabilization step for preparing the next etching process after returning to the normal state. It comprises an etching step.

The hybrid plasma source may include an ICP source (Inductive Coil Plasma Source) using an inductive coil located above the chamber and a Capacitively Coupled Plasma Source (BPS) using bias power transferred from the electrostatic chuck to the wafer. Can be.

In addition, in the electrostatic chuck heating step, the heater may be separated and configured independently of the inner zone and the outer zone of the electrostatic chuck to enable temperature control independently of the center and edge of the wafer.

In addition, it is preferable to provide ON / OFF relays to the heaters of the electrostatic chuck so that the temperature can be controlled independently.

The mask layer etching step includes an antireflection film etching step and a hard mask etching step of etching an amorphous carbon layer under the antireflection film.

In addition, the etching of the multi-stack layer mask generates plasma using an ICP source together even when high bias power is not applied to the electrostatic chuck so that the etching may be sufficiently performed by a radical chemical reaction. can do.

In addition, in the oxide film etching step, a high bias power may be applied so that etching may be performed by a physical reaction by ion energy.

As described above, the present invention enables independent precise control of the CD at the center and the edge of the wafer through stable control of the Hybrid Plasma Source and the electrostatic chuck heater. CD uniformity and etching uniformity can be secured, thereby improving process efficiency and increasing productivity by increasing chip yield.

1 is a schematic structural diagram of an embodiment of a plasma reactor,
2 is a block diagram of a hybrid plasma source of the present invention,
3 is a configuration diagram of the electrostatic chuck heating system of the present invention;
4 is a schematic view showing two heating modes of the electrostatic chuck of FIG.
5 is a flowchart of an oxide film etching method of a multi-stack layer mask structure using a hybrid plasma source and an electrostatic chuck of the present invention;
6 is an etching process diagram of the present invention.

The present invention is characterized in that by using a hybrid plasma source (Hybrid Plasma Source), it is possible to stably control the heater installed in the electrostatic chuck (ESC), by adjusting the heater of the electrostatic chuck by the oxide film of the multi-stack layer mask structure By precisely controlling the CD (critical dimension) of the mask layer on the wafer, the overall CD uniformity of the wafer surface is realized.

Hereinafter, the present invention will be described in detail with reference to the drawings.

1 is a schematic configuration diagram of an embodiment of a plasma reactor according to the present invention, and schematically illustrates components related to an oxide etching method of a multi-stack layer mask structure using a hybrid plasma source and an electrostatic chuck of the present invention. .

As shown, the reaction chamber 100 is to provide a plasma reaction space that is isolated from the outside in the etching process, to form a sealed space of a predetermined size therein, depending on the size or process characteristics of the wafer (W) It may be formed in the form.

Here, the body of the reaction chamber 100 is connected to the ground, the upper portion is provided with an RF shield cover (Shield Cover) (150).

In addition, the lower portion of the reaction chamber 100 is provided with an exhaust unit 130 for discharging reaction by-products such as a reaction gas, polymer or particles, etc. to the outside, the exhaust unit 130 is an internal gas The turbo pump 135 is installed to forcibly discharge the inside to convert the interior into a vacuum atmosphere.

Meanwhile, a cathode assembly 140 is installed at the center of the reaction chamber 100, and an electrostatic chuck (ESC) on which the wafer W is loaded to perform an etching process is disposed on the cathode assembly 140. 10) is installed in a horizontal state, in which the electrostatic chuck 10 is connected to a CCP source (Capacitively Coupled Plasma Source) (60).

In this case, the electrostatic chuck 10 has a heater 30 installed therein to enable temperature control of the wafer W loaded thereon, and a gas pipe (not shown) capable of injecting a heat transfer gas such as helium (He) gas. ) Is installed.

Here, the wafer W is loaded and fixed in a horizontal state on top of the electrostatic chuck 10 by electrostatic power.

An RF shield cover 150 is coupled to the upper portion of the reaction chamber 100, and the RF shield cover 150 is an inductive coil (IC) source 50 as an inductively coupled plasma source 50. Inductive Coil) 55 is provided.

The inductive coil 55 is connected to the RF generator (13.56MHz).

In addition, the upper gas injector 110 and the side gas injector 120 are installed in the upper center and side portions of the reaction chamber 100, respectively, and the upper gas injector 110 and the side gas injector 120 have separate flow rates. It is connected to the control module 125.

The upper gas injector 110 is a plurality of injection holes to simultaneously spray the reaction gas in the downward direction and lateral direction as shown by the arrow so that the reaction gas is rapidly diffused into the reaction chamber 100 to form a uniform plasma It is preferably provided in the form of a shower head provided with.

Therefore, the reaction gas is simultaneously injected from the upper side and the side of the reaction chamber 100 through the upper gas injector 110 and the side gas injector 120.

Here, the reaction gas injected from the upper gas injector 110 and the side gas injector 120 is diffused into the reaction chamber 100 and converted into a plasma state by an applied RF power, and the plasma is in contact with the surface of the wafer W. By contact and physical or chemical reaction, the surface of the wafer W is etched in a predetermined pattern.

Various kinds of gases may be used for each etching process characteristic, but CxFx or SxFx series or HBr, Ar, O₂ and other gases are generally used. After the reaction is completed, the reaction gas and reaction by-products are exhausted. Forced to discharge to the outside through (130).

In general, the reaction gas does not form a plasma uniformly due to a difference in diffusion degree in the process of reaching the center and the edge of the wafer W, so that the wafer W is The difference between the etching rate and the CD (critical dimension) of the center part and the edge part is generated, and the chip yield of the edge part is significantly reduced as well as the process defect.

In particular, due to the large diameter of the wafer W and the high integration of semiconductor devices, process margins are reduced, and as the CD is smaller than 30 nm, defects due to plasma unevenness at edges are significantly increased. .

Therefore, the oxide layer etching method of the multi-stack layer mask structure according to the present invention uses the hybrid plasma source and the electrostatic chuck heater 30 to apply the mask layer 250 without applying a high bias power. By effectively etching), it is to finally control the CD of the oxide (oxide) (200).

In this case, the etching process of the mask layer 250 may apply a low RF bias power to the electrostatic chuck 10, so that the heater 30 may have an inner zone and an outer of the electrostatic chuck 10 without RF interference. By effectively controlling the temperature of the zone (Outer Zone) it is possible to precisely compensate for the difference between the etching rate (Etch Rate) and the CD (Critical Dimension) of the center and the edge of the wafer (W) to eliminate the deviation.

2 shows a configuration diagram of a hybrid plasma source of the present invention.

As shown, the hybrid plasma source is an Inductively Coupled Plasma Source 50 by Coil Current and a Capacitively Coupled Plasma Source 60 by Bias Power. Is done.

The generation of plasma using both the above and two sources is called a hybrid plasma source.

The RF generator generates an plasma in the reaction chamber 100 by applying an RF current to the inductive coil 55, which is an ICP source, and the CCP source 60 is a bias RF generator connected to the cathode assembly 140. The plasma is generated by applying a bias power to the electrostatic chuck 10 through 2, 3 (61, 65).

Therefore, the inductive coil 55 generates a magnetic field when an RF current is applied from the ICP source 50, and induces an electric field inside the reaction chamber 100 by the magnetic field. It will generate a high density plasma.

Meanwhile, the CCP source 60 generates plasma in the reaction chamber 100 by supplying bias power to the electrostatic chuck 10, and applies RF generator 2 (2MHz) 61 to apply bias power in a relatively low frequency region. And an RF generator 3 (27 MHz) 65 that applies a bias power in a relatively high frequency region, and includes a bias impedance matching circuit 133.

At this time, the bias impedance matching circuit 133 mixes the RF bias power received from the RF generator 2 61 and the RF bias power of the relatively high frequency received from the RF generator 3 65 through the cathode assembly 140. Supply to the electrostatic chuck 10.

Therefore, the CCP source 60 applies a dual frequency bias power of the two frequencies to the electrostatic chuck 10.

At this time, the power delivered to the electrostatic chuck is finally referred to as bias power because it is directly delivered to the wafer.

Hereinafter, the heating system of the electrostatic chuck 10 will be described with reference to FIG. 3.

As shown, the electrostatic chuck 10 is connected to the CCP source 60, the electrode plate 15 is installed therein.

Therefore, when a voltage is applied to the electrode plate 15, the electrode plate 15 has a positive potential and correspondingly, the wafer W is charged with negative charge so that the wafer W is electrostatically chucked on the top of the electrostatic chuck 10. To be chucked to.

Meanwhile, a heater 30 for heating the wafer W to a predetermined temperature is installed inside the electrostatic chuck 10.

In this case, the heater 30 may independently control the temperature of the inner zone and the outer zone of the electrostatic chuck 10 and an inner heater 31 and an outer heater. An inner heater 31 and an outer heater 35 are connected to the temperature control units 32 and 36, respectively.

In this case, each of the temperature controllers 32 and 36 may be provided with RF filters 31b and 35b, respectively, and the inner heater 31 and the outer heater 35 may be connected by the ON / OFF relays 31a and 35a. have.

In addition, the electrostatic chuck 10 is provided with temperature sensors 12 and 13 in the inner zone and the outer zone, respectively.

Therefore, the heater 30 built into the electrostatic chuck 10 can independently control the temperature of the inner zone (center) and the outer zone (outer peripheral portion) of the electrostatic chuck 10, so that the temperature of the center portion and the edge portion of the wafer W is adjusted. Will be able to control each.

Hereinafter, the oxide etching method of the multi-stack layer mask structure using the hybrid plasma source and the electrostatic chuck of the present invention will be described in detail with reference to FIGS. 4 to 6.

4 is a flowchart of an oxide etching method of a multi-stack layer mask structure using a hybrid plasma source and an electrostatic chuck of the present invention, FIG. 5 is a schematic diagram showing two heating modes of an electrostatic chuck, and FIG. 6 is a multi-layer of the present invention. The etching process diagram by the stack layer etching method is shown.

As shown, the present invention includes an electrostatic chuck heating step S10, a mask layer etching step S20, a chamber stabilization step S30, and an oxide film etching step S40.

First, in the electrostatic chuck heating step S10, when the wafer W, which is an object to be etched, is transferred into the reaction chamber 100 and placed on the top of the electrostatic chuck 10, the electrostatic chuck 10 temperature control unit 32. 36 turns on the ON / OFF relays 31a and 35a to heat the electrostatic chuck 10 by applying a current to the heater 30.

In this case, the temperature controllers 32 and 36 are optimized for the mask layer 250 etching process, and the inner and outer heaters 31 and outer heaters can maintain the appropriate temperature in the inner zone and the outer zone. AC current appropriate to each of 35 is applied.

At the same time, the reaction gas is injected into the reaction chamber 100 through the upper gas injector 110 and the side gas injector 120, and the vacuum control system operates the turbo pump 135 of the exhaust unit 130 to operate the reaction chamber. (100) to adjust the internal pressure.

When the reaction chamber 100 reaches a constant pressure, RF current is applied to the inductive coil 55 on the reaction chamber 100 to form a plasma in the reaction chamber 100.

Then, when a predetermined voltage is applied to the electrode plate 15 provided inside the electrostatic chuck 10, negative charge is charged to the wafer W, and the wafer W is fixed to the electrostatic chuck 10 by electrostatic power. Will be.

 When the wafer W is fixed, helium He for cooling the wafer W is injected from the surface of the electrostatic chuck 10, so that the heat of the electrostatic chuck 10 is transferred to the wafer W through the injected helium. It is delivered.

Therefore, the wafer W independently maintains the temperature at which the center and edge portions are optimized by the inner heater 31 and the outer heater 35 of the electrostatic chuck 10.

As described above, when the fixing of the wafer W and the heating of the electrostatic chuck 10 are completed, the mask layer etching step S20 of etching the mask layer 250 is performed.

In terms of the etching process, the etching process of the present invention consists of two steps.

In other words, the oxide etch process of the multi-stack layer mask structure is composed of a multi-stack mask layer (Step 1) and an oxide etch (Step 2), and if there is no CD bias between each step, Since the CD formed in Step 1 influences the final CD after all the etching processes are completed, the CD of the mask layer 250 is controlled through the temperature control of the wafer W by adjusting the heater 30 of the electrostatic chuck 10. This allows full CD control.

On the other hand, the etching of the mask layer 250 is a process that relies more on chemical reaction by Radical than physical reaction by Ion Energy.

In the conventional method, a high bias power has to be applied to secure a large number of radials. However, in the present invention, a large amount of radials is mixed by using a hybrid plasma source, that is, a bias power and a coil current. To secure.

Therefore, since a relatively low bias power can be used, there is no problem in using the electrostatic chuck 10 heater 30 (a simple RF filtering circuit can eliminate the interference of RF to the heater). During the etching process, the electrostatic chuck 10 is used in the heated mode as shown in FIG. 5A to control the CD of the center and the edge of the wafer W. FIG.

At this time, since the inner zone and the outer zone of the electrostatic chuck 10 can be set to different temperatures, the CD in the center and the edge of the wafer W can be controlled independently.

That is, the present invention controls the amount of polymer by controlling the temperature of the electrostatic chuck 10 to remove the CD deviation of the center and the edge of the wafer (W).

As the etching process proceeds, the polymer layer that interferes with the etching of the wafer W is accumulated on the surface at the same time as the etching proceeds (Polymer Deposition), and the polymer deposition is usually formed on the pattern side (Polymer Passivation). It also has a big impact on CDs.

In other words, when the temperature of the wafer W is high, the polymer passivation action in which the polymer is deposited on the pattern side is reduced, so that the etching speed to the side of the pattern is accelerated, which directly affects the CD.

Of course, if the temperature of the wafer W is low, the opposite phenomenon occurs.

On the other hand, the oxide film etching step (S50) corresponds to the Dielectric Etch (dielectric etching) process, and is a process to apply a high bias power, so that the electrostatic chuck 10 is blocked by cutting off the current connected to the electrostatic chuck 10 heater. By turning off the heating, the electrostatic chuck 10 is used in the normal mode as shown in FIG.

In the case of using the electrostatic chuck 10 by the above method, since the temperature range of the electrostatic chuck 10 corresponds to both low and high temperatures, the electrostatic chuck 10 has a large chucking force depending on the temperature. It is desirable to be designed to have a specific resistance value designed so as not to change.

Meanwhile, in the mask layer etching step S20, the mask layer 250 on the wafer W is etched and patterned into a specific pattern.

As shown in FIG. 6A, the wafer W includes a mask layer 250 in which a hard mask layer 210 and an anti-reflection film 220 are sequentially stacked on an oxide 200. The stack is formed and a photoresist layer 230 is formed on the anti-reflection film 220 to etch the mask layer 250.

At this time, the anti-reflection film 220 is to minimize the light reflection generated during the exposure process for forming the pattern of the upper photoresist layer 230, BARC (Bottom Anti Reflective Coating) or 'SiON' may be applied.

Meanwhile, the hard mask layer 210 may be formed of an amorphous carbon layer (ACL).

The mask layer etching step 250 is specific to the photoresist layer 230 as shown in FIG. 6B through an exposure process of first irradiating light selectively onto the photoresist layer 230 applied to the uppermost layer. CD 235 of the pattern is formed.

As described above, the antireflection film 220 and the hard mask layer 210 are sequentially etched using the photoresist layer 230 patterned through a photolithography process as an etching mask.

In this case, an appropriate reaction gas is injected into the reaction chamber 100 to perform the etching process of the mask layer 250, and at the same time, the ICP source 50 applies an RF current to the inductive coil 55. The CCP source 60 generates plasma in the reaction chamber 100 by applying bias power to the electrostatic chuck 10.

 At this time, the inner zone and the outer zone of the electrostatic chuck 10 are heated to different temperatures while the mask layer 250 is etched and thus transferred to the center and the edge of the wafer W. The heat will be different.

Therefore, since the heat transferred to the wafer W determines the amount of polymer accumulated on the wafer W during the etching process, the temperature of the center portion and the edge portion of the wafer W is controlled. It is possible to independently adjust the center of the (W) and the CD of the edge portion.

Here, the mask layer etching step 250 generates a plasma using the ICP source 50 together without applying a high bias power to the electrostatic chuck 10, thereby etching by radical chemical reaction. This can be done sufficiently.

In this case, the oxide film 200 is etched by reacting with the plasma for a predetermined time by the portion of the hard mask layer 210 that is exposed to the CD, thereby ignoring the CD bias generated during the etching process. As shown in FIG. 6C, the CD 215 determined in the hard mask layer 210 determines the final CD 205.

Meanwhile, the chamber stabilization step S30 is a step for preparing the oxide film etching step S50 and has a stabilizing time for stabilizing the reaction chamber 100.

In the oxide film etching step S50, since a high bias power is used, temperature control of the electrostatic chuck 10 becomes very difficult.

Therefore, after cooling the electrostatic chuck 10 during the chamber stabilization step (S30), by turning off the ON / OFF relays (31a, 35a) to cut off the current applied to the heater 30, as shown in Figure 5 (b) As described above, the electrostatic chuck 10 is switched to a normal mode.

In addition, the chamber stabilization step (S30) is to prepare the next etching process by discharging the reaction gas, the reaction by-products such as polymer or polymer (particle), etc. during the etching process of the mask layer 250 to the outside through the exhaust.

On the other hand, the oxide film etching step S50 is a process of patterning the oxide film 200 on the wafer W using the hard mask layer 210 etched in the mask layer etching step S20 as an etching mask (FIG. 6C). , (d)].

Therefore, in the oxide film etching step S50, plasma is generated by etching a suitable reaction gas into the reaction chamber 100 and applying a high bias power to the electrostatic chuck 10 to etch the oxide film 200.

At this time, the oxide film etching step (S50) is to apply the high bias power (Bias Power) to proceed the etching mainly on the physical reaction by the ion energy, wherein the bias power of the different frequency RF generators 2,3 It is applied to the reaction chamber 100 via (61, 65) so that the dual frequency bias power is used.

The bias power applied here is preferably set to 4 kw or more due to the characteristics of the oxide film etching process.

As shown in FIG. 6D, when the oxide film etching step S50 is completed, the wafer W may be dechucked and transferred to a subsequent process.

Therefore, according to the present invention, the plasma is generated using a hybrid plasma source, thereby stably controlling the temperature of the heater 30 installed in the electrostatic chuck 10 so that the CD at the center and the edge of the wafer W is stable. The difference can be eliminated, and the electrostatic chuck 10 heater 30 is separated into the inner zone and the outer zone to independently and precisely control the temperature of the center portion and the edge portion of the wafer W, thereby providing a wafer W. The independent CD can be controlled to effectively compensate the difference between the etch rate and the CD in the center and edge of the wafer (W) to ensure etching uniformity on the entire surface of the wafer (W) It will be possible.

As described above, the exemplary embodiments are merely described as examples for convenience of description, and thus are not intended to limit the scope of the claims, and may be modified and applied in various forms within the technical scope of the present invention.

Description of the Related Art [0002]
10: electrostatic chuck 12,13: temperature sensor
15: electrode plate 30: heater
31: inner heater 35: outer heater
31a, 35a: ON / OFF relay 31b, 35b: RF filter
32,36: Temperature control part 50: ICP source
55: inductive coil 60: CCP source
61: RF Generator 2
65: RF Generator 3
100: reaction chamber 110: upper gas injector
120: side gas injector 130: exhaust
135: turbo pump
140: cathode assembly 150: RF shield cover
200: oxide film 205,215,235: CD
210: hard mask layer 220: antireflection film
230 photoresist layer 250 mask layer
S10: electrostatic chuck heating step S20: mask layer etching step
S23: anti-reflection film etching step
S25 hard mask etching step
S30: Chamber stabilization step
S50: oxide etching step
W: Wafer

Claims (7)

delete An electrostatic chuck heating step of loading wafers on the electrostatic chuck and optimizing the temperature of the inner zone and the outer zone of the electrostatic chuck after applying current to the heater of the electrostatic chuck;
Hybrid Plasma consisting of ICP source (Inductive Coil Plasma Source) using inductive coil located on top of reaction chamber A mask layer etching step of etching a mask layer by generating a plasma in the reaction chamber by turning on a source;
A reaction chamber stabilizing step of cutting off the current applied to the heater of the electrostatic chuck, cooling the electrostatic chuck to return to the normal state, and preparing a next etching process; And
An oxide film etching step of etching an oxide film using a mask pattern formed in the mask layer etching step as an etching mask by applying a bias power from the CCP source to the electrostatic chuck;
Oxide film etching method of a multi-stack layer mask structure using a hybrid plasma source and an electrostatic chuck heater comprising a. The method of claim 2,
The electrostatic chuck heating step,
The heater is separated from the inner zone and the outer zone of the electrostatic chuck independently so that the temperature control is possible independently of the center and the edge of the wafer. Oxide film etching method of multi-stack layer mask structure using heater. The method of claim 3,
An oxide etching method of a multi-stack layer mask structure using a hybrid plasma source and an electrostatic chuck heater, characterized in that the heaters of the electrostatic chuck are respectively provided with ON / OFF relays to control the temperature independently. The method of claim 2,
The mask layer etching step,
An oxide film etching method of a multi-stack layer mask structure using a hybrid plasma source and an electrostatic chuck heater, comprising: an anti-reflection film etching step and a hard mask etching step of etching an amorphous carbon layer under the anti-reflection film. The method of claim 2,
The mask layer etching step,
Oxide etching of a multi-stack layer mask structure using a hybrid plasma source and an electrostatic chuck heater, characterized in that etching can be performed by a radical chemical reaction using a bias power and an ICP source together. Way. The method of claim 2,
The oxide layer etching step,
An etching method of an oxide film having a multi-stack layer mask structure using a hybrid plasma source and an electrostatic chuck heater, characterized in that etching is performed by applying a bias power to a physical reaction by ion energy.

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