KR101219142B1 - Display apparatus and method of the display substrate - Google Patents

Abstract

Disclosed are a display device and a method of manufacturing the same, which can improve display quality of an image. The display device includes a plurality of gate lines, a plurality of data lines, and a pixel electrode. Each of the plurality of gate lines has one adjacent line connected to each other, and the plurality of data lines extend to cross the gate lines, and have a straight shape. In addition, the pixel electrode is formed in the pixel area defined by the gate lines and the data lines, the center is bent in a direction parallel to the data lines, has a left-right symmetric shape, and is divided into a plurality of domains. Therefore, since the data lines for providing the data signal to the pixel electrode are formed in a straight line shape, the length of the data line is relatively short, thereby preventing the delay of the data signal.

Description

DISPLAY APPARATUS AND METHOD OF THE DISPLAY SUBSTRATE}

1 is a plan view illustrating a display device according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

3 is a plan view illustrating a display device according to a second exemplary embodiment of the present invention.

4 is a cross-sectional view taken along line II-II ′ of FIG. 3.

5 is a plan view illustrating a display device according to a third exemplary embodiment of the present invention.

6 is a plan view illustrating a display device according to a fourth exemplary embodiment of the present invention.

7 is a plan view illustrating a display device according to a fifth exemplary embodiment of the present invention.

8 is a plan view illustrating a display device according to a sixth exemplary embodiment of the present invention.

9 is a plan view illustrating a display device according to a seventh exemplary embodiment of the present invention.

10A through 10D are plan views illustrating manufacturing of the display device according to the first exemplary embodiment of the present invention illustrated in FIG. 1.

<Description of the symbols for the main parts of the drawings>

SAP1, SPA2, SAP3: first to third sub pixel regions

STL1, STL2: first and second storage lines

102, 104: 1-1st and 1-2th electrode parts

110,210,310: first to third TFT

202, 204: 2-1 and 2-2 electrode portions

302, 304: 3-1 and 3-2 electrode portions

The present invention relates to a display device and a manufacturing method thereof, and more particularly, to a display device having a structure capable of improving display quality and a method of manufacturing the same.

In general, a liquid crystal display device includes a first electrode, a second electrode, one or two substrates for forming the electrodes, and a liquid crystal layer disposed between the electrodes to form an electric field. do.

By applying voltage to the first and second electrodes, an electric field is formed between the first and second electrodes. The liquid crystal molecules of the liquid crystal layer are rearranged by the electric field, thereby changing the light transmittance of light passing through the liquid crystal layer and displaying an image from the liquid crystal display.

The liquid crystal display device has an advantage of being thin in comparison with a cathode ray tube type display device. However, the liquid crystal display has a disadvantage in that the viewing angle is narrower than that of the cathode ray tube display.

In order to improve the narrow viewing angle of the liquid crystal display device, a liquid crystal display device having a patterned vertical alignment (PVA) mode, a multi-domain vertical alignment (MVA) mode, and an in-plane switching (IPS) mode have been developed. have.

The PVA mode liquid crystal display includes a transparent electrode having an opening pattern for dividing a plurality of domains of the liquid crystal layer in a unit pixel area. Here, the liquid crystal molecules are arranged in different directions between the domains of the plurality of divided liquid crystal layers, thereby improving the viewing angle.

In the PVA mode liquid crystal display, the transparent electrode has a V shape to improve light transmittance characteristics. In this case, the data line has a zigzag shape to correspond to the transparent electrode.

Therefore, as the data line has a zigzag shape, the length of the data line becomes longer and the wiring resistance of the data line increases. Therefore, a liquid crystal display including a zigzag data line has a problem in that the display quality of an image is degraded due to a transmission delay of a data signal.

Accordingly, an object of the present invention is to provide a display device capable of preventing a transmission delay of a data signal.

Another object of the present invention is to provide a method of manufacturing the display device.

A display device according to the present invention for achieving the above object includes a plurality of gate lines, a plurality of data lines and a pixel electrode. One end of each of the plurality of gate lines is connected to each other by two adjacent lines, and the plurality of data lines extend to cross the gate lines, and have a straight shape. In addition, the pixel electrode is formed in a pixel region defined by the gate lines and the data lines, the center is bent in a direction parallel to the data lines, and has a left-right symmetrical shape and is divided into a plurality of domains. do.

In order to achieve another object of the present invention, a plurality of gate lines, one end of which is adjacent to each other, are formed on the substrate, and a plurality of data lines extending to intersect the gate lines and having a straight line shape are formed. do. Next, a pixel electrode formed in the pixel area defined by the gate lines and the data lines, the center of which is bent in a direction parallel to the data lines, has a left-right symmetric shape, and is divided into a plurality of domains. Form.

According to such a display device and a method of manufacturing the same, since data lines for providing a data signal to a pixel electrode having a V or M shape are formed in a straight line shape, the length of the data line is relatively short to prevent delay of the data signal. can do.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a display device according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

As shown in FIG. 1, the display device according to the present exemplary embodiment includes a plurality of gate lines GL1, GL2, GL3, GL4,... And gate lines GL1, extending in the first direction D1. It includes a plurality of data lines DL1, DL2, DL3, ... extending in the second direction D2 to intersect GL2, GL3, GL4, ...).

The pixel area PA is defined by the gate lines GL1, GL2, GL3, GL4... And the data lines DL1, DL2, DL3,. The plurality of gate lines GL1, GL2, GL3, GL4, ... are bent in the second direction D2 to have a V shape so as to correspond to one pixel area, and the V shape It has a zigzag shape repeated in the first direction D1. At this time, the gate lines GL1, GL2, GL3, GL4, ... are bent at an angle of about 90 degrees. In addition, two adjacent gate lines are formed such that one end is connected to each other. That is, one end of the first gate line GL1 and the second gate line GL2 is connected to each other, and one end of the third gate line GL3 and the fourth gate line GL4 is connected to each other. Accordingly, the same gate signal is provided to the first and second gate lines GL1 and GL2, and the same gate signal is provided to the third and fourth gate lines GL3 and GL4.

In addition, the plurality of data lines DL1, DL2, DL3,... Extend in a straight line in the second direction D2 to correspond to both ends and the center of the pixel area PA. That is, the first data line DL1 is formed to be adjacent to one end of the pixel area PA, and the second data line DL2 is formed to correspond to the center of the pixel area PA. DL3 is formed to be adjacent to the other end of the pixel area PA.

The pixel area PA includes a first sub pixel area SPA1, a second sub pixel area SPA2, and a third sub pixel area SPA3 sequentially arranged in the second direction D2. The first sub pixel area SPA1 is an area in which red is displayed by a data signal provided from the second data line DL2, and the second sub pixel area SPA2 is a data signal provided from the first data line DL1. Is a region in which green color is displayed, and the third sub pixel region SPA3 is a region in which blue color is displayed by the data signal provided from the third data line DL3.

In addition, a first pixel electrode and a first TFT 110 are formed in the first sub pixel area SPA1. The first pixel electrode has a 'V' shape in which a center thereof is bent in a second direction D2 to correspond to gate lines GL1, GL2, GL3, GL4,...

The first pixel electrode has a symmetrical shape with respect to the second data line DL2. That is, the first pixel electrode has a first-first electrode portion 102 positioned on the left side with respect to the second data line DL2 and a first-second electrode portion positioned on the right side with respect to the second data line DL2. It consists of 104. In this case, the first-first electrode part 102 and the first-second electrode part 104 are partially connected to each other only in an area adjacent to the first gate line GL1.

That is, as shown in FIG. 2, most of the first pixel electrode formed on the display substrate 400 is removed from a region overlapping with the second data line DL2, thereby being symmetrically symmetrically around the second data line DL2. The first-first electrode portion 102 and the first-second electrode portion 104.

A passivation layer 410 having a very thin thickness is formed between the second data line DL2 and the first-first and first-second electrode parts 102 and 104. As described above, since the formation thickness of the protective film 410 is thin, the coupling capacitance between the first-first and first-second electrode parts 102 and 104 and the second data line DL2 is large. Therefore, in the present exemplary embodiment, since the first-first electrode part 202 and the first-second electrode part 204 are separated from the left and right in a region overlapping with the second data line DL2, only a part thereof is connected. The occurrence of coupling capacitance is thus significantly reduced.

Referring back to FIG. 1, the first TFT 110 includes a first gate electrode 111, a first active pattern 112, a first source electrode 113, and a first drain electrode 114. The first active pattern 112 is formed to overlap a portion of the first gate line GL1, and the first source electrode 113 is formed to branch from the second data line DL2. In this case, the first gate electrode 111 is defined as a region overlapping the first active pattern 112 of the first gate line GL1. The first drain electrode 114 is spaced apart from the first source electrode 113 and electrically connected to the first-first electrode portion 102 of the first pixel electrode 100 through a contact hole (not shown). Connected.

The first TFT 110 having the above-described configuration is switched to the gate signal provided from the first gate line GL1, and thus the data signal from the second data line DL2 is transferred to the first-first electrode portion 102. ) And the first and second electrode portions 104.

Meanwhile, the second pixel electrode 200 and the first TFT 210 are formed in the second sub pixel area SPA2. The second pixel electrode 200 has a 'V' shape in which a center is bent in a second direction D2 to correspond to the gate lines GL1, GL2, GL3, GL4,... The second pixel electrode 200 includes a 2-1 electrode portion 202 and a 2-2 electrode portion 204. In this case, since the 2-1 electrode part 202 and the 2-2 electrode part 204 have the same shape as the 1-1 electrode part 102 and the 1-2 electrode part 104, Detailed description will be omitted.

In addition, the second TFT 210 includes a second gate electrode 211, a second active pattern 212, a second source electrode 213, and a third drain electrode 214. The second active pattern 212 is formed to overlap a portion of the second gate line GL2, and the second source electrode 213 is formed to branch from the first data line DL1. In this case, the second gate electrode 211 is defined as an area overlapping the second active pattern 212 of the second gate line GL2. The second drain electrode 214 is spaced apart from the second source electrode 213, and is electrically connected to the second-first electrode part 202 of the second pixel electrode 200 through a contact hole (not shown). Connected.

The second TFT 210 having the above-described configuration is switched by a gate signal provided from the second gate line GL2, and thus the data signal from the first data line DL1 is transferred to the second-first electrode portion 202. ) And the second-2 electrode portion 204. In this case, since one end of the second gate line GL2 is connected to the first gate line GL1, the gate signal from the second gate line GL2 is the same as the gate signal from the first gate line GL1.

A third pixel electrode 300 and a third TFT 310 are formed in the third sub pixel area SPA3. The second pixel electrode 300 has a 'V' shape having a center bent in a second direction D2 to correspond to the gate lines GL1, GL2, GL3, GL4,... The third pixel electrode 300 includes a 3-1 electrode part 302 and a 3-2 electrode part 304. In this case, since the 2-1 electrode part 302 and the 2-2 electrode part 304 have the same shape as the 1-1 electrode part 102 and the 1-2 electrode part 104, Detailed description will be omitted.

The third TFT 310 includes a third gate electrode 311, a third active pattern 312, a third source electrode 313, and a third drain electrode 314. The third active pattern 312 is formed to overlap a portion of the second gate line GL2, and the third source electrode 313 is formed to branch from the third data line GL3. In this case, the third gate electrode 311 is defined as a region overlapping with the third active pattern 312 of the second gate line GL2. The third drain electrode 314 is spaced apart from the third source electrode 313 and electrically connected to the third-2 electrode part 304 of the third pixel electrode 300 through a contact hole (not shown). Connected.

The third TFT 310 having the above-described configuration is switched by the gate signal from the second gate line GL2, and thus the data signal from the third data line DL3 is transferred to the 3-1 electrode part 302. ) And the third-2 electrode part 304.

A first storage line STL1 and a second storage line STL2 are further formed in the pixel area PA. The first storage line STL1 is formed in the same shape as the first gate line GL1 between the first sub pixel area SPA1 and the second sub pixel area SPA2. The second storage line STL2 is formed in the same shape as the second gate line GL2 between the third sub pixel area SPA3 and the next pixel area.

In addition, a first storage capacitor 120 is further formed in the first sub pixel area SPA1, and a second storage capacitor 220 is further formed in the second sub pixel area SPA2. A third storage capacitor 320 is further formed in the third sub pixel area SPA3.

The first storage capacitor 120 is formed by overlapping an electrode extending from the first storage line STL1 and a portion of the first drain electrode 114. The second storage capacitor 220 is formed by overlapping an electrode extending from the first storage line STL1 and a portion of the second drain electrode 214. In addition, the third storage capacitor 320 is formed by overlapping an electrode extending from the second storage line STL2 and a portion of the third drain electrode 314.

In addition, the display device according to the present exemplary embodiment is formed on the counter substrate 420 facing the display substrate 400 as shown in FIG. 2 and faces the common electrodes 430 facing the first to third pixel electrodes 100, 200, and 300. It includes more. A first portion of the common electrode 430 corresponding to the first sub pixel region SPA1 is partially removed from the center of the first-first electrode portion 102 in a shape corresponding to the first-first electrode portion 102. In the center of the −1 opening portion 432 and the 1-2 electrode portion 104, a 1-2 opening portion 434 is partially formed in a shape corresponding to the 1-2 electrode portion 104. In this case, the first sub pixel area SPA1 is divided into four domains by the first and second openings 432 and 434.

A second part of the common electrode 430 corresponding to the second sub pixel area SPA2 is partially removed in a shape corresponding to the 2-1 electrode part 202 at the center of the 2-1 electrode part 202. In the center of the −1 opening portion 442 and the second electrode portion 204, a second opening portion 444 having a portion removed in a shape corresponding to the second electrode portion 204 is formed. The second sub pixel area SPA2 is divided into four domains by the second through second openings 442 and 444.

In addition, a part of the common electrode 430 corresponding to the third sub pixel area SPA3 is removed from the center of the 3-1 electrode part 302 in a shape corresponding to the 3-1 electrode part 302. In the center of the 3-1 opening portion 452 and the 3-2 electrode portion 304, a 3-2 opening portion 454 is partially formed in a shape corresponding to the 3-2 electrode portion 304. The third sub pixel area SPA3 is divided into four domains by the third through third openings 452 and 454.

Therefore, the liquid crystal molecules in the first to third sub-pixel areas SPA1, SPA2, and SPA3 are vertically arranged in different directions for each of the domains, thereby improving response speed. In addition, as the response speed is improved, an interval between the first to third pixel electrodes 100, 200 and 300 and the first to third to second openings 432, 434, 442, 444, 452 and 454 can be widened, thereby improving the aperture ratio.

According to the present exemplary embodiment, the gate lines have a zigzag shape, the data lines have a straight shape, and most of the pixel electrodes are removed from regions overlapping the data lines. Thus, the length of the data line is reduced, and the occurrence of coupling capacitance between the data line and the pixel electrode is reduced, thereby reducing the transmission delay of the data signal.

3 is a plan view illustrating a display device according to a second exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line II-II ′ of FIG. 3.

First, the present embodiment is the same as the first embodiment except for the configuration formed to completely cover the data line in the region overlapping with the data line. Therefore, the same reference numerals are given to the same configuration as the first embodiment, and detailed description thereof will be omitted.

As shown in FIG. 3, the display device according to the present exemplary embodiment includes a plurality of gate lines GL1, GL2, GL3, GL4,... And gate lines GL1, extending in the first direction D1. It includes a plurality of data lines DL1, DL2, DL3, ... extending in the second direction D2 to intersect GL2, GL3, GL4, ...).

The gate lines GL1, GL2, GL3, GL4, ... have a shape bent in the second direction D2 to have a 'V' shape corresponding to one pixel region, and a 'V' character. The shape has a zigzag shape extending in the first direction D1.

In addition, the plurality of data lines DL1, DL2, DL3,... Extend in a straight line in the second direction D2 to correspond to both ends and the center of the pixel area PA. That is, the first data line DL1 is formed to be adjacent to one end of the pixel area PA, and the second data line DL2 is formed to correspond to the center of the pixel area PA. DL3 is formed to be adjacent to the other end of the pixel area PA.

The pixel area PA includes first to third sub pixel areas SPA1, SPA2, and SPA3 sequentially arranged in the second direction D2. The first pixel electrode 100 is formed in the first sub pixel area SPA1, and the second pixel electrode 200 is formed in the second sub pixel area SPA2. In addition, a third pixel electrode 300 is formed in the third sub pixel area SPA3.

The first to third pixel electrodes 100, 200, and 300 have a symmetrical shape with respect to the second data line DL2. In addition, the first to third pixel electrodes 100, 200, and 300 may have a shape overlapping with each other even in a region corresponding to the second data line DL2.

As shown in FIG. 4, the passivation layer 410 and the organic layer 440 are sequentially formed on the display substrate 400 on which the second data line DL2 is formed. The organic layer 440 has a relatively thicker thickness than the protective layer 410. Therefore, even when the first pixel electrode 100 and the second data line DL2 overlap with each other, the generation of the coupling capacitance is reduced by the organic layer 440. In addition, the second pixel electrode 200 and the third pixel electrode 300 also have a shape in which the second data line DL2 overlaps with each other.

5 is a plan view illustrating a display device according to a third exemplary embodiment of the present invention.

First, the present embodiment is the same as the first embodiment except for the configuration in which the pixel electrodes are completely separated in the region overlapping with the data line. Therefore, the same reference numerals are given to the same configuration as the first embodiment, and detailed description thereof will be omitted.

As shown in FIG. 5, the display device according to the present exemplary embodiment includes a plurality of gate lines GL1, GL2, GL3, GL4,..., And a second direction D2 extending in the first direction D1. It includes a plurality of data lines (DL1, DL2, DL3, ...) extended to.

The gate lines GL1, GL2, GL3, GL4, ... have a shape bent in the second direction D2 to have a 'V' shape corresponding to one pixel region, and a 'V' character. The shape has a zigzag shape extending in the first direction D1. In addition, the plurality of data lines DL1, DL2, DL3,... Extend in a straight line in the second direction D2 to correspond to both ends and the center of the pixel area PA.

The pixel area PA is defined by the gate lines GL1, GL2, GL3, GL4,... And the data lines DL1, DL2, DL3,. The pixel area PA includes a first sub pixel area SPA1, a second sub pixel area SPA2, and a third sub pixel area SPA3 sequentially arranged in the second direction D2.

The first pixel electrode including the first-first electrode part 502 and the first-second electrode part 504 is formed in the first sub pixel area SPA1. The first-first electrode part 502 is positioned on the left side with respect to the second data line DL2, and the first-second electrode part 504 is located on the right side. In this case, the first-first electrode part 502 and the second-second electrode part 504 have a shape separated from each other. Accordingly, the data signal is applied to the first-first TFT 510 and the first-second electrode part 502 for providing a data signal to the first-first electrode part 502 in the first sub pixel area SPA1. A first-2 TFT 520 for providing is formed. In this case, since the first-first TFT 510 and the first-second TFT 520 have the same configuration as the first TFT 110 of FIG. 1, detailed description thereof will be omitted.

A second pixel electrode including the 2-1 electrode part 202 and the 2-2 electrode part 204 is formed in the second sub pixel area SPA2, and a third pixel electrode is formed in the third sub pixel area SPA3. A third pixel electrode including the −1 electrode portion 302 and the third-2 electrode portion 304 is formed. A part of the 2-1 electrode part 202 and the 2-2 electrode part 204 is connected to each other, and a part of the 3-1 electrode part 302 and the 3-2 electrode part 304 are also mutually different. Connected. Accordingly, the second TFT 210 and the third TFT 310 are formed in the second sub pixel area SPA2 and the third sub pixel area SPA3, respectively.

In the present exemplary embodiment, only the first-first electrode part 502 and the first-second electrode part 504 are separated from each other left and right with respect to the second data line DL2, but the second pixel electrode ( The second-first electrode part 202 and the second-second electrode part 204 of the 200, and the third-first electrode part 302 and the third-second electrode part 304 of the third pixel electrode 300. May have shapes separated from each other. In this case, two TFTs are provided in the second pixel electrode 200 and the third pixel electrode 300 to provide data signals to the electrode portions separated from each other.

6 is a plan view illustrating a display device according to a fourth exemplary embodiment of the present invention.

First, the position of the data line in this embodiment is different from that in the first embodiment, and the rest of the configuration is the same. Therefore, the same components as those in the first embodiment are assigned the same numbers, and detailed description thereof will be omitted.

As shown in FIG. 6, the display device according to the present exemplary embodiment includes a plurality of gate lines GL1, GL2, GL3, GL4,... And gate lines GL1, extending in the first direction D1. It includes a plurality of data lines DL1, DL2, DL3, ... extending in the second direction D2 to intersect GL2, GL3, GL4, ...).

The pixel area PA is defined by the gate lines GL1, GL2, GL3, GL4,... And the data lines DL1, DL2, DL3,. The plurality of gate lines GL1, GL2, GL3, GL4, ... are bent in the second direction D2 to have a V shape so as to correspond to one pixel area, and the V shape It has a zigzag shape repeated in the first direction D1. At this time, the gate lines GL1, GL2, GL3, GL4, ... are bent at an angle of about 90 degrees. In addition, two adjacent gate lines are formed such that one end is connected to each other. That is, one end of the first gate line GL1 and the second gate line GL2 is connected to each other, and one end of the third gate line GL3 and the fourth gate line GL4 is connected to each other. Accordingly, the same gate signal is provided to the first and second gate lines GL1 and GL2, and the same gate signal is provided to the third and fourth gate lines GL3 and GL4.

In addition, the plurality of data lines DL1, DL2, DL3,... Are formed to extend in a straight line in the second direction D2 to have a predetermined distance from each other in the pixel area PA. That is, the second data line DL2 is formed at the center of the pixel area PA, and the first data line DL1 is formed at the center between the second data line DL2 and one end of the pixel area PA. The third data line DL3 is formed at the center between the second data line DL2 and the other end of the pixel area PA.

As such, as the plurality of data lines DL1, DL2, DL3,... Are formed to have a predetermined interval in the pixel area PA, parasitic capacitance between data lines positioned in adjacent pixel areas may be reduced. Can be.

In the above-described exemplary embodiment, data lines DL1, DL2, DL3,..., Arranged in the pixel area PA are arranged to have a uniform interval, but the data lines DL1, DL2, DL3, ...) may be arranged to have non-uniform spacing in the pixel area PA.

In addition, in the present embodiment, a structure in which most of the pixel electrodes are removed from a region overlapping with the data line in order to reduce parasitic capacitance between the pixel electrode and the data line is exemplified. However, when the organic layer is formed as shown in FIG. The generation of coupling capacitance can be reduced even if the pixel electrode is not removed in the region.

7 is a plan view illustrating a display device according to a fifth exemplary embodiment of the present invention.

As shown in FIG. 7, the display device according to the present exemplary embodiment includes a plurality of gate lines GL1, GL2, GL3, GL4,... And gate lines GL1, extending in the first direction D1. It includes a plurality of data lines DL1, DL2, DL3, ... extending in the second direction D2 to intersect GL2, GL3, GL4, ...).

The pixel area PA is defined by the gate lines GL1, GL2, GL3, GL4,... And the data lines DL1, DL2, DL3,. The plurality of gate lines GL1, GL2, GL3, GL4,... Are bent in the second direction D2 to have a 'V' shape to correspond to one pixel area, and the 'V' shape It has a zigzag shape repeated in the first direction D1. At this time, the gate lines GL1, GL2, GL3, GL4, ... are bent at an angle of about 90 degrees. In addition, two adjacent gate lines are formed such that one end is connected to each other. That is, one end of the first gate line GL1 and the second gate line GL2 is connected to each other, and one end of the third gate line GL3 and the fourth gate line GL4 is connected to each other. Accordingly, the same gate signal is provided to the first and second gate lines GL1 and GL2, and the same gate signal is provided to the third and fourth gate lines GL3 and GL4.

The pixel area PA includes a first sub pixel area SPA1, a second sub pixel area SPA2, and a third sub pixel area SPA3 sequentially arranged in the second direction D2. In the first to third sub-pixel areas SPA1, SPA2, and SPA3, the centers of the first to third sub-pixel regions SPA1, SPA2, and SPA3 are bent in the second direction D2 to correspond to the gate lines GL1, GL2, GL3, GL4,. It has two 'M' shaped shapes.

The first sub pixel area SPA1 is an area in which red is displayed by a data signal provided from the first data line DL1, and the second sub pixel area SPA2 is a data signal provided from the second data line DL2. Is a region in which green color is displayed, and the third sub pixel region SPA3 is a region in which blue color is displayed by the data signal provided from the third data line DL3.

A first pixel electrode and a first TFT 710 are formed in the first sub pixel area SPA1. The first pixel electrode has an 'M' shape in which two 'V' letters whose centers are bent in a second direction D2 to correspond to the gate lines GL1, GL2, GL3, GL4,... .

The first pixel electrode includes a first-first electrode part 702, a first-second electrode part 704, a first-three electrode part 706, and a first-fourth electrode part 708. The first-first electrode part 702 and the first-second electrode part 704 are symmetrical with respect to the first data line DL1. That is, the first-first electrode part 702 is located on the left side with respect to the first data line DL1, and the first-second electrode part 704 is located on the right side with respect to the first data line DL1. In addition, the 1-3 electrode portion 706 and the 1-4 electrode portion 708 are symmetrical about the third data line DL3. That is, the 1-3 electrode portion 706 is located on the left side with respect to the third data line DL3, and the 1-3-4 electrode portion 708 is located on the right side with respect to the third data line DL3. The first-first and first-second electrode parts 702 and 704 and the first-three and first-fourth electrode parts 706 and 708 are symmetrically symmetric with respect to the second data line DL2.

The first to third data lines DL1, DL2, and DL3 may reduce the coupling capacitance between the first to third data lines DL1, DL2, and DL3. In the region overlapping with), most have a shape removed.

The first TFT 710 includes a first gate electrode, a first active pattern, a first source electrode and a first drain electrode branched from the first data line DL1. The first gate electrode is defined as a region in which the first active pattern overlaps among the first gate lines GL1. In addition, the first drain electrode is electrically connected to the first-first electrode part 702 through a contact hole (not shown).

The first TFT 710 having the above-described configuration is switched by a gate signal provided from the first gate line GL1, so that the data signal from the first data line DL1 is first to first to first. -4 electrode portions 702, 704, 706, 708.

A second pixel electrode and a second TFT 810 are formed in the second sub pixel area SPA2. The second pixel electrode has an 'M' shape in which two 'V' letters are bent in the second direction D2 so as to correspond to the gate lines GL1, GL2, GL3, GL4,... .

The second pixel electrode includes a 2-1 electrode portion 802, a 2-2 electrode portion 804, a 2-3 electrode portion 806, and a 2-4 electrode portion 808. The 2-1 th electrode portion 802 is positioned on the left side with respect to the first data line DL1, and the 2-2 th electrode portion 804 is positioned on the right side with respect to the first data line DL1. In addition, the 2-3 electrode portion 806 is positioned on the left side with respect to the third data line DL3, and the 2-4 electrode portion 808 is positioned on the right side with respect to the third data line DL3. In addition, the 2-1 and 2-2 electrode parts 802 and 804 and the 2-3 and 2-4 electrode parts 806 and 808 are symmetrical with respect to the second data line DL2.

The 2-1 to 2-4 electrode parts 802, 804, 806, and 808 may include the first to third data lines DL1, DL2, and DL3 in order to reduce coupling capacitance between the first to third data lines DL1, DL2, and DL3. In the region overlapping with), most have a shape removed.

The second TFT 810 includes a second gate electrode, a second active pattern, a second source electrode and a second drain electrode branched from the second data line DL2. The second gate electrode is defined as a region overlapping the second active pattern of the second gate line GL2. The second drain electrode is electrically connected to the second-2 electrode part 804 through a contact hole (not shown).

The second TFT 810 having the above-described configuration is switched by a gate signal provided from the second gate line GL2, and thus the data signals from the second data line DL2 are converted into the second through second through second through second gate lines GL2. Four electrode portions 802, 804, 806 and 808. In this case, since the second gate line GL2 has a structure connected to the first gate line GL1, the gate signal from the second gate line GL2 is the same as the gate signal from the first gate line GL1. .

Meanwhile, a third pixel electrode and a third TFT 910 are formed in the third sub pixel area SPA3. The third pixel electrode has an 'M' shape in which two 'V' letters are bent in the second direction D2 so as to correspond to the gate lines GL1, GL2, GL3, GL4,... .

The third pixel electrode includes a 3-1 electrode portion 902, a 3-2 electrode portion 904, a 3-3 electrode portion 906, and a 3-4 electrode portion 908. The 3-1 th electrode portion 902 is located on the left side with respect to the first data line DL1, and the 3-2 th electrode portion 904 is located on the right side with respect to the first data line DL1. In addition, the third-3 electrode part 906 is located on the left side with respect to the third data line DL3, and the third-4 electrode part 908 is located on the right side with respect to the third data line DL3. In addition, the 3-1 and 3-2 electrode parts 902 and 904 and the 3-3 and 3-4 electrode parts 906 and 908 are symmetrical with respect to the second data line DL2.

The 3-1 to 3-4 electrode parts 902, 904, 906, and 908 may have first to third data lines DL1, DL2, and DL3 in order to reduce coupling capacitance between the first to third data lines DL1, DL2, and DL3. In the region overlapping with), most have a shape removed.

In addition, the third TFT 910 includes a third gate electrode, a third active pattern, a third source electrode and a third drain electrode branched from the second data line DL2. The third gate electrode is defined as a region overlapping the third active pattern of the second gate line GL2. The third drain electrode is electrically connected to the third-4 electrode part 908 through a contact hole (not shown).

The third TFT 910 having the above-described configuration is switched by the gate signal from the second gate line GL2, and thus the data signal from the third data line DL3 is converted into the third through third through third gates. Four electrode portions 902, 904, 906, and 908.

In addition, the first storage line STL1 and the second storage line STL2 are further formed in the pixel area PA. The first storage line STL1 is formed in the same shape as the first gate line GL1 between the first sub pixel area SPA1 and the second sub pixel area SPA2. The second storage line STL2 is formed in the same shape as the second gate line GL2 between the third sub pixel area SPA3 and the next pixel area.

In addition, a first storage capacitor 720 is further formed in the first sub pixel area SPA1, and a second storage capacitor 820 is further formed in the second sub pixel area SPA2. A third storage capacitor 920 is further formed in the third sub pixel area SPA3.

In addition, the display device according to the present exemplary embodiment further includes a common electrode (not shown) facing the first to third pixel electrodes 700, 800, and 900.

The common electrode corresponding to the first sub pixel area SPA1 may have a first-first opening 732, a first-second opening 734, a first-third opening 736, and a first-fourth opening ( 738 is formed. The first-first opening 732 is partially formed in a shape corresponding to the first-first electrode part 702 at the center of the first-first electrode part 702, and the first-second opening 734 is formed. ) Is formed by removing a portion of the center of the 1-2 electrode portion 704 in a shape corresponding to the 1-2 electrode portion 704. In addition, the first opening 736 is partially formed in a shape corresponding to the first opening electrode 706 at the center of the first opening electrode 706, and the first opening 4 ( 738 is formed by removing a portion of the shape of the first-4 electrode portion 708 corresponding to the first-4 electrode portion 708. Therefore, the first sub pixel area SPA1 is divided into eight domains by the first-first through first-fourth openings 732, 734, 736, and 738.

In addition, the common electrode corresponding to the second sub pixel area SPA2 may have a second-first opening 832, a second-second opening 834, a second-three opening 836, and a second-fourth opening ( 838 is formed. The second-first opening 832 is formed by removing a portion of the second-first opening 832 in a shape corresponding to the second-first electrode 802 at the center of the second-first electrode 802, and then opening the second-second opening 834. ) Is formed in a shape corresponding to the second-2 electrode portion 804 at the center of the second-2 electrode portion 804 by removing a portion thereof. In addition, the second opening 836 is partially formed in a shape corresponding to the second opening electrode 806 at the center of the second opening electrode 806, and the second opening opening 836 is formed. 838 is formed by removing a portion of the shape of the second-4 electrode part 808 in the center corresponding to the second-4 electrode part 808. Accordingly, the second sub pixel area SPA2 is divided into eight domains by the second through second openings 832, 834, 836, and 838.

The common electrode corresponding to the third sub pixel area SPA3 has a 3-1 opening 932, a 3-2 opening 934, a 3-3 opening 936, and a 3-4 opening 938. ) Is formed. The 3-1 opening 932 is formed by removing a portion of the 3-1 opening 932 in a shape corresponding to the 3-1 electrode portion 902 at the center of the 3-1 electrode portion 902 and the 3-2 opening ( The part 934 is formed by removing a portion of the shape of the third-2 electrode part 904 in the center corresponding to the third-2 electrode part 904. In addition, the third opening 936 is partially formed in a shape corresponding to the third opening 906 at the center of the third opening 906, and the third opening 3 ( The 938 is formed by removing a portion of the shape of the 3-4 electrode part 908 at the center of the 3-4 electrode part 908. Accordingly, the third sub pixel area SPA3 is divided into eight domains by the third through third openings 932, 934, 936 and 938.

Accordingly, the first to third sub-pixel areas SPA1, SPA2, and SPA3 are divided into eight domains, and the liquid crystal molecules are vertically arranged in different directions for each of the domains, thereby improving response speed. In addition, as the response speed is improved, the electrode interval can be widened, and the aperture ratio is improved.

In addition, the plurality of data lines DL1, DL2, DL3,..., Extend in a straight line in the second direction D2 and are formed in the pixel area PA. That is, the first data line DL1 is formed to extend in the second direction D2 between the first-first electrode part 702 and the first-second electrode part 704, and the second data line DL2. ) Is formed to extend in the second direction D2 between the 1-2 electrode portion 704 and the 1-3 electrode portion 706. In addition, the third data line DL3 extends in the second direction D2 between the 1-3 electrode portion 706 and the 1-4 electrode portion 708.

Therefore, in the present embodiment, since the plurality of data lines DL1, DL2, DL3, ... have a straight line shape, the length of the line is relatively reduced compared to the zigzag shape, thereby preventing the delay of the data signal. do.

In addition, since the liquid crystal molecules lie in different directions as an electric field is applied between the first to first to fourth electrode parts 702, 704, 706, and 708, the texture is generated. Therefore, since the plurality of data lines DL1, DL2, DL3,... Are positioned in the region where the texture is generated, a decrease in the aperture ratio can be prevented.

8 is a plan view illustrating a display device according to a sixth exemplary embodiment of the present invention.

First, the present embodiment is the same as the fifth embodiment except for the configuration in which the pixel electrodes are completely separated from side to side at the center of the pixel region. Therefore, the same components as those in the fifth embodiment are assigned the same numbers, and detailed description thereof will be omitted.

As illustrated in FIG. 8, the pixel area PA of the display device according to the present exemplary embodiment includes a first sub pixel area SPA1, a second sub pixel area SPA2, and a third sub pixel area SPA3. .

The first to first electrode parts 1002, 1004, 1006, and 1008 in the first sub pixel area SPA1 are separated from the left and right around the second data line DL2. That is, the 1-2 electrode portion 1004 and the 1-3 electrode portion 1006 are separated from each other. Accordingly, the first-first electrode part 1002 and the first-second electrode part 1004 positioned on the left side of the second data line DL2 are connected to each other to operate as a main electrode part. In addition, the 1-3th electrode portion 1006 and the 1-4th electrode portion 1008 positioned on the right side of the second data line DL2 are connected to each other to operate as a sub-electrode portion. The main electrode part and the sub-electrode part are provided with data signals having the same voltage level or data signals having different voltage levels.

In this case, in order to provide data signals having different voltage levels from the main electrode part and the sub electrode part, TFTs are formed in the main electrode part and the sub electrode part, respectively. On the other hand, a coupling capacitor is formed in the sub-electrode part to receive the data signal through the main electrode part, thereby providing a data signal having a lower voltage level than the data signal provided in the main electrode part.

As such, when data signals having different voltage levels are provided to the main electrode part and the sub-electrode part, voltage-transmittance (or gamma curve) characteristics of the main electrode part and the sub-electrode part are different so that visibility is improved.

In addition, the second and third pixel electrodes formed in the second sub pixel area SPA2 and the third sub pixel area SPA3 have the same center on the second data line DL2 as in the first sub pixel area SPA1. It has a shape separated from side to side. That is, the second-second electrode part 1104 and the second-third electrode part 1106 of the second sub pixel area SPA2 are separated from each other. In addition, the third-second electrode part 1204 and the third-third electrode part 1206 of the third sub pixel area SPA3 are separated from each other. Accordingly, the second and third sub pixel areas SPA2 and SPA3 are also divided into a main electrode part and a sub electrode part around the second data line DL2, similarly to the first sub pixel area SPA1.

9 is a plan view illustrating a display device according to a seventh exemplary embodiment of the present invention.

First, the present embodiment is the same as the fifth embodiment except for the configuration in which the pixel electrodes are entirely connected at the center of the pixel region, and the positions of the data lines are different. Therefore, the same components as those in the fifth embodiment are assigned the same numbers, and detailed description thereof will be omitted.

As shown in FIG. 9, in the display device according to the present exemplary embodiment, the pixel area PA includes a first sub pixel area SPA1, a second sub pixel area SPA2, and a third sub pixel area SPA3. .

The first sub pixel area SPA1 may be formed into the first-first electrode part 1002, the first-second electrode part 1004, the first-third electrode part 1006, and the first-fourth electrode part 1008. Is done. At this time, only a part of the first-first electrode part 1002 and the first-second electrode part 1004 are connected to each other, and the first-second electrode part 1004 and the first-third electrode part 1006 are integral with each other. Leads to. Only a part of the 1-3 electrode portion 1006 and the 1-4 electrode portion 1008 are connected to each other.

Meanwhile, since the second and third sub pixel areas SPA2 and SPA3 also have the same configuration as the first sub pixel area SPA1, a detailed description thereof will be omitted.

In addition, the data lines DL1, DL2, DL3,... Are positioned in an empty space between the texture generation region of the pixel region PA and the pixel region PA. That is, the first data line DL1 is formed to extend in the second direction D2 between the first-first electrode portion 1002 and the first-second electrode portion 1004, and the second data line DL2. ) Is formed to extend in the second direction D2 between the 1-3 electrode portion 1006 and the 1-4 electrode portion 1008. In addition, the third data line DL3 is formed to extend in the second direction D2 between the first-fourth electrode part 1008 and the next pixel area. Therefore, since the plurality of data lines DL1, DL2, DL3, ... are positioned in the region where the texture is generated, a decrease in the aperture ratio can be prevented.

10A through 10D are plan views illustrating manufacturing of the display device according to the first exemplary embodiment of the present invention illustrated in FIG. 1.

As shown in FIG. 10A, a first conductive thin film is formed on the display substrate 100 (see FIG. 2), and a plurality of gate lines GL1, GL2, GL3, and GL4 are formed using an etching mask having a predetermined pattern. , ...). The plurality of gate lines GL1, GL2, GL3, GL4,... Have a 'V' shape with respect to one pixel area, and have a zigzag shape in which 'V' is extended in a first direction D1. Have In addition, the plurality of gate lines GL1, GL2, GL3, GL4,..., Two adjacent lines are connected to each other at one end. That is, one end of the first gate line GL1 and the second gate line GL2 is connected to each other, and one end of the third gate line GL3 and the fourth gate line GL4 is connected to each other.

Meanwhile, when the plurality of gate lines GL1, GL2, GL3, GL4,..., Are formed, they have the same shape as the plurality of gate lines GL1, GL2, GL3, GL4, ... in the pixel area PA. First and second storage lines STL1 and STL2 are formed. That is, the first storage line STL1 is formed between the first gate line GL1 and the second gate line GL2. The second storage line STL2 is formed between the second gate line GL2 and the third gate line GL3.

In addition, the first electrode 122, the second electrode 222, and the third electrode (not shown) may extend from the first and second storage lines STL1 and STL2 to form the first to third storage capacitors 120, 220, and 320, respectively. 322 is formed.

Next, referring to FIG. 10B, a semiconductor layer is formed on the display substrate 400 on which the plurality of gate lines GL1, GL2, GL3, GL4,... First to third active patterns 112, 211 and 311 for forming the TFTs 110, 210 and 310 are formed. The first active pattern 112 is formed on a part of the first gate line GL1, and the second active pattern 212 and the third active pattern 312 are formed on a part of the second gate line GL2. .

In this case, an area overlapping the first gate line GL1 and the first active pattern 112 is defined as the first gate electrode 111. A region where the second gate line GL2 and the second active pattern 212 overlap each other is defined as a second gate electrode 211, and the second gate line GL2 and the third active pattern 312 overlap each other. The region is defined as the third gate electrode 311.

As shown in FIG. 10C, a second conductive thin film is formed on the display substrate 400 on which the first to third active patterns 112, 212 and 312 are formed. The second conductive thin film is etched using an etching mask to form a plurality of data lines DL1, DL2, DL3,... The plurality of data lines DL1, DL2, DL3 ... cross the plurality of gate lines GL1, GL2, GL3, GL4, ... and extend in a second direction D2. Has Therefore, according to the present embodiment, since the length is reduced relative to the zigzag data line, delay of the data signal can be prevented.

In this case, first to third source electrodes 113, 213, and 313 and first to third drain electrodes 114, 214, and 314 branched from the plurality of data lines DL1, DL2, DL3,... As the portions of the first to third drain electrodes 114, 214, and 314 overlap the first to third electrodes 122, 212, and 312, first to third storage capacitors 120, 220, and 320 are formed, respectively.

Referring to FIG. 10D, the passivation layer 410 (see FIG. 2) is formed on the display panel 400 on which the plurality of data lines DL1, DL2, DL3,... Subsequently, a material forming a transparent conductive thin film is deposited on the display substrate 400 on which the passivation layer 410 is formed, and then patterned to form first to third pixel electrodes 100, 200, and 300 in the pixel area PA. The first pixel electrode 100 includes the first-first electrode portion 102 and the first-second electrode portion 104, and the second pixel electrode 200 includes the second-first electrode portion 202 and the second pixel electrode 200. It consists of the 2-2 electrode part 204. The third pixel electrode 300 includes a 3-1 electrode part 302 and a 3-2 electrode part 304. In this case, the first to third pixel electrodes 100, 200, and 300 may be connected to the data lines DL1, DL2, DL3,... To reduce coupling capacitance with the data lines DL1, DL2, DL3,... The overlapping area has a removed shape.

On the other hand, when the organic film 440 (see FIG. 4) having a thick formation thickness is formed on the passivation layer 410, the coupling capacitance with the data lines DL1, DL2, DL3,... As a result, the overlapping area between the first to third pixel electrodes 100, 200 and 300 and the data lines DL1, DL2, DL3.

As described above, the present invention includes a plurality of gate lines having a zigzag shape, and a plurality of data lines extending to intersect the gate lines and having a straight line shape. In addition, the pixel electrode formed in the pixel region defined by the plurality of gate lines and the data lines has a V shape or an M shape, and has a shape in which a part of the pixel electrode is removed from the region overlapping the data lines.

Accordingly, in the present invention, since the data lines have a straight line shape, the length of the data line is relatively reduced as compared with the zigzag shape, thereby reducing the transmission delay of the data signal applied to the data line. This improves the display quality of the display device.

In the detailed description of the present invention described above with reference to the preferred embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary skill in the art will be described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the scope of the present invention.

Claims (21)

A plurality of gate lines, one end of which is connected to each other by two adjacent lines; A plurality of data lines extending to intersect the gate lines and having a straight line shape; A plurality of TFTs connected to the gate lines and the data lines; And A pixel electrode connected to each of the TFTs, the center of which is bent in a direction parallel to the data lines and has a symmetrical shape and is divided into a plurality of domains, wherein the pixel electrode is parallel to the data lines. A first sub pixel electrode, a second sub pixel electrode, and a third sub pixel electrode sequentially arranged in a direction, and the first TFT connected to the first sub pixel electrode is connected to a first gate line, and the second sub pixel electrode is connected to the second sub pixel electrode. And a second TFT and a third TFT connected to a pixel electrode and the third sub pixel electrode, respectively, adjacent to the first gate line and connected to a second gate line having one end connected to each other. The display device of claim 1, wherein the gate lines have a V-shape, and the V-shape extends to have a zigzag shape. The display device of claim 1, wherein the pixel electrode has a V shape when viewed in a plane. delete The method of claim 1, wherein one of the plurality of data lines is included. The third n-th (n is a natural number) data line is positioned to be adjacent to one end of the first to third sub pixel electrodes. The third n-th data line is positioned to correspond to the center of the first to third sub pixel electrodes. And the third n-th data line is adjacent to the other end of the first to third sub pixel electrodes. The method of claim 5, wherein the first to third sub-pixel electrode A first electrode part disposed on the left side with respect to the third n-1 th data line; And Each of the second electrode parts positioned on the right side with respect to the third n-th data line; And the first and second electrode portions are linearly symmetrical with respect to the third n-th data line, and only a portion of the first and second electrode portions are connected to each other in an area overlapping the third n-th data line. delete The method of claim 5, wherein at least one of the first to third sub pixel electrodes A first electrode part disposed on the left side with respect to the third n-1 th data line; And A second electrode part positioned on the right side with respect to the third n-1 th data line; And the first and second electrode portions are linearly symmetrical with respect to the third n-th data line and separated left and right. delete The method of claim 1, wherein one of the plurality of data lines is included. The third n-1 (n is a natural number) data line is positioned to correspond to the center of the first to third sub pixel electrodes. A third n−2 th data line is positioned to correspond between the third n−1 th data line and one end of the first to third sub pixel electrodes; And a third n-th data line corresponding to the third n-th data line and the other end of the first to third sub pixel electrodes. The display device of claim 1, wherein the pixel electrode has an M shape when viewed in a plane. delete The method of claim 11, wherein the first to third sub-pixel electrode A left electrode part positioned at a left side with respect to the bent center of the pixel electrode and having a center bent in a second direction opposite to the bent direction of the center of the pixel electrode; And And a right electrode part positioned on the right side with respect to the bent center of the pixel electrode and bent in the second direction. 14. The method of claim 13, The left electrode part includes a first electrode part and a second electrode part which are symmetrical with respect to the center, And the third electrode part and the fourth electrode part which are symmetrical with respect to the center of the right electrode part. 15. The method of claim 14, wherein: among the plurality of data lines A third n−1 (n is natural number) data line is positioned between the second electrode part and the third electrode part; A third n−2 th data line is positioned between the first electrode portion and the second electrode portion; And a third nth data line is positioned between the third electrode portion and the fourth electrode portion. The display device of claim 15, wherein the first to fourth electrode parts are connected to each other in an area overlapping the data lines. delete 16. The method of claim 15, The first and second electrode portions are partially connected to each other in an area overlapping the data lines, The third and fourth electrode portions are partially connected to each other in an area overlapping the data lines, And the second and third electrode portions are separated from each other. 16. The method of claim 15, The first and second electrode portions are partially connected to each other in an area overlapping the data lines, The third and fourth electrode portions are partially connected to each other in an area overlapping the data lines, And the second and third electrode parts are integrally formed with each other. 15. The method of claim 14, wherein: among the plurality of data lines A third n-th (n is a natural number) data line is positioned between the first electrode portion and the second electrode portion, A third n−1 th data line is positioned between the third electrode portion and the fourth electrode portion; And a third n-th data line is adjacent to one end of the fourth electrode part. Forming a plurality of gate lines, one end of which is connected to each other by two adjacent lines on the substrate; Forming a plurality of data lines extending to intersect the gate lines and having a straight line shape; And Forming a pixel electrode having a center bent in a direction parallel to the data lines and having a symmetrical shape and divided into a plurality of domains; The pixel electrode may include a first sub pixel electrode, a second sub pixel electrode, and a third sub pixel electrode sequentially arranged in a direction parallel to the data lines, and the first TFT connected to the first sub pixel electrode may include a first sub pixel electrode. The second TFT and the third TFT connected to the first gate line and respectively connected to the second sub pixel electrode and the third sub pixel electrode are adjacent to the first gate line and connected to a second gate line having one end connected to each other. Method of manufacturing a display device, characterized in that.

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