KR101213029B1

KR101213029B1 - Semiconductor package

Info

Publication number: KR101213029B1
Application number: KR1020100125357A
Authority: KR
Inventors: 김동규; 김윤식
Original assignee: (주) 윈팩
Priority date: 2010-12-09
Filing date: 2010-12-09
Publication date: 2012-12-18
Also published as: KR20120064225A

Abstract

The present invention discloses a semiconductor package capable of improving the reliability of a semiconductor package in which a semiconductor chip is flip chip bonded on a substrate. The semiconductor package according to the present disclosure has one surface on which a first wiring including a bonding finger is formed and the other surface opposite to the one surface and on which a second wiring including a borland is formed, and the bonding finger and on the one surface and the other surface, respectively. A semiconductor chip having a solder resist formed to expose a ball land, a flip chip bonded on one surface of the substrate, and a bonding pad formed on a surface facing the substrate, the bonding pad facing the bonding finger, the bond finger of the substrate and the semiconductor chip An encapsulation member formed between bonding pads to fill a space between the bonding chip and the bonding pad electrically and the space between the semiconductor chip and the substrate, and to seal one surface of the flip chip bonded substrate. And a substrate, wherein the substrate has the solder resist at one surface portion facing the semiconductor chip. Has an open area is partially removed, and the bonding fingers is characterized in that disposed on the outside of the open area.

Description

Semiconductor Package {SEMICONDUCTOR PACKAGE}

The present invention relates to a semiconductor package, and more particularly, to a semiconductor package capable of improving the reliability of a semiconductor package flip-bonded with a semiconductor chip on a substrate.

The semiconductor package in the semiconductor industry generally refers to a form in which a semiconductor chip in which a microcircuit is designed is sealed with a mold resin or a ceramic so as to be protected from the external environment and mounted on an electronic device.

Recently, rather than packaging a semiconductor chip for the purpose of wrapping and protecting the semiconductor chip with the mold resin or ceramic, or simply mounting the electronic chip on the electronic device, the performance and quality of the electronic device are improved by miniaturization, thinning, and multifunctionality of the electronic device. For the purpose of packaging the semiconductor chip. Therefore, the importance of semiconductor packages is increasing.

In general, a semiconductor package includes a substrate and a semiconductor chip mounted on the substrate, and a wire bonding method or a flip chip bonding method is applied to electrically connect the semiconductor chip and the substrate.

In the case of manufacturing a semiconductor package by applying the flipping bonding method, a semiconductor chip is disposed on a substrate in the form of a face-down type via a connection member, and is connected to the semiconductor chip by the connection member. The substrates are electrically connected to each other. An underfill process is performed to fill the space between the semiconductor chip and the substrate.

Specifically, the underfill process is performed by a flow method of injecting a liquid filling material around the semiconductor chip after flip chip bonding a semiconductor chip on the substrate, wherein the filling material is a semiconductor through the underfill process. The semiconductor chip is protected from external impact by filling in the space between the chip and the substrate.

However, in the above-described prior art, the filling material does not flow smoothly into the space between the semiconductor chip and the substrate during the underfill process, which causes a problem that the space between the semiconductor chip and the substrate is not properly filled. That is, in the above-described prior art, it is difficult for the filling material to completely fill the space between the semiconductor chip and the substrate because the space in which the filling material is injected during the underfilling process is not sufficiently wide, whereby the semiconductor chip is protected from external impact. Inadequate protection can reduce the reliability of semiconductor packages.

In particular, as the space between the semiconductor chip and the substrate becomes narrower in accordance with the trend of miniaturization of the semiconductor package, it becomes more difficult for the filling material to flow properly. As a result, the space between the semiconductor chip and the substrate is stabilized. There is a need for a new technology for filling with.

The present invention provides a semiconductor package capable of improving the reliability of a semiconductor package flip-bonded with a semiconductor chip on a substrate.

The semiconductor package according to the embodiment of the present invention has one surface on which a first wiring including a bonding finger is formed and the other surface opposite to the one surface and a second wiring including a ball land is formed, and the bonding on the one surface and the other surface, respectively. A substrate on which a solder resist is formed to expose a finger and a ball land, a semiconductor chip having flip chip bonding on one surface of the substrate, and a bonding pad facing the bonding finger on a surface facing the substrate, a bond finger of the substrate, and the semiconductor A space between the semiconductor chip and the substrate and a connection member electrically connecting the bonding finger and the bonding pad to be formed between the bonding pads of the chip, and the semiconductor chip seals one surface of the flip chip bonded substrate. And an encapsulation member, wherein the substrate has the solder resist at one surface portion facing the semiconductor chip. The agent has a partially removed with an open region, and the bonding fingers is characterized in that disposed on the outside of the open area.

The encapsulation member includes an epoxy molding compound (EMC).

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The semiconductor package further includes an external connection terminal formed on a ball land of the other surface of the substrate.

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The bond finger and the bonding pad may be formed of at least one edge-pad type on the substrate and the semiconductor chip, respectively.

The bond finger and the bonding pad may be formed of at least one center-pad type on the substrate and the semiconductor chip, respectively.

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The connection member includes a bump or a solder ball.

The open area of the substrate has a rectangular shape or a rectangular picture frame shape when viewed on a plane.

The substrate has a window formed to penetrate the substrate in the open area.

The open area of the substrate, when viewed on a plane, consists of at least two or more having a rectangular shape.

The substrate has windows formed to penetrate the substrate in each of the open regions.

The open area of the substrate has a width narrower than that of the semiconductor chip.

The open area of the substrate has a length longer than the length of the semiconductor chip.

The present invention enables the implantation of EMC through the open region by flip chip bonding a semiconductor chip onto the open region of the substrate having an open region in which solder resist is partially removed, and thus the present invention provides an underfill process. Without performing the EMC, the EMC may fill the space between the semiconductor chip and the substrate and seal one surface of the flip chip bonded substrate.

Therefore, the present invention provides the space between the semiconductor chip and the substrate is completely filled by the EMC. Since the semiconductor chip can be effectively protected from an external impact, the reliability of the semiconductor package in which the semiconductor chip is flip chip bonded on the substrate can be improved.

1A and 1B are a plan view and a cross-sectional view for describing a semiconductor package according to an embodiment of the present invention.
2A and 2B are a plan view and a cross-sectional view for illustrating a semiconductor package according to this embodiment of the present invention.
3A and 3B are plan views and cross-sectional views illustrating a semiconductor package according to an embodiment of the present invention.
4A and 4B are a plan view and a cross-sectional view for describing a semiconductor package according to four embodiments of the present disclosure.
5A and 5B are plan and cross-sectional views illustrating a semiconductor package according to an exemplary embodiment of the present invention.
6A and 6B are plan and cross-sectional views illustrating a semiconductor package according to six embodiments of the present disclosure.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1A and 1B are a plan view and a cross-sectional view for describing a semiconductor package according to an embodiment of the present invention.

As illustrated, the semiconductor chip 200 is flip chip bonded on the substrate 100 having one surface and the other surface opposite thereto, with the connection member 150 interposed therebetween.

A first wiring (not shown) is formed on one surface of the substrate 100, for example, a bond finger 112, and a second wiring (not shown) is formed on the other surface of the substrate 100. For example, a second wiring including the borland 114 is formed. The solder resists 110A and 110B are exposed on one surface and the other surface of the substrate 100 to expose at least a portion of the first wiring including the bond finger 112 and the second wiring including the ball land 114, respectively. ) Is formed. Specifically, the solder resist 110A is formed on one surface of the substrate 100 to expose the bond finger 112, and the solder resist 110B is formed on the other surface of the substrate so that the ball lands 114 are exposed. It is.

The semiconductor chip 200 flip chip bonded on one surface of the substrate 100 includes a bonding pad 212 corresponding to the bond finger 112 on a surface facing the surface of the substrate 100. The bond fingers 112 and the bonding pads 212 may be formed of at least one edge-pad type on the substrate 100 and the semiconductor chip 200, respectively.

In addition, a connection member 150 is formed between the bond finger 112 of the substrate 100 and the bonding pad 212 of the semiconductor chip 200, and the substrate 100 is formed by the connection member 150. ) And the semiconductor chip 200 are electrically connected to each other. The connection member 150 includes, for example, bumps or solder balls.

Here, the substrate 100 has an open area (O / A) in which the solder resist 110A is partially removed from one surface portion facing the semiconductor chip 200. The open area O / A of the substrate 100 has a rectangular shape when viewed on a plane. In addition, in the open area O / A of the substrate 100, the bond finger 112 of the substrate 100 arranged in an edge-pad type and the bonding pad 212 of the semiconductor chip 200 may be connected to the connection member 150. A width narrower than the width of the semiconductor chip 200 so that the semiconductor chip 200 may be contacted with each other under the interposition of the semiconductor chip 200, and the filling material may be injected while the semiconductor chip 200 is flip chip bonded. It has a length longer than the length.

Therefore, in the present invention, a filling material is injected through the open area O / A of the substrate 100 to fill the space between the semiconductor chip 200 and the substrate 100 and the semiconductor chip 200. The encapsulation member 250 is formed to seal one surface of the flip chip bonded substrate 100. The encapsulation member 250 includes, for example, an epoxy molding compound (EMC). The external connection terminal 260 is formed on the ball land 114 on the other surface of the substrate 100.

As described above, in the semiconductor package according to the exemplary embodiment of the present invention, the flip chip bonding of the semiconductor chip 200 on the substrate 100 having the open area O / A in which the solder resist 110A is partially removed. As a result, a filling material, that is, an EMC, may be injected through the open area O / A while the semiconductor chip 200 is flip chip bonded. Therefore, the present invention can protect the semiconductor chip 200 from an external impact even without an underfill process.

In detail, in the case of the conventional semiconductor package, an underfill process has to be additionally performed to fill the space between the semiconductor chip and the substrate after flip chip bonding the semiconductor chip, and the space between the semiconductor chip and the substrate is not wide enough. The underfill process caused a problem that the space between the semiconductor chip and the substrate was not properly filled. However, in the case of the semiconductor package of the present invention described above, an open area O / A is formed by removing a portion of the solder resist 110A on one surface of the substrate 100, and a semiconductor chip (eg, on the open area O / A) is formed. By flip chip bonding 200, a space equal to the thickness of the removed solder resist 110A, for example, about 10 to 40 μm, may be secured under the semiconductor chip 200. It is possible to properly fill the space between the semiconductor chip 200 and the substrate 100 through the region O / A.

Therefore, in one embodiment of the present invention, the semiconductor chip 200 can be properly protected from an external impact even without an underfill process, so that the process can be simplified and the reliability of the semiconductor package can be effectively improved.

Meanwhile, in the above-described embodiment of the present invention, an open area O / A is provided at a portion of the substrate 100 below the semiconductor chip 200, and the semiconductor chip 200 is provided through the open area O / A. Although the case where the space between the substrate 100 and the substrate 100 is filled and described, the embodiment of the present invention is not limited thereto, and as an embodiment of the present invention, a window through which the substrate penetrates the substrate in an open area is provided. It is also possible to have a.

2A and 2B are a plan view and a cross-sectional view for illustrating a semiconductor package according to this embodiment of the present invention.

As illustrated, the semiconductor chip 200 is flip chip bonded on the substrate 100 having one surface and the other surface opposite thereto, with the connection member 150 interposed therebetween. The substrate 100 has an open area (O / A) in which the solder resist 110A is partially removed from one surface portion facing the semiconductor chip 200. The open area O / A of the substrate 100 has a rectangular shape when viewed on a plane. The open area O / A of the substrate 100 has a width narrower than the width of the semiconductor chip 200 and a length longer than the length of the semiconductor chip 200.

Here, the substrate 100 includes a window W formed to penetrate the substrate 100 in the open area O / A. The window W is formed to penetrate through the solder resists 110A and 110B and the substrate 100 on one surface and the other surface of the substrate 100, and has a width narrower than that of the open area O / A.

Therefore, in the present invention, a filling material is injected through the open area O / A of the substrate 100 to fill the space between the semiconductor chip 200 and the substrate 100 and the semiconductor chip 200. The encapsulation member 250 is formed to seal one surface of the flip chip bonded substrate 100. The encapsulation member 250 includes, for example, EMC.

In addition, in the present invention, the air is smoothly discharged through the window (W) provided in the open (O / A) area, it is possible to suppress the generation of residual pores inside the semiconductor package when forming the encapsulation member (250). have.

As described above, in the semiconductor package according to this embodiment of the present invention, the flip chip bonding of the semiconductor chip 200 on the substrate 100 having the open area (O / A) in which the solder resist 110A is partially removed. As a result, a filling material, that is, an EMC, may be injected through the open area O / A while the semiconductor chip 200 is flip chip bonded. Therefore, the present invention can properly protect the semiconductor chip 200 from an external impact even without an underfill process, thereby simplifying the process and at the same time effectively improving the reliability of the semiconductor package.

In addition, in this embodiment of the present invention, by providing a window penetrating the substrate in the open area, it is possible to smoothly discharge the air through the window (W), and thus, the present invention provides the encapsulation member 250. It is possible to suppress the generation of residual pores in the semiconductor package during formation.

Meanwhile, in the above-described embodiments of the present invention, a rectangular open area (O / A) is provided on a portion of the substrate 100 under the semiconductor chip 200 and is formed through the rectangular open area (O / A). Although the case where the space between the semiconductor chip 200 and the substrate 100 is filled and described, the embodiment of the present invention is not limited thereto, and as an embodiment of the present invention, the open area may have a rectangular shape. It is also possible to have a picture frame shape.

3A and 3B are plan views and cross-sectional views illustrating a semiconductor package according to an embodiment of the present invention.

As shown, the open area O / A of the substrate 100 has a rectangular picture frame shape when viewed on a plane. The open area O / A of the substrate 100 has a width narrower than the width of the semiconductor chip 200 and a length longer than the length of the semiconductor chip 200.

As described above, in the semiconductor package according to the third embodiment of the present invention, the flip chip bonding of the semiconductor chip 200 on the substrate 100 having the open area O / A in which the solder resist 110A is partially removed. As a result, a filling material, that is, an EMC, may be injected through the open area O / A while the semiconductor chip 200 is flip chip bonded. Therefore, the present invention can properly protect the semiconductor chip 200 from an external impact even without an underfill process, thereby simplifying the process and at the same time effectively improving the reliability of the semiconductor package.

In addition, in the third embodiment of the present invention, since the open (O / A) region has a rectangular picture frame shape, a portion of the solder resist 110A is not removed from the center portion of the open region (O / A). Therefore, the present invention prevents the semiconductor chip 200 from being struck or bent in the open area O / A by supporting the semiconductor chip 200 where the solder resist 110A remains. Can be.

In particular, according to the third embodiment of the present invention, the semiconductor chip 200 may be formed of a substrate (not shown) with an epoxy material (not shown) applied to support the semiconductor chip 200 in a portion where the solder resist 110A remains. As the flip chip is bonded onto the substrate 100, the phenomenon that the semiconductor chip 200 is struck or bent on the open area O / A may be more effectively prevented.

Meanwhile, in the above-described third embodiment of the present invention, the open area O / A has a rectangular picture frame shape, and thus the semiconductor chip 200 is prevented from falling or bending. The embodiment of the present invention is not limited thereto, and as the fourth embodiment of the present invention, the same effect may be obtained when the open area is formed of at least two having a rectangular shape.

4A and 4B are a plan view and a cross-sectional view for describing a semiconductor package according to four embodiments of the present disclosure.

As shown, the open area (O / A) of the substrate 100, when viewed in plan view, consists of at least two or more having a rectangular shape, and thus, solder resist between the open areas (O / A). A portion of 110A remains unremoved. Accordingly, in the present invention, the portion where the solder resist 110A remains may support the semiconductor chip 200, thereby preventing the semiconductor chip 200 from falling or bending over the open area O / A.

In addition, even in an exemplary embodiment of the present invention, the semiconductor chip 200 may be formed by applying a substrate (not shown) to an epoxy material (not shown) to support the semiconductor chip 200 in the remaining portion of the solder resist 110A. As the flip chip is bonded onto the substrate 100, the phenomenon that the semiconductor chip 200 is struck or bent on the open area O / A may be more effectively prevented.

Although not shown, even when the open area has a rectangular frame shape or at least two or more rectangular shapes, a window penetrating the substrate may be provided in the open area. It is possible to prevent the phenomenon that the semiconductor chip is struck or bent, and to suppress the generation of residual pores in the semiconductor package.

Meanwhile, in the above-described embodiments of the present invention, a case in which the bond fingers of the substrate and the bonding pads of the semiconductor chip are arranged in an edge-pad type is described and described, but embodiments of the present invention are not limited thereto. As a fifth embodiment of the invention, it is also possible for the bond fingers of the substrate and the bonding pads of the semiconductor chip to be arranged in a center-pad type.

5A and 5B are plan and cross-sectional views illustrating a semiconductor package according to an exemplary embodiment of the present invention.

The semiconductor chip 200 flip chip bonded on one surface of the substrate 100 includes a bonding pad 212 corresponding to the bond finger 112 on a surface facing the surface of the substrate 100. The bond fingers 112 and the bonding pads 212 may be formed of at least one center-pad type on the substrate 100 and the semiconductor chip 200, respectively.

Here, the substrate 100 has an open area (O / A) in which the solder resist 110A is partially removed from one surface portion facing the semiconductor chip 200. The open area O / A of the substrate 100 may include at least two or more rectangular shapes when viewed in plan view. In addition, the open area O / A of the substrate 100 has a width narrower than that of the semiconductor chip 200 and has a length longer than that of the semiconductor chip 200.

As described above, in the semiconductor package according to the fifth embodiment of the present invention, the flip chip bonding of the semiconductor chip 200 on the substrate 100 having the open area O / A in which the solder resist 110A is partially removed. As a result, a filling material, that is, an EMC, may be injected through the open area O / A while the semiconductor chip 200 is flip chip bonded. Therefore, the present invention can properly protect the semiconductor chip 200 from an external impact even without an underfill process, thereby simplifying the process and at the same time effectively improving the reliability of the semiconductor package.

In addition, in the fifth embodiment of the present invention, the semiconductor in the state where an epoxy material (not shown) for supporting the semiconductor chip 200 is coated on the solder resist 110A on both sides of the open area O / A. Since the chip 200 is flip chip bonded onto the substrate 100, the semiconductor chip 200 may be prevented from being inclined or bent to both sides of the connection member 150.

Meanwhile, in the above-described exemplary embodiment of the present invention, an open area O / A is provided at a portion of the substrate 100 under the semiconductor chip 200, and the semiconductor chip 200 is provided through the open area O / A. Although the space between the substrate 100 and the substrate 100 is illustrated and described, the embodiment of the present invention is not limited thereto, and as a sixth embodiment of the present invention, a window in which the substrate penetrates the substrate in an open area is provided. It is also possible to have a.

6A and 6B are plan and cross-sectional views illustrating a semiconductor package according to six embodiments of the present disclosure.

As illustrated, the semiconductor chip 200 is flip chip bonded on the substrate 100 having one surface and the other surface opposite thereto, with the connection member 150 interposed therebetween. The substrate 100 has an open area (O / A) in which the solder resist 110A is partially removed from one surface portion facing the semiconductor chip 200. The open area O / A of the substrate 100 may include at least two or more rectangular shapes when viewed in plan view. The open area O / A of the substrate 100 has a width narrower than the width of the semiconductor chip 200 and a length longer than the length of the semiconductor chip 200.

Here, the substrate 100 includes windows W formed to penetrate the substrate 100 in each of the open regions O / A. The window W is formed to penetrate through the solder resists 110A and 110B and the substrate 100 on one surface and the other surface of the substrate 100, and has a width narrower than that of the open area O / A.

In addition, in the present invention, the air is smoothly discharged through the windows (W) provided in each of the open (O / A) areas, and it is possible to suppress the generation of residual pores in the semiconductor package when the encapsulation member 250 is formed. Can be.

In addition, in the sixth embodiment of the present invention, the semiconductor in a state in which an epoxy material (not shown) for supporting the semiconductor chip 200 is coated on portions of the solder resist 110A on both sides of the open area O / A. Since the chip 200 is flip chip bonded onto the substrate 100, the semiconductor chip 200 may be prevented from being inclined or bent to both sides of the connection member 150.

On the other hand, although not shown, the open region may have a shape of a photo frame in which a solder resist portion is left in a portion where a bond finger and a bonding pad arranged in a center-pad type are disposed in plan view. It is also possible to have a window penetrating the substrate in the open area.

In other words, in the semiconductor package according to the embodiment of the present invention, the open area provided in the substrate is not limited to its shape and number, and may be appropriately determined according to other environments such as the bond finger of the substrate and the type of bonding pads of the semiconductor chip. It is changeable, and the window arrange | positioned in the said open area can also be changed suitably regardless of the shape and number.

Hereinbefore, the present invention has been illustrated and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications and variations can be made.

100: substrate 110A, 110B: solder resist
112: bonding pad 114: Borland
O / A: Open Area W: Windows
150 connection member 200 semiconductor chip
212: bonding pad 250: sealing member
260: external connection terminal

Claims

A substrate having one surface on which a first wiring including a bonding finger is formed and another surface facing the one surface and on which a second wiring including a ball land is formed, and a solder resist formed on the surface and the other surface to expose the bonding finger and the ball land, respectively ;
A semiconductor chip flip-bonded on one surface of the substrate and formed with a bonding pad facing the bonding finger on a surface facing the substrate;
A connection member formed between the bond finger of the substrate and the bonding pad of the semiconductor chip to electrically connect the bonding finger and the bonding pad; and
And a sealing member filling the space between the semiconductor chip and the substrate and sealing the one surface of the flip chip bonded substrate.
And the substrate has an open area in which the solder resist is partially removed from one surface portion facing the semiconductor chip, and the bonding finger is disposed outside the open area.

The method of claim 1,
The encapsulation member is a semiconductor package comprising an epoxy molding compound (EMC).

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The method of claim 1,
An external connection terminal formed on a ball land of the other surface of the substrate;
The semiconductor package further comprises.

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The method of claim 1,
The at least one bond finger and the at least one bonding pad may be formed on at least one edge-pad type on the substrate and the semiconductor chip, respectively.

The method of claim 1,
The at least one bond finger and the at least one bonding pad may be formed of at least one center-pad type on the substrate and the semiconductor chip, respectively.

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The method of claim 1,
The connecting member is a semiconductor package, characterized in that it comprises a bump or solder ball.

The method of claim 1,
The open area of the substrate, when viewed on a plane, a semiconductor package, characterized in that it has a rectangular shape or a rectangular picture frame shape.

The method of claim 9,
And the substrate has a window formed through the substrate in the open area.

The method of claim 1,
The open area of the substrate, when viewed in plan view, the semiconductor package, characterized in that made of at least two or more.

13. The method of claim 12,
And the substrate has a window formed in each of the open regions so as to pass through the substrate.

The method of claim 1,
And the open area of the substrate has a width narrower than that of the semiconductor chip.

The method of claim 1,
And the open area of the substrate has a length longer than that of the semiconductor chip.