KR101212746B1 - Phase Change Memory Device Capable of Reducing Stand-By Current - Google Patents

Abstract

A phase change memory device capable of reducing standby current. The phase change memory device of the present invention includes a cell array including a plurality of memory cells, and a write driver providing a set or reset pulse to selected memory cells of the cell array. And control the selection of the memory cell and the write driver, and upon rising of the write voltage provided from the write driver for write operation, the cell until the write voltage reaches a constant voltage level for the write operation. And a controller configured to hold a supply of signals provided to the array.

Description

Phase Change Memory Device Capable of Reducing Stand-By Current

The present invention relates to a nonvolatile memory device, and more particularly, to a phase change memory device capable of reducing leakage current.

Currently, research on nonvolatile memory devices using resistors has been proposed, and nonvolatile memory devices using such resistors include phase change memories, resistance memories, magnetic memories, and the like. In particular, the phase change memory device has a random access (random access) can achieve a fast operating speed, such as DRAM, and the memory can be performed simply by the crystallization characteristics of the phase change material such as chalcogenide alloy Have

The phase change memory device includes a cell array like a DRAM, and each unit cell constituting the cell array may include a 1-switching element and a 1-resistor.

Currently, MOSFETs or vertical diodes are used as switching elements, and chalcogenide alloys may be used as resistors. Here, the resistor is crystallized by the current by the voltage applied from the drain of the MOSFET. Therefore, high voltage (Vpp) is generally applied to the drain of the MOSFET used as the switching element for smooth phase change.

However, when a high voltage is applied to the drain of the MOSFET used as the switching element for the phase change of the resistor, that is, for the data recording of the memory cell as described above, it is not selected by the gate induced drain leakage (GIDL) phenomenon. There is a problem that a standby current is generated in a non-state state (that is, a state in which the write driver is not driven).

Moreover, the high voltage causes GIDL even in a standby state in which the write driver is not driven.

Accordingly, the present invention provides a phase change memory device capable of reducing standby current.

The phase change memory device according to the present embodiment includes a cell array including a plurality of memory cells, a write driver providing a set or reset pulse to a selected memory cell of the cell array, and a selection of the memory cell and the write driver. And to hold the supply of signals provided to the cell array until the write voltage reaches a constant voltage level for the write operation, upon rising of the write voltage provided from the write driver for write operation. Contains a controller.

In addition, a phase change memory device according to another exemplary embodiment of the present invention may include a cell array including a plurality of memory cells, a write driver providing a set or reset pulse to a selected memory cell of the cell array, and selection of the memory cell. And supplying a clock that controls the write driver and generates a signal for activating the cell array until the write voltage reaches a predetermined voltage level when the write voltage rises from the write driver for a write operation. It includes a controller configured to include a clock holding unit for holding a.

According to the present invention, a relatively low high voltage (voltage below an operating level) is provided through a bit line in a cell array region during a standby period and a similar nonoperation period of a phase change memory device. Accordingly, the drain voltage of the switching transistor connected to the bit line is lowered, thereby lowering the GIDL of the switching transistor. Accordingly, the standby current can be reduced in the standby period and the non-operation period, thereby improving the current characteristics of the phase change memory device.

1 is a block diagram illustrating a schematic configuration of a phase change memory device according to an embodiment of the present invention;
2 is a block diagram showing a configuration of a controller of a phase change memory device according to an embodiment of the present invention;
3 is a circuit diagram showing a configuration of a clock holding unit in a controller according to an embodiment of the present invention;
4 is a graph showing an output pulse of a light driver according to an embodiment of the present invention;
5 is a schematic circuit diagram illustrating a cell array of a phase change memory device according to an embodiment of the present invention; and
6 is a timing diagram illustrating signal pulses over time of a phase change memory device according to an exemplary embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Referring to FIG. 1, the phase change memory device 100 includes a controller 200, a pumping circuit unit 280, a write driver 300, and a cell array 350.

As shown in FIG. 2, the controller 200 includes a control counter 210, a command controller 220, an address controller 230, a light controller 240, a clock holding unit 250, and a clock oscillator 260. Can be configured.

The control counter 210 receives the external transfer data and generates a command decoding command signal C_St and an address decoding command signal A_St. Here, the command decoding command signal C_St and the address decoding signal A_St may be signals obtained by latching a signal input from a command pad (not shown) and an address pad (not shown). In addition, the command decoding command signal C_St may be, for example, a command for determining a set or reset of the phase change memory device. In addition, the control counter 210 may receive the clock signal CLK from the clock oscillator 260 and generate a first activation signal ENP for activating the light controller 240.

The command controller 220 receives a command decoding command signal C_St from the control counter 210, decodes a command input from a command pad (not shown), and generates an erase signal ERASE. do. The erase signal ERASE is a signal provided to the pumping circuit unit 280 and may be a pumping enable signal corresponding to a set or reset state according to a command type.

The address controller 230 receives the address decoding command signal A_St from the control counter 210, decodes the addresses input to the address pad (not shown), and activates the second cell array 350 to activate the cell array 350. Generate an activation signal (PGMPTEN).

The light controller 240 receives the first activation signal ENP from the control counter 210 and generates a signal WR_CON for controlling the light driver 300.

The clock holding unit 250 receives a command decoding command C_St and a high voltage detection signal VPP2detect provided from the control counter 210 and generates a clock stop signal CLKPAUSE. As illustrated in FIG. 3, the clock holding unit 250 may include a pair of NAND gates NAND1 and NAND2 connected in a latch form. The first NAND gate NAND1 is configured to receive a command decoding command C_St and an output signal of the second NAND gate NAND2, and the second NAND gate NAND2 is a high voltage detection signal VPP2detect and the first NAND gate NAND1. The output signal of the NAND gate NAND1 may be input. In this case, the clock stop signal CLKPAUSE is a signal obtained by inverting the output signal of the first NAND gate NAND1 by the inverter IN. That is, the clock holding unit 250 generates a clock stop signal CLKPAUSE that is enabled high until the high voltage detection signal Vpp is enabled while the command decoding command Cst is enabled. It is composed.

The clock oscillator 260 is configured to generate a clock pulse in response to the clock stop signal CLKPAUSE. That is, the clock oscillator 260 is configured not to generate a clock pulse while the clock stop signal CLKPAUSE is enabled, and generate a clock pulse when the clock stop signal CLKPAUSE is disabled.

Referring back to FIG. 1, the pumping circuit unit 280 receives an erase signal ERASE, which is an enable signal, from the command controller 220 and generates a pumping voltage according to a command type. In general, when the pumping circuit unit 280 of the phase change memory device supplies the first high voltage VPP1 to the write driver 300 and needs to write reset data, the second high voltage (VPP1) higher than the first high voltage VPP1 may be used. VPP2) is provided to the write driver 300. At this time, the pumping circuit unit 280 is designed to output a high voltage detection signal VPP2detect signal when the output voltage reaches the second high voltage VPP2 level when the second high voltage VPP2 is to be output. In addition, although a high voltage is continuously applied in the related art, the present embodiment may be configured such that a relatively high second high voltage VPP2 is provided only when necessary.

The write driver 300 is illustrated in FIG. 4 using the first or second high voltages VPP1 and VPP2 provided by the pumping circuit unit 280 in response to the write driver control signal WR_con provided from the controller 200. And output a set or reset pulse as shown. The write driver 300 forms a pulse having a gentle falling edge such that the phase change element is gradually cooled at a low temperature during a set operation, and has a sharp falling edge such that the phase change element is rapidly cooled at a high temperature during a reset operation. Form a pulse. Accordingly, the write driver 300 may require the first high voltage VPP1 to form the set pulse and the second high voltage VPP2 to form the reset pulse.

As illustrated in FIG. 5, the cell array 350 includes a plurality of word lines WL0-WLn and a plurality of bit lines BL0-BLm that cross each other. A plurality of phase change memory regions are defined by the word lines WL0-WLn and the bit lines BL0-BLm, and switching elements T connected to the corresponding word lines WL0-WLn in each phase change memory region. ) And a memory cell mc composed of a phase change element R receiving data from the bit lines BL0-BLm by the switching element T, respectively. The cell array 350 receives a set or reset pulse from the write driver 300 and receives a first activation signal PCMPTEN for activating the memory cell mc of the selected address from the address controller 230.

An operation of the phase change memory device having the above configuration will be described with reference to FIG. 6 as follows.

As shown in FIG. 6, external transfer data having command information, command address information, and cell data information is input to the controller 200, and the clock oscillator 260 generates a clock pulse CLK with a clock.

In response to the falling edge of the clock pulse CLK, the control counter 210 generates a control decoding command C_St. The command controller 220 receives the control decoding command C_St and generates an erase signal ERASE in response thereto.

The pumping circuit unit 280 outputs a relatively low first high voltage VPP1 and is leveled up to a second high voltage VPP2 in response to the erase signal ERASE.

At this time, the clock holding unit 250 receives the control decoding command C_St and enables the clock stop signal CLKPAUSE. The clock stop signal CLKPAUSE is provided to the clock oscillator 260 so as not to generate the clock CLK during the period in which the clock stop signal CLKPAUSE is enabled.

The pumping circuit section 280 then generates a high voltage detection signal VPP2 detect that is enabled high when its output level reaches the second high voltage VPP2. When the high voltage detection signal VPP2detect is enabled high, the output signal of the clock holding unit 250 is disabled, and the clock oscillator 260 generates a clock pulse again, and accordingly, the address decoding command A_ST ), The first activation signal ENP and the second activation signal PGMPTEN are enabled.

In the phase change memory device, in the standby state, a relatively low first high voltage VPP1 is provided to the cell array region 350, and a relatively high second high voltage VPP2 is applied to the cell array region 350 when a command is input. Is provided. Then, in the standby state, a relatively low first high voltage is provided to the bit line, that is, the drain of the switching transistor, thereby reducing the potential difference between the drain and the source of the switching transistor and further preventing the cell array activation.

According to the present invention, a relatively low high voltage (voltage below an operating level) is provided through a bit line in a cell array region during a standby period and a similar nonoperation period of a phase change memory device. Accordingly, the drain voltage of the switching transistor connected to the bit line is lowered, thereby lowering the GIDL of the switching transistor. Accordingly, the standby current can be reduced in the standby period and the non-operation period, thereby improving the current characteristics of the phase change memory device.

200: controller 210: control counter
220: command controller 230: address controller
240: light controller 250: clock holding unit
260: clock oscillator 280: pumping circuit
300: light driver 350: cell array

Claims (10)

A cell array including a plurality of memory cells;
A write driver providing a set or reset pulse to selected memory cells of the cell array; And
Controlling the selection of the memory cell and the write driver, and upon rising of the write voltage provided from the write driver for a write operation, to the cell array until the write voltage reaches a predetermined voltage level for the write operation. A phase change memory device comprising a controller configured to hold a supply of provided signals. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1,
The controller includes:
And a clock holding unit generating a signal for stopping a clock generation for generating the signals provided to the cell array until the write voltage reaches the predetermined voltage level. Claim 3 has been abandoned due to the setting registration fee. The method of claim 2,
The clock holding unit,
And generate a clock stop signal that is enabled in response to a command decoding signal and is disabled in response to a high voltage sense signal generated when the voltage level in the write operation is reached. Claim 4 has been abandoned due to the setting registration fee. The method of claim 3, wherein
The clock holding unit,
A first NAND gate receiving the command decoding signal;
A second NAND gate receiving the high voltage detection signal; And
An inverter connected to an output terminal of the first NAND gate,
And an output of the first NAND gate is input to the second NAND gate, and an output of the second NAND gate is input to the first NAND gate. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1,
And a pumping circuit unit configured to provide a first high voltage or a second high voltage greater than the first high voltage to the write driver. Claim 6 has been abandoned due to the setting registration fee. The method of claim 5, wherein
The pumping circuit unit provides the first or second high voltage to the write driver according to a state control signal provided from the controller.
And outputting a high voltage sensing signal when the rising of the second high voltage from the first high voltage to the second high voltage is completed. Claim 7 has been abandoned due to the setting registration fee. The method of claim 1,
The controller includes:
A command controller for generating a state control signal from external transfer data;
An address controller for designating a location of the memory cell to be selected from the external transfer data; And
And a write driver for generating a control signal for controlling the write driver from a clock. A cell array including a plurality of memory cells;
A write driver providing a set or reset pulse to selected memory cells of the cell array; And
Controlling the selection of the memory cell and the write driver, and upon raising the write voltage provided from the write driver for a write operation, a signal for activating the cell array until the write voltage reaches a predetermined voltage level. And a controller configured to include a clock holding unit for holding a supply of a generated clock. Claim 9 has been abandoned due to the setting registration fee. The method of claim 8,
The clock holding unit,
And generate a clock stop signal that is enabled in response to a command decoding signal and is disabled in response to a high voltage sense signal generated when the voltage level in the write operation is reached. Claim 10 has been abandoned due to the setting registration fee. The method of claim 9,
The clock holding unit
First and second NAND gates connected in a latch form, and
An inverter connected to an output terminal of the first NAND gate,
The command signal and the output signal of the second NAND gate are applied to the first NAND gate,
The second NAND gate is a phase change memory device to which the high voltage detection signal and the output signal of the first NAND gate is applied.

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