KR101196014B1 - Hybrid duty-cycle corrector circuit using successive approximation register - Google Patents

Abstract

PURPOSE: A hybrid duty-cycle corrector circuit using successive approximation register is provided to increase a margin in feedback timing by decreasing driving clock speed of a digital feedback block. CONSTITUTION: An analog feedback loop(400) senses a duty cycle error of an output clock signal and stores duty cycle control information for removing errors. The analog feedback loop generates an analog differential control voltage according to the duty cycle control information. A digital feedback block(500) converts the duty cycle control information into a digital bit using a successive approximation register. The digital feedback block outputs a digital differential control voltage. A duty amplifier(100) corrects an input duty cycle by receiving the analog differential control voltage and the digital differential control voltage. [Reference numerals] (100) Duty amplifier; (200) Level converter; (300) Clock tree part; (400) Charge pump; (510) Comparator

Description

Hybrid duty-cycle corrector circuit using successive approximation register

The present invention relates to a duty cycle correction circuit, and more particularly, by applying a continuous approximation register (SAR) to increase the accuracy of the output duty cycle due to improved feedback timing margin, effectively reducing the locking time of the system It relates to a hybrid duty cycle correction circuit that can be made.

For high-speed digital systems such as memory, microprocessors, and communication chips, delay-locked loops that use both the rising and falling edges of the clock with the chip-to-chip I / O interface to improve power consumption and data transfer rates. Use DLL: Delay Locked Loop or PLL: Phase Locked Loop. In these systems, the 50% duty cycle of the clock is essential for improving timing margins.

However, the clock duty-cycle of the DLL or PLL output can be aggravated by a number of factors, such as input signal asymmetry, device mismatch, processor variation, and crosstalk noise. To ensure that the divided clock signal has 50% duty cycle, the delay locked loop (or phase locked loop) generally includes an analog or digital type duty cycle correction circuit.

The duty cycle correction circuit is generally divided into two types, an analog duty cycle correction circuit and a digital duty cycle correction circuit, depending on the type of feedback loop that controls the duty cycle of the output clock.

The analog duty cycle correction circuit uses a scheme of storing duty cycle control information in a capacitor of a feedback loop. In general, analog feedback loops have a simple structure, accurate duty cycle correction capability, and a wide duty cycle correction range and operating frequency range.

However, the analog duty cycle correction circuit cannot maintain the duty cycle control information stored in the capacitor due to the leakage current without wasting power, and the analog duty cycle correction circuit is not able to switch to the active mode quickly. It cannot be used in the system applied.

On the other hand, the digital duty cycle correction circuit uses a method of storing the duty cycle control information in digital bits through a finite state machine in the feedback loop, thereby enabling quick wakeup from a low power standby mode. However, digital duty cycle correction circuits generally have the disadvantage of having a narrow duty cycle correction range, a limited operating frequency range, high power consumption and a large area.

The hybrid duty cycle correction circuit, which is a combination of the analog feedback loop and the digital feedback loop, maintains the wide duty cycle correction range, operating frequency range, and accurate duty cycle correction capability of the analog duty cycle correction circuit. It is developed to support low power standby mode.

1 is a schematic configuration diagram of a hybrid duty cycle correction circuit according to the prior art. Referring to FIG. 1, a hybrid duty cycle correction circuit according to the related art, the hybrid duty cycle correction circuit 60 includes a duty amplifier 10, a level converter 20, a clock tree unit 30, and an analog feedback loop 40. ) And digital feedback block 50.

The duty amplifier 10 receives the input clock signal IN_CLK, according to the control signals Vctrl and Vctrlb output from the charge pump of the analog feedback loop 40 and the control signals VDctrl and VDctrlb output from the digital feedback block 50. The duty cycle of IN_CLKb) is adjusted and output. The level converter 20 is installed at the rear end of the duty amplifier 10 and converts the small swing signal output from the duty amplifier 10 into a full swing output. The clock tree unit 30 receives the output signal of the level converter 20 and increases the current driving capability to output the output clock signals OUT_CLK and OUT_CLKb.

The hybrid duty cycle correction circuit according to the prior art may have a wide operating frequency range and a duty cycle correction range, like the analog duty cycle correction circuit. In addition, since the duty cycle control information is stored in the digital bit using the finite state machine 52, it is suitable for fast wake-up operation from the low power standby mode to the active mode.

However, the hybrid duty cycle correction circuit according to the prior art is composed of a dual feedback loop composed of an analog feedback loop 40 and a digital feedback block 50, so that the two feedback loops work together to achieve accurate duty cycle correction capability. It is essential to secure stability due to wide timing margin.

The driving clock speed of the digital feedback block is a key factor in ensuring stability due to timing margins. However, since the driving clock speed of the digital feedback block has a trade-off relationship with the locking time, in order to secure the stability of the hybrid duty cycle correction circuit and improve the duty cycle correction accuracy, it is necessary to bear the locking time, which is a hybrid duty. This results in limiting the performance and usefulness of the cycle correction circuit.

SUMMARY OF THE INVENTION The present invention has been made to overcome the above-mentioned conventional problems. The problem to be solved by the present invention is to use a continuous approximation register as a finite state machine of a digital feedback block to improve timing margin in the interoperation process of a dual feedback loop, The purpose is to provide a hybrid duty cycle correction circuit that enables accurate duty cycle correction capability and fast locking time.

According to an exemplary embodiment of the present invention, by detecting a duty cycle error of the output clock signal, stores the duty cycle control information for error cancellation, and generates and outputs an analog differential control voltage according to the duty cycle control information Feedback loop; The duty cycle control information is converted into a digital bit by a comparator and a continuous approximation register (SAR) by using the analog differential control voltage output from the analog feedback loop, and the digital differential control voltage is generated by a digital analog converter. An output digital feedback block; And a duty amplifier configured to receive an input of the analog differential control voltage and the digital differential control voltage output from the analog feedback loop and the digital feedback block, respectively, and to correct an input duty cycle. Is provided.

The digital feedback block may include: a comparator for comparing a difference between the analog differential control voltages output from the analog feedback loop and outputting a high or low digital voltage; A continuous approximation register for converting an output signal of the comparator into a digital bit using a binary search method and outputting the digital bit; And a digital analog converter for converting a digital bit output from the continuous approximation register into an analog signal and outputting a digital differential control voltage.

The continuous approximation register is characterized in that it is modified from the most significant bit to the lower bit in order from each of the most significant bits to approximate the analog differential control voltage input to the comparator.

The analog feedback loop includes a charge pump.

The duty amplifier uses a single stage duty amplifier or a two stage duty amplifier.

The two stage duty amplifier is characterized by consisting of two cascade differential amplifiers.

And a level converter installed at an output terminal of the duty amplifier to convert the corrected small-swing output clock of the duty amplifier into a full-swing output.

And a clock tree unit installed at an output terminal of the level converter and receiving an output signal of the level converter to increase a current driving capability and output an output clock signal.

After generating the analog differential control voltage during the analog duty cycle correction period, the analog feedback loop is equalized gradually according to the operation of the digital feedback block, and is fully equalized when the operation of the digital feedback block is completed.

As in the present invention, a continuous approximation register is applied to a hybrid feedback cycle correction circuit having a dual feedback loop, that is, an analog feedback loop and a digital feedback block, and thus, unlike a sequential search method used in a general counter, a binary search ( Binary Search) enables fast locking times linearly proportional to resolution and drive clock speed, and increases the feedback timing margin by lowering the drive clock speed of the digital feedback block. The effect is to increase the cycle accuracy and at the same time provide a fast locking time.

In addition, the continuous approximation resistor has a similar power consumption and area compared to a conventional finite state machine, so that it is easy to apply to a hybrid duty cycle correction circuit and is easy to design.

1 is a schematic configuration diagram of a hybrid duty cycle correction circuit according to the prior art.
2 is a schematic diagram of a hybrid duty cycle correction circuit using a continuous approximation register according to an embodiment of the present invention.
FIG. 3 is a circuit diagram of a single stage duty amplifier applicable to the duty amplifier shown in FIG. 2.
4 is a schematic diagram of a hybrid duty cycle correction circuit using a continuous approximation register according to another embodiment of the present invention.
FIG. 5 is a circuit diagram of a two stage duty amplifier applicable to the duty amplifier shown in FIG. 4.
6 is a flowchart illustrating an operation process of the continuous approximation register illustrated in FIGS. 2 and 4.
FIG. 7A illustrates a process of generating a control signal of a hybrid duty cycle correction circuit using a continuous approximation register according to the present invention, and FIG. 7B illustrates a process of generating a control signal of a hybrid duty cycle correction circuit to which a counter according to the prior art is applied. .
8A and 8B are conceptual views illustrating a change in feedback timing margin according to a driving clock speed of a digital feedback loop according to the present invention.
9A is a circuit diagram of an 8-bit continuous approximation register used in an embodiment of the present invention, and FIG. 9B is a circuit diagram of the individual continuous approximation register shown in FIG. 9A.
10A to 10B illustrate an input / output signal and a control signal of a hybrid duty cycle correction circuit using an 8-bit continuous approximation register according to an embodiment of the present invention.
11A to 11D are graphs comparing duty cycle correction accuracy of an output clock when a hybrid duty cycle correction circuit using a counter and a hybrid duty cycle correction circuit using a continuous approximation register are used in a finite state machine.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

FIG. 2 is a schematic diagram of a hybrid duty cycle correction circuit using a continuous approximation register according to an embodiment of the present invention, and FIG. 3 is a circuit diagram of a single stage duty amplifier applicable to the duty amplifier shown in FIG.

2, a hybrid duty cycle correction circuit 1000 using a continuous approximation register according to an embodiment of the present invention may include a duty amplifier 100, a level converter 200, a clock tree unit 300, and an analog feedback loop. 400 and digital feedback block 500.

The duty amplifier 100 converts the duty cycle of the output clock into a preset duty cycle in accordance with the analog differential control voltages Vctrl and Vctrlb generated in the dual feedback loop and the digital differential control voltages VDctrl and VDctrlb. Convert the mode voltage to compensate for the duty cycle.

The level converter 200 converts the corrected small-swing output clock of the duty amplifier 100 into a full-swing output and outputs it. The clock tree unit 300 is installed at the output terminal of the level converter 200. The output signal of OUT_CLK and OUT_CLKb are output by increasing the current driving capability by receiving the output signal of 200.

The charge pump of the analog feedback loop 400 detects a duty cycle error of the output clock signal, stores duty cycle control information for error cancellation in a capacitor, and generates analog differential control voltages Vctrl and Vctrlb in proportion thereto.

Analog feedback loop 400 has an analog differential control voltage (Vctrl, Vctrlb) generation time within about 50 nS, after which the duty cycle of the output clock maintains 50%. The analog differential control voltages Vctrl and Vctrlb are gradually equalized as the digital feedback block operates, and are fully equalized at the completion of the operation of the digital feedback block, thus losing the duty cycle correction role. Even during the process of equalizing the analog differential control voltages (Vctrl, Vctrlb), the output duty cycle is maintained at 50% by the digital differential control voltages (VDctrl, VDctrlb).

The digital feedback block 500 converts the analog differential control voltage output from the analog feedback loop into digital bits to replace the role of the analog feedback loop after the duty cycle is fixed.

The digital feedback block 500 uses the charge pump output of the analog feedback loop 400 to store the duty cycle control information in the digital bits of the continuous approximation register (SAR) 520, and the digital differential control voltages VDctrl and VDctrlb. Create When the operation of the digital feedback block 500 is completed, the digital differential control voltages VDctrl and VDctrlb completely replace and equalize the analog differential control voltages Vctrl and Vctrlb. Finally, output duty cycle correction is performed only with the duty cycle control information stored in the digital bits in the digital feedback block. Thus, during low power standby mode, duty cycle control information can be stored without power consumption and allows quick wakeup to active mode.

Therefore, during the standby or power-down mode, the duty-cycle error information is not stored in the charge pump of the analog feedback loop but can be turned off without being lost because it is stored as a digital bit. As a result, the wakeup time for switching from the standby mode or the power-down mode to the active mode using the duty-cycle error information stored as digital bits can be much shorter than the duty cycle correction circuit according to the prior art.

The digital feedback block 500 of the hybrid duty cycle correction circuit 1000 using the continuous approximation register according to an embodiment of the present invention includes a comparator 510, a continuous approximation register (SAR) 520, and a digital-to-analog converter (DAC). 530.

The comparator 510 compares the difference between the analog differential control voltages Vctrl and Vctrlb output from the analog feedback loop 400 and outputs the low or high digital voltages Up / Down.

The continuous approximation register (SAR) 520 stores the duty cycle control information according to the analog differential control voltages Vctrl and Vctrlb output from the analog feedback loop 400 as digital bits. The continuous approximation register (SAR) 520 finds and outputs a digital bit closest to the analog differential control voltage for input duty cycle correction using a binary search method according to the output signal of the comparator 510. That is, the continuous approximation register (SAR) 520 does not sequentially increase to determine the value of each bit, but the digital differential control voltage (output from the digital-to-analog converter in such a manner as to be modified from the most significant bit to the lower bit in order. VDctrl, VDctrlb) approximates the analog differential control voltages (Vctrl, Vctrlb) input to the comparator much faster.

The result is a fast locking time that is linearly proportional to the resolution and drive clock period, unlike a typical finite state machine.

The digital-analog converter 530 converts the digital bits output from the continuous approximation register 520 into analog voltages and outputs digital differential control voltages VDctrl and VDctrlb.

FIG. 3 is a circuit diagram of a single stage duty amplifier applicable to the duty amplifier shown in FIG. 2.

4 is a schematic diagram of a hybrid duty cycle correction circuit using a continuous approximation register according to another embodiment of the present invention, and FIG. 5 is a circuit diagram of a two stage duty amplifier applicable to the duty amplifier shown in FIG. 4. This embodiment is different from the above embodiment in that it uses a two-stage duty amplifier as the duty amplifier, and the rest of the configuration is similar and will be described in detail below with a different configuration.

Referring to FIG. 4, the hybrid duty cycle correction circuit using the continuous approximation register according to the present embodiment includes a first stage duty amplifier 151, a second stage duty amplifier 152, a level converter 200, and a clock tree unit ( 300, an analog feedback loop 400, and a digital feedback block 500.

FIG. 5 is a circuit diagram of the first and second stage duty amplifiers of the hybrid duty cycle correction circuit using the continuous approximation register shown in FIG. 4.

Referring to FIG. 5, a hybrid duty cycle correction circuit using a continuous approximation register according to an embodiment of the present invention uses a duty amplifier composed of two stages, that is, first and second stage duty amplifiers 151 and 152. The first and second stage duty amplifiers 151, 152 consist of two cascade differential amplifiers as a whole, which increases the isolation between the differential amplifiers and reduces the capacitive load on each stage output stage, resulting in a large gain bandwidth product. Get

The first stage duty amplifier 151 receives the analog differential control voltages Vctrl and Vctrlb output from the analog feedback loop. The second stage duty amplifier 152 receives the digital differential control voltages VDctrl and VDctrlb output from the digital feedback block. Since the output of the first and second stage duty amplifiers 151 and 152 has only one additional differential amplifier, the capacitive load can be distributed to obtain high frequency operation and low jitter. In addition, in the present embodiment, since the duty amplifier is composed of two stages, the duty-cycle correction range may be at least twice that of the single stage duty amplifier due to the increased stabilization of the feedback loop compared to the single stage.

6 is a flowchart illustrating an operation process of the continuous approximation register illustrated in FIGS. 2 and 4.

Referring to FIG. 6, first, a process of initializing all bits of the continuous approximation register to '0' is performed (S10). A process of starting an operation at the most significant bit is performed (S20). The process of setting the corresponding bit to '1' is performed (S30).

Then, the process of comparing the digital differential control voltage and the analog differential control voltage output value of the digital analog converter (DAC) is performed (S40). That is, compare the continuous approximation resistor value with the analog differential control voltage.

As a result of comparison, when the digital differential control voltage induced by the continuous approximation register value is greater than the analog differential control voltage, the process of clearing the corresponding bit of the continuous approximation register to 'O' is performed (S50).

On the other hand, if the digital differential control voltage induced by the continuous approximation register value is less than or equal to the analog differential control voltage, the process of checking whether all bits of the continuous approximation register are determined is performed (S60).

As a result of performing the S60 process, if not, that is, if all bit values of the continuous approximation register are not determined, the process moves to the lower bit (S70).

Then, the process returns to step S30 to repeat the above process.

On the other hand, when all the bit values of the continuous approximation register is determined as a result of performing the process S60, the process of writing the determined value in the register is performed (S80).

FIG. 7A illustrates a process of generating a control signal of a hybrid duty cycle correction circuit using a continuous approximation register according to the present invention, and FIG. 7B illustrates a process of generating a control signal of a hybrid duty cycle correction circuit to which a counter according to the prior art is applied. .

FIG. 7A illustrates an example of a control signal generation process of the hybrid duty cycle correction circuit when the 4-bit continuous approximation register is applied to the finite state machine, and the 4-bit counter is applied to the finite state machine.

For the N-bit counter, the sequential search method requires 2 ^N periods of the maximum digital feedback loop drive clock to determine the value of each bit.

On the other hand, the N-bit continuous approximation register uses a binary search method that determines the value of each bit by moving from the most significant bit to the lower bit step by step, so only N periods of the digital feedback loop driving clock are locked. The time decreases exponentially.

Also, because the continuous approximation register has a locking time that increases linearly with resolution, even if the speed of the digital feedback loop driving clock is reduced, the overall locking time does not change significantly. This allows the feedback timing margin to be increased to improve the accuracy of the output clock duty cycle.

8A and 8B are conceptual views illustrating a change in feedback timing margin according to a driving clock speed of a digital feedback loop according to the present invention.

The digital differential control voltages (VDctrl, VDctrlb) must vary by V _{1 bit} , and ideally the analog differential control voltages (Vctrl, Vctrlb) must also change by this amount as one bit change of the continuous approximation register digital output. In an ideal case, the variation of analog differential control voltages (Vctrl, Vctrlb) is given by

[expression]

T _CLK is the period of the digital feedback drive clock, C is the capacitive load of the charge pump output stage, and I _CP is the amount of current in the charge pump flowing to the capacitive load.

As T _CLK increases, the potential difference between the analog differential control voltage and the digital differential control voltage becomes equal. This also increases the duty cycle calibration accuracy of the output clock.

9A is a circuit diagram of an 8-bit continuous approximation register used in an embodiment of the present invention, and FIG. 9B is a circuit diagram of the individual continuous approximation register shown in FIG. 9A. Fig. 9A shows a circuit diagram of an 8-bit continuous approximation register, which is similar in complexity to other finite state machines and has the same input and output relationships, making it simple to substitute for a hybrid duty cycle correction circuit.

10A to 10B illustrate an input / output signal and a control signal of a hybrid duty cycle correction circuit using an 8-bit continuous approximation register according to an embodiment of the present invention.

FIG. 10A is a graph showing an input clock IN_CLK of a hybrid duty cycle correction circuit using a continuous approximation register according to an embodiment of the present invention, in which an input clock signal having a duty ratio of 80% is shown.

Figure 10b shows the analog differential control voltages (Vctrl, Vctrlb) output through the charge pump of the analog feedback loop and corrects the duty cycle of the output clock to 50% within about 50ns. The analog feedback loop is gradually equalized according to the operation of the digital feedback block, and is completely equalized at the completion of the digital feedback block to lose the duty cycle correction role.

10C illustrates the digital differential control voltages VDctrl and VDctrlb output through the digital feedback block. The continuous approximation register converts and stores the analog differential control voltages Vctrl and Vctrlb into digital bits, and shows how the digital differential control voltages VDctrl and VDctrlb are generated by the digital-to-analog converter. The duty cycle control information is stored as digital bits within 8 cycles of the drive clock of the digital feedback block, depending on the nature of the continuous approximation register that increases linearly with resolution.

FIG. 10D illustrates an output clock OUT_CLK that is output after all the calibration procedures of the hybrid duty cycle correction circuit using the continuous approximation register according to an embodiment of the present invention are shown, and an output clock signal having a duty cycle of 50% is shown. do.

11A to 11D are graphs comparing duty cycle correction accuracy of an output clock when a hybrid duty cycle correction circuit using a counter and a hybrid duty cycle correction circuit using a continuous approximation register are used in a finite state machine.

Referring to FIGS. 11A through 11D, the input clock having an operating frequency of 0.5 GHz to 2.0 GHz and a duty cycle of ± 35%, in the prior art, that is, the hybrid duty cycle correction circuit applying the counter has a maximum of 3.51%. There is a duty cycle error of the output clock.

In contrast, the hybrid duty cycle correction circuit using the continuous approximation register according to the present invention has a duty cycle error of up to 0.92% output clock under the same conditions, which shows that an improvement of about 82% can be obtained.

What has been described above is only an exemplary embodiment of a hybrid duty cycle correction circuit using a continuous approximation register according to the present invention, and the present invention is not limited to the above embodiment, as claimed in the following claims, Without departing from the gist of the present invention, anyone of ordinary skill in the art will have the technical spirit of the present invention to the extent that various modifications can be made.

100: duty amplifier
200: level converter
300: clock tree portion
400: analog feedback loop
500: digital feedback block
510: comparator
520: continuous approximation register (SAR)
530: digital to analog converter

Claims (9)

In a hybrid duty cycle correction circuit using a continuous approximation register,
An analog feedback loop which detects a duty cycle error of the output clock signal, stores duty cycle control information for error cancellation, and generates and outputs an analog differential control voltage according to the duty cycle control information;
A digital feedback block converting and storing the duty cycle control information into digital bits using a continuous approximation register (SAR) using the analog differential control voltage output from the analog feedback loop, and generating and outputting a digital differential control voltage; And
A duty amplifier receiving the analog differential control voltage and the digital differential control voltage output from the analog feedback loop and the digital feedback block and correcting an input duty cycle;
Hybrid duty cycle correction circuit using a continuous approximation register, characterized in that it comprises a.
The method of claim 1,
The digital feedback block,
A comparator for comparing a difference between the analog differential control voltages output from the analog feedback loop and outputting a high or low digital voltage;
A continuous approximation register for converting an output signal of the comparator into a digital bit using a binary search method and outputting the digital bit; And
And a digital analog converter which converts the digital bits output from the continuous approximation register into an analog signal and outputs a digital differential control voltage.
The method of claim 2,
The continuous approximation register is characterized in that the successive approximation to the analog differential control voltage input to the comparator to the digital differential control voltage output from the digital analog converter by modifying the lower bit in order from the most significant bit to determine each bit value Hybrid duty cycle correction circuit using approximate register.
The method of claim 1,
And said analog feedback loop comprises a charge pump.
The method of claim 1,
And the duty amplifier uses a single stage duty amplifier or a two stage duty amplifier.
The method of claim 5,
And said two stage duty amplifier comprises two cascade differential amplifiers.
The method of claim 1,
And a level converter installed at an output terminal of the duty amplifier and converting the corrected small-swing output clock of the duty amplifier into a full-swing output and outputting the full-swing output. .
The method of claim 7, wherein
And a clock tree unit provided at an output terminal of the level converter and outputting an output clock signal by increasing the current driving capability by receiving the output signal of the level converter. .
The method of claim 1,
After the analog feedback loop generates the analog differential control voltage during the analog duty cycle correction period, the analog differential control voltage is gradually equalized according to the operation of the digital feedback block, and at the time when the operation of the digital feedback block is completed. And said analog differential control voltage is fully equalized.

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