KR101190693B1 - Fabrication Method of Phase-Change Random Access Memory Device - Google Patents

Abstract

Providing a semiconductor substrate having a word line, forming a diode structure material layer over the entire structure of the semiconductor substrate, forming and patterning an interlayer insulating film on the diode structure material layer to form a lower electrode contact, and a lower electrode Sequentially forming a phase change material layer and an upper electrode material layer on the entire structure where the contact is formed, and patterning the upper electrode material layer, the phase change material layer, the interlayer insulating film, and the diode structure material layer to form a unit memory cell. Phase change memory device comprising forming

Description

Fabrication Method of Phase-Change Random Access Memory Device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a phase change memory device.

A phase-change random access memory (PCRAM) device changes a state of a phase change material pattern formed on a lower electrode by supplying or blocking a current to a heater, that is, a lower electrode, through a switching element.

As the switching element of the phase change memory device, a PN junction diode, a Schottky diode, or the like may be used, and a current must be supplied to each cell by applying a potential to the semiconductor substrate on which the switching device is formed.

In a phase change memory device employing a PN junction diode, current is supplied to each cell through a word line electrically connected to a junction region of a semiconductor substrate. In order to ensure the minimum operating performance of the phase change memory device, word lines are repeatedly formed for each specified number of cells. Accordingly, since the area for the word line needs to be allocated in addition to the area occupied by the memory cell, the degree of integration is reduced.

Therefore, recently, a metal word line is formed on a semiconductor substrate, and a Schottky diode electrically connected thereto is used as a switching element of a phase change memory device.

1 to 11 are diagrams for describing a general method of manufacturing a phase change memory device.

As shown in FIG. 1, the barrier metal layer 105 and the silicon layer 107 are sequentially formed on the semiconductor substrate 101 on which the word lines 103 are formed.

In addition, the silicon layer 107 and the barrier metal layer 105 are patterned by an exposure and etching process using a first mask (not shown) to be in a state as shown in FIG. 2.

Next, as shown in FIG. 3, spacers 109 are formed on sidewalls of the barrier metal layer 105 and the silicon layer 107 pattern, and a first interlayer insulating layer 111 is formed on the entire structure. 107) planarize so that the top is exposed.

Thereafter, as shown in FIG. 4, the metal layer 113 is formed on the entire structure and heat treatment is performed to form the metal silicide layer 115 (see FIG. 5). As a result, a Schottky Barrier Diode (SBD) including the barrier metal layer 105, the silicon layer 107, and the metal silicide layer 115 is completed.

FIG. 6 illustrates a state in which the second interlayer insulating layer 117 is formed on the entire structure on which the SBD is formed, and then the second interlayer insulating layer 117 is patterned by an exposure and etching process using a second mask (not shown). The top of the silicide layer 115 is exposed (see FIG. 7).

Subsequently, a bottom electrode contact (BEC) is formed as shown in FIG. 8. The lower electrode contact BEC may be formed in various ways. Referring to FIG. 8 as an example, after the second interlayer insulating layer 117 is patterned, the first conductive layer 119 is formed on the entire structure, and the entire surface is etched to form the first conductive layer 119 only at the bottom of the lower electrode contact hole. Remain. Thereafter, the spacer insulating layer 121 is formed on the entire structure, and then the spacer insulating layer 121 is left only on the inner wall of the lower electrode contact hole by etching the spacer. Then, the second conductive layer 121 and the buried insulating film 125 are formed on the entire structure and planarized to expose the upper portion of the second interlayer insulating film 117.

When the lower electrode contact BEC is formed, the phase change material layer 127 and the upper electrode material layer 129 are formed on the entire structure as shown in FIG. 9. As shown in FIG. 10, the upper electrode material layer 129 and the phase change material layer 127 are patterned by an exposure and etching process using a third mask (not shown) to form the phase change material pattern 127A and the upper part. The electrode 129A is formed.

Thereafter, an encapsulation layer 131 is formed on the outer wall of the phase change material pattern 127A and the upper electrode 129A, and a bit line 135 electrically connected to the upper electrode 129A is formed (see FIG. 11). ). Reference numeral 133 denotes a third interlayer insulating film.

As described above, in the current phase change memory device fabrication process, a patterning process using a mask is performed three times (see FIGS. 2, 7, and 10). Thus, the process is complicated, resulting in an increase in the time and cost required for the process.

In addition, in the current phase change memory device, the phase change material pattern 127A is formed in a line type. That is, it is formed without complete separation between adjacent cells. The phase change material is very sensitive to heat, and thus, when the phase change material pattern 127A is formed in a line type, heat may be conducted between adjacent cells, thereby causing a disturbance phenomenon. This disturbance phenomenon affects the operation of the cell, causing changes in data stored in the cell or causing the cell not to operate.

The present invention provides a method of manufacturing a phase change memory device capable of minimizing a process.

Another technical problem of the present invention is to provide a method of manufacturing a phase change memory device capable of improving the insulation characteristics between unit cells.

According to an aspect of the present invention, there is provided a method of manufacturing a phase change memory device, including: providing a semiconductor substrate having a word line; Forming a layer of diode structure material over the entire structure of the semiconductor substrate; Forming and patterning an interlayer insulating layer on the diode structure material layer to form a lower electrode contact; Sequentially forming a phase change material layer and an upper electrode material layer on the entire structure in which the lower electrode contacts are formed; And patterning the upper electrode material layer, the phase change material layer, the interlayer insulating film, and the diode structure material layer to form a unit memory cell.

In the present invention, the switching element and the phase change material pattern are simultaneously patterned. Therefore, the number of masks required for patterning can be minimized, and the exposure, etching and cleaning processes can be significantly reduced. As a result, the cost of the memory device can be reduced by simplifying the process and minimizing the cost.

In addition, in forming the phase change material pattern, it is formed in an island type to be completely separated from adjacent cells that do not share a word line. Therefore, it is possible to prevent the heat generated in a specific memory cell from being conducted to the adjacent phase change material pattern, thereby suppressing the disturbance phenomenon. Accordingly, the yield improvement and the operation reliability of the phase change memory device can be improved.

1 to 11 are cross-sectional views of a device for explaining a method of manufacturing a general phase change memory device;
12 to 19 are cross-sectional views of devices for describing a method of manufacturing a phase change memory device according to an embodiment of the present invention;
20 to 26 are cross-sectional views of devices for explaining a method of manufacturing a phase change memory device according to another embodiment of the present invention;
27 is a perspective view of the phase change memory device shown in FIG. 17;
FIG. 28 is a perspective view of the phase change memory device shown in FIG. 24.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

12 to 19 are cross-sectional views of devices for describing a method of manufacturing a phase change memory device according to an embodiment of the present invention.

As shown in FIG. 12, the diode constituent material layer 211 is formed on the semiconductor substrate 201 on which the word line 203 is formed. Here, the diode constituent material layer 211 may be a stacked structure of the barrier metal layer 205, the silicon layer 207, and the metal silicide layer 209. In addition, the silicon layer 207 may be formed using polysilicon, or may be formed by doping impurities after depositing an amorphous silicon layer. In addition, the metal silicide layer 209 may be formed through the reaction of a silicon layer with all possible metal materials capable of lowering interfacial resistance such as a cobalt silicide layer and a titanium silicide layer.

Next, as shown in FIG. 13, a first interlayer insulating film 213 is formed over the entire structure.

An exposure and etching process using a mask is performed to form a lower electrode contact hole by patterning the first interlayer insulating layer 213 as shown in FIG. 14. As a result, the top of the diode constituent material layer 211 is exposed.

Subsequently, as shown in FIG. 15, a lower electrode contact BEC is formed in the lower electrode contact hole.

The lower electrode contact BEC may be formed in various ways. For example, after the first interlayer insulating layer 213 is patterned, the first conductive layer 215 is formed on the entire structure, and the entire surface is etched to leave the first conductive layer 215 only at the bottom of the lower electrode contact hole. Thereafter, the spacer insulating layer 217 is formed on the entire structure, and then the spacer is etched to leave the spacer insulating layer 217 only on the inner wall of the lower electrode contact hole. The second conductive layer 219 and the buried insulating film 221 are formed on the entire structure and planarized to expose the upper portion of the first interlayer insulating film 213.

When the lower electrode contact BEC is formed, the phase change material layer 223 and the upper electrode material layer 225 are sequentially formed on the entire structure (see FIG. 16). Here, the phase change material layer 223 may be formed by physical vapor deposition (PVD).

Then, an exposure and etching process using a mask is performed. In this case, a double patterning process using a dot (DOT) type mask or a line type mask may be applied, and of course, the mask is disposed to expose a portion where the lower electrode contact is formed. As a result, as shown in FIG. 17, a unit memory cell including a Schottky barrier diode SBD, a lower electrode contact BEC, a phase change material pattern 223A, and an upper electrode 225A is formed.

Next, as shown in FIG. 18, an encapsulation layer 227 is formed on the outer wall of the unit memory cell, and a bit line 231 electrically connected to the upper electrode 225A is formed. Reference numeral 229 denotes a second interlayer insulating film.

As described above, in the present invention, after forming the diode constituent material layer 211, the lower electrode contact BEC and the phase change material layer 223 and the upper electrode material layer 225 are formed without performing a patterning process. The Schottky barrier diode SBD, the lower electrode contact BEC, the phase change material pattern 223A, and the upper electrode 225A are simultaneously patterned.

Therefore, the process process can be simplified and a cost reduction effect can be expected.

In addition, by performing a double patterning process using a dot type mask or a line type mask, the phase change material pattern 223A may be completely separated from an adjacent cell, thereby suppressing the disturbance phenomenon.

Meanwhile, in the above-described phase change memory device manufacturing process, the lower electrode contact formation and the bit line forming process may be easily changed as necessary, and another example thereof will be described below.

20 to 26 are cross-sectional views of devices for describing a method of manufacturing a phase change memory device according to another embodiment of the present invention.

First, as described with reference to FIGS. 12 and 13, the first interlayer insulating layer 213 is formed on the diode constituent material layer 211.

As shown in FIG. 20, the first interlayer insulating film 213 is patterned to form a lower electrode contact hole, and then a conductive material layer 301 and a spacer insulating film 303 are formed over the entire structure.

Thereafter, as shown in FIG. 21, the spacer insulating layer 303 and the conductive material layer 301 are selectively removed by a spacer etching process. Accordingly, the conductive material layer 301 remains only on the inner wall of the lower electrode contact hole and the lower portion of the spacer insulating layer 303. In this sense, the lower electrode contact BEC illustrated in FIG. 21 may be referred to as a wall type.

A buried insulating film 305 is formed over the entire structure and planarized so that the upper portion of the first interlayer insulating film 213 is exposed.

FIG. 22 illustrates a state in which a phase change material layer 307, an upper electrode material layer 309, and an antireflection film 311 are formed on an entire structure in which a lower electrode contact BEC is formed. Here, the phase change material layer 307 may be formed by physical vapor deposition (PVD).

In this state, the anti-reflection film 311, the upper electrode material layer 309 and the phase change material layer 307 are patterned in a first direction, for example, a direction perpendicular to the word line 203, and the patterning structure 307A, 309A and 311A, an encapsulation layer 313 is formed on the outer wall (see FIG. 23).

Subsequently, the anti-reflection film 311, the upper electrode material layer 309, and the phase change material layer 307 are patterned in a second direction, for example, in the direction of the word line 230, and the patterning structures 307A, 309A, and 311A. An encapsulation layer (see 319 in FIG. 28) is formed on the outer wall, and the first interlayer insulating film 213 and the diode structure material are formed using the patterning structures 307A, 309A, and 311A as hard masks, as shown in FIG. 24. Layer 211 is patterned. As a result, a unit cell consisting of the Schottky barrier diode SBD, the lower electrode BEC, the phase change material pattern 307A, and the upper electrode 309A is formed.
That is, in the present embodiment, the anti-reflection film 311, the upper electrode material layer 309, and the phase change material layer 307 are first patterned in the vertical direction of the word line, and then an encapsulation layer is formed on the exposed outer wall. . The encapsulation layer is formed on the exposed outer wall after the secondary patterning in the word line direction. Accordingly, the etching damage may be prevented from being applied to the patterning structures 307A, 309A, and 311A during the two etching processes and the subsequent diode etching process for the patterning structures 307A, 309A, and 311A.

Next, as shown in FIGS. 25 and 26, a second interlayer insulating film 315 is formed over the entire structure and patterned to expose the upper portion of the upper electrode 309A. The bit line 317 is formed in electrical contact with the upper electrode 309A.

In the above description, the double patterning is performed in the patterning process of FIGS. 23 and 24. However, the present invention is not limited thereto, and the Schottky barrier diode (SBD), the lower electrode contact (BEC), It goes without saying that the unit cell including the phase change material pattern 307A and the upper electrode 309A may be formed by a simultaneous patterning process.

FIG. 27 is a perspective view of the phase change memory element shown in FIG. 17, for example, showing a patterning result using a dot type mask.

In the exposure process using a dot type mask, wavelengths, such as I-line, KrF, ArF, ArFi, EUV, can be used. In addition, the dot type mask may use any one of a binary intensity mask (BIM), an embedded attenuated phase shifted mask (EASPM), an alternating aperture phase shift mask (AAPSM), and a phase inversion (CPL) mask.

As shown in FIG. 27, it can be seen that the phase change material pattern 223A is formed to be completely separated from adjacent cells that do not share a word line. In FIG. 27, the encapsulation layer 227 is omitted for convenience of understanding, but as described above, the outer circumferential surface of the unit cell is protected by the encapsulation layer 227.

FIG. 28 is a perspective view of the phase change memory device shown in FIG. 24, for example, illustrating a patterning result through a double patterning process.

Also in this case, the phase change material pattern 307A is formed to be completely separated from all adjacent cells through the first line patterning process for the word line direction and the second line patterning process for the bit line direction, thereby affecting the heat of the adjacent cells. It is free from the problem, and finally, it is possible to obtain an advantage of preventing the disturbance phenomenon.

Moreover, when the double patterning process is used, the cell-to-cell spacing can be made finer, which is advantageous for high integration of the device.
In addition, since the patterning structures 307A, 309A, and 311A are protected by the encapsulation layers 311 and 319 before the diode structures are patterned to form the Schottky barrier diode (SBD), the patterning structures 307A, 309A, Etch damage to 311A) can also be prevented.

Regardless of which patterning process is applied, in the present invention, the switching element (schottky barrier diode), the phase change material pattern, and the upper electrode are simultaneously patterned, and the phase change material pattern is formed in an island type completely separated from the adjacent cells. As a result, the yield and operational reliability of the phase change memory device are improved.

In the above description, a case where a Schottky barrier diode is used as the switching element has been described as an example. However, the present invention is not limited thereto, and it is a matter of course that a PN junction diode formed by forming a silicon layer on a word line and implanting impurities at a predetermined depth can be adopted as a switching element.

Thus, those skilled in the art will appreciate that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

201: semiconductor substrate
203: wordline
211: diode structure material layer
213: first interlayer insulating film
215, 219, 301: lower electrode contact
217, 303: spacer insulating film
221, 305: buried insulating film
223, 307: phase change material layer
225, 309: upper electrode material layer
227, 313: encapsulation layer
229 and 315: second interlayer insulating film
231, 317: bit line
311: antireflection film

Claims (8)

Providing a semiconductor substrate having a word line formed thereon;
Forming a layer of diode structure material over the entire structure of the semiconductor substrate;
Forming and patterning an interlayer insulating layer on the diode structure material layer to form a lower electrode contact;
Sequentially forming a phase change material layer and an upper electrode material layer on the entire structure in which the lower electrode contacts are formed;
First patterning the upper electrode material layer and the phase change material layer in a direction perpendicular to the word line;
Forming an encapsulation layer on both sidewalls of the upper electrode material layer and the phase change material layer exposed by the primary patterning to form a primary patterning structure;
Second patterning the first patterning structure in the direction of the wordline;
Forming encapsulation layers on both sidewalls of the primary patterning structure exposed by the secondary patterning to form a secondary patterning structure; And
Patterning the interlayer insulating layer and the diode structure material layer using the secondary patterning structure as a hard mask to form a unit memory cell;
Phase change memory device manufacturing method comprising a. delete delete delete Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1,
The forming of the diode structure material layer may include sequentially forming a barrier metal layer, a silicon layer, and a metal silicide layer on the word line. Claim 6 has been abandoned due to the setting registration fee. The method of claim 1,
Forming the diode structure material layer comprises: forming a silicon layer on the wordline; And
Implanting impurities into the silicon layer at a specified depth;
Phase change memory device manufacturing method comprising a. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1,
The forming of the lower electrode contact may include forming a lower electrode contact hole by patterning the interlayer insulating layer;
Forming a first conductive material layer on a bottom of the lower electrode contact hole;
Forming a spacer insulating layer on an inner wall of the lower electrode contact hole;
Sequentially forming a second conductive material layer and a buried insulating film on the entire structure; And
Planarizing the exposed interlayer insulating film;
Phase change memory device manufacturing method comprising a. Claim 8 was abandoned when the registration fee was paid. The method of claim 1,
The forming of the lower electrode contact may include forming a lower electrode contact hole by patterning the interlayer insulating layer;
Sequentially forming a conductive material layer and a spacer insulating film on the entire structure;
Forming a lower electrode contact on an inner sidewall of the lower electrode contact hole and a lower portion of the spacer insulating layer by performing a spacer etching process; And
Forming a buried insulating film over the entire structure and planarizing the upper portion of the interlayer insulating film;
Phase change memory device manufacturing method comprising a.

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