KR101185797B1 - Methode of building clock distribution path and 3-dimensional integrated circuit including clock distribution path - Google Patents

Abstract

The three-dimensional integrated circuit includes a tree clock distribution path, a substrate, at least one semiconductor chip and at least one interposer layers. The tree clock distribution path carries a clock signal and includes a first clock path, a second clock path, and a wiring path. The first clock path is comprised of at least one first through silicon vias passing through the semiconductor chips to transfer the clock signal in a first direction. The second clock path is composed of at least one second through silicon vias passing through the semiconductor chips to transmit the clock signal in a second direction and a first direction. A wiring path connects the first clock path and the second clock path. Thus, skew and jitter of the clock signal distributed to the plurality of semiconductor layers of the three-dimensional integrated circuit is reduced.

Description

METHODE OF BUILDING CLOCK DISTRIBUTION PATH AND 3-DIMENSIONAL INTEGRATED CIRCUIT INCLUDING CLOCK DISTRIBUTION PATH}

The present invention relates to a three-dimensional integrated circuit, and more particularly, to a three-dimensional integrated circuit including a clock distribution path forming method and a clock distribution path.

As semiconductor chips become smaller and lighter, three-dimensional integrated circuits capable of high speed / wideband input / output (I / O) transmission have been studied. The stacking technology can improve the integration and signal transmission characteristics by implementing an electronic circuit including a semiconductor chip or a semiconductor chip package. As a method of connecting a plurality of stacked semiconductor chips to each other, there is a bonding wire method and a through silicon via (TSV) method. The bonding wire method is one of methods for connecting each chip in a stacked 3D integrated circuit, and the location and number of bond pads for connecting the bonding wires are limited, and the semiconductor chip stacked on the upper side is smaller than the semiconductor chip in the lower layer. There is a problem. In the case of using the TSV, the above-mentioned limitation is not provided, and the wiring distance can be significantly shortened compared to the bonding wire method, so that the device can be faster, lower in power, and smaller in size.

In a three-dimensional integrated circuit in which a plurality of semiconductor chips are stacked, a through silicon via penetrating through the plurality of semiconductor chips may be used to transmit a single clock signal for driving the plurality of semiconductor chips. The clock may be distributed to a plurality of semiconductor chips through the through silicon vias. In this case, there is a problem that skew may occur because the time at which the clock reaches the plurality of semiconductor chips from the clock generator is different.

It is an object of the present invention to provide a three-dimensional integrated circuit comprising a tree clock distribution path that can minimize skew and jitter in the clock signal.

It is an object of the present invention to provide a method of forming a tree clock distribution path that can minimize skew and jitter in a clock signal.

A three-dimensional integrated circuit according to an embodiment of the present invention for achieving the above object includes a tree clock distribution path, a substrate, at least one semiconductor chip and at least one interposer layers formed on the substrate. The tree clock distribution path carries a clock signal and includes a first clock path, a second clock path, and a wiring path. The first clock path is composed of at least one first through-silicon vias passing through the semiconductor chips to transmit the clock signal in a first direction from the substrate side to the semiconductor chip side. The second clock path includes at least one second through silicon via passing through the semiconductor chips to transmit the clock signal in a second direction and a first direction opposite to the first direction. The wiring path connects the first clock path and the second clock path. The at least one interposer layers are located between the at least one semiconductor chip.

The tree clock distribution path may further include a terminal wiring path connecting the second clock path and a clock terminal of the at least one semiconductor chip to transfer the clock signal to the clock terminal.

In at least one example embodiment, the thicknesses of the at least one semiconductor chip may be the same.

In an embodiment, the thickness of the interposer layers may be the same as the thickness of the semiconductor chips.

In one embodiment, the material constituting the first through silicon vias and the second through silicon vias may be any one of copper, aluminum, tungsten, and polysilicon.

In one embodiment, the interposer layer may be a silicon interposer.

In one embodiment, the material constituting the first through silicon vias and the second through silicon vias may be any one of copper, aluminum, tungsten, and polysilicon.

According to an embodiment of the present disclosure, a method of forming a tree clock distribution path of a 3D integrated circuit may include determining positions of first through silicon vias and second through silicon vias formed in a semiconductor chip, Determining positions of third through silicon vias and fourth through silicon vias formed in the interposer layer to be stacked; forming the first through silicon vias and the second through silicon vias in the semiconductor chip; Forming the interposer layer on the chip, forming the third through silicon via connected to the first through silicon via and the fourth through silicon via connected to the second through silicon via on the interposer layer And forming a wiring path connecting the third through silicon via and the fourth through silicon via to the interposer layer. Includes steps.

In an embodiment, the thickness of the semiconductor chip and the thickness of the interposer layer may be the same.

In one embodiment, the interposer layer may be a silicon interposer.

In one embodiment, the material constituting the first through silicon vias and the second through silicon vias may be any one of copper, aluminum, tungsten, and polysilicon.

A method of forming a tree clock distribution path of a three-dimensional integrated circuit according to an embodiment of the present invention may include determining positions of a first clock path and a second clock path, and determining the determined first clock path and the second clock path. Determining a wiring path connecting the first clock path and the second clock path based on a position of the at least one semiconductor substrate; at least one semiconductor based on the determined first clock path, a position of the second clock path, and a wiring path; Stacking chips, at least one interposer layers and at least one wiring layer, vias through the stacked semiconductor chips, interposer layers and wiring layers based on the determined position of the first clock path and the second clock path Forming a hole and filling the formed via hole with a conductive material to form a through silicon via .

In an embodiment, the thickness of the semiconductor chip and the thickness of the interposer layer may be the same.

In one embodiment, the interposer layer may be a silicon interposer.

A method of forming a tree clock distribution path of a three-dimensional integrated circuit according to an embodiment of the present invention may include: alternately stacking a plurality of semiconductor chips and a plurality of interposer layers; Forming a plurality of via holes through the interposer layer, filling a conductive material in some of the formed via holes, and filling an insulating material in some of the via holes existing on top of the filled conductive material And filling conductive material in via holes present on top of the filled insulating material.

The system according to an embodiment of the present invention includes a three-dimensional integrated circuit, a central processing unit and at least one input / output device. A plurality of semiconductor chips and interposer layers are alternately stacked in the three-dimensional integrated circuit, and the clock signal is distributed by a tree clock distribution path. The tree clock distribution path includes a first clock path, a second clock path, and a wiring path connecting the first clock path and the second clock path through the plurality of semiconductor chips and the interposer layers.

In an embodiment, the plurality of semiconductor chips may be memory chips.

The three-dimensional integrated circuit according to the embodiments of the present invention as described above includes a tree clock distribution path. The tree clock distribution path reduces skew and jitter of a clock signal distributed to a plurality of semiconductor layers, thereby making it suitable for high-speed operation and reducing system errors. Therefore, the operating characteristics of the three-dimensional integrated circuit can be improved.

1 is a perspective view illustrating an example of a three-dimensional integrated circuit system.
2 is a perspective view illustrating an example of a three-dimensional integrated circuit system including a single clock distribution path.
3 is a cross-sectional view illustrating a clock signal distributed to each semiconductor layer through a single clock distribution path.
4 is a cross-sectional view illustrating a clock signal distributed to clock terminals of each semiconductor layer through a single clock distribution path.
5 is a perspective view illustrating an example of a 3D integrated circuit system including a tree clock distribution path according to an embodiment of the present invention.
6 is a cross-sectional view illustrating a clock signal distributed to each semiconductor layer through a tree clock distribution path according to an embodiment of the present invention.
7 is a cross-sectional view illustrating a clock signal distributed to clock terminals of each semiconductor layer through a tree clock distribution path according to an embodiment of the present invention.
FIG. 8 is a diagram illustrating a structure of a second interposer layer of FIG. 6.
FIG. 9 is a diagram illustrating a structure of a first interposer layer of FIG. 6.
FIG. 10 is a diagram illustrating a structure of the semiconductor layer of FIG. 6.
FIG. 11 is a perspective view illustrating a structure of a second interposer layer of FIG. 8, a first interposer layer of FIG. 9, and a semiconductor layer of FIG. 10.
12 is a graph illustrating a skew of a three dimensional integrated circuit system including a single clock distribution path and four semiconductor layers.
FIG. 13 is a graph illustrating an eye diagram of a three dimensional integrated circuit system including a single clock distribution path and four semiconductor layers.
14 is a graph illustrating a skew of a three-dimensional integrated circuit system according to an embodiment of the present invention.
FIG. 15 is a graph illustrating an eye diagram of a 3D integrated circuit system according to an exemplary embodiment.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. In describing the drawings, similar reference numerals are used for the components.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof that has been described, and that one or more of them is present. It is to be understood that it does not exclude in advance the possibility of the presence or addition of other features or numbers, steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

1 is a perspective view illustrating an example of a three-dimensional integrated circuit system.

Referring to FIG. 1, the 3D integrated circuit system 10 may include first to fourth memory chips 110, 120, 130, and 140, a digital circuit 150, a silicon interposer layer 160, and an analog circuit 170. ), A micro electro mechanical system (MEMS) 180 and a package 190.

Since the first to fourth memory chips 110, 120, 130, and 140 of the stacked structure occupy a relatively small area than the memory chips implemented in a single plane, the circuit and the system may be miniaturized. However, an additional wiring structure is required to supply a clock signal, a driving power, and the like to the first to fourth memory chips 110, 120, 130, and 140 having the stacked structure.

The microelectromechanical system 180 refers to a device in which mechanical components, sensors, actuators, and electronic circuits are integrated on a single silicon substrate as a fine technology. Although mainly manufactured using semiconductor integrated circuit fabrication technology, the step of manufacturing a three-dimensional shape is also included. Applications include inkjet printer heads, pressure sensors, acceleration sensors, gyroscopes, projectors, and the like. The three-dimensional integrated circuit system 10 is mainly used in the semiconductor field, but may be used including the microelectromechanical system 180 as shown in FIG. 1.

2 is a perspective view illustrating an example of a three-dimensional integrated circuit system including a single clock distribution path.

Referring to FIG. 2, the 3D integrated circuit system 20 may include a digital circuit 205, first to fourth semiconductor chips 221, 222, 223, and 224, a logic die 230, and a silicon interposer. 240, microelectromechanical system 250, analog circuit 260, and package 270.

The digital circuit 205 may include a clock generator 210. The clock signal CLOCK generated by the clock generator 210 of the digital circuit 205 is output through the clock terminal 215 of the digital circuit and passes through the silicon interposer 240 and the logic die 230 to form a first signal. To fourth semiconductor chips 221, 222, 223, and 224. In FIG. 2, the clock signal CLOCK is illustrated by an arrow composed of dotted lines.

Since the 3D integrated circuit system 20 distributes the clock signal CLOCK through a single clock distribution path, the clock signal CLOCK is applied to the fourth semiconductor chip 224 stacked directly on the logic die 230. First, the clock signal CLOCK may be provided in the order of the third semiconductor chip 223, the second semiconductor chip 222, and the first semiconductor chip 221.

For example, when the 3D integrated circuit system 20 is an image processing apparatus such as a graphic card, the digital circuit 205 may be a graphic processing unit (GPU). In addition, the first to fourth semiconductor chips may be first to fourth memory chips, respectively. The image processing apparatus may store image information in the first to fourth memory chips.

In order to describe the configuration of the single clock distribution structure in more detail, a description of a part of the cross-sectional view shown by the cross section D1 will be described later with reference to FIG. 3.

3 is a cross-sectional view illustrating a clock signal distributed to each semiconductor layer through a single clock distribution path.

Referring to FIG. 3, there is shown a cross-sectional view of a three-dimensional integrated circuit 30 represented by cross section D1 of FIG. 2. 3, only the first to fourth semiconductor chips 311, 312, 313, and 314, the logic die 320, and the substrate 330 of the three-dimensional integrated circuit system are shown, and other components are not shown. . In FIG. 3, the clock signal CLOCK is illustrated by an arrow including a solid line.

The three-dimensional integrated circuit system 30 of FIG. 3 uses a single clock distribution path 370 for clock signal CLOCK distribution. The single clock distribution path 370 is a through silicon via formed in a row on the first to fourth semiconductor chips 311, 312, 313, and 314 and the logic die 320, respectively, in a direction orthogonal to the substrate 330. Can be configured. In FIG. 3, the five through silicon vias formed in a row on the first to fourth semiconductor chips 311, 312, 313, and 314 and the logic die 320 respectively form a single clock distribution path 370.

When using the single clock distribution path 370, the clock signal CLOCK is applied to the fourth semiconductor chip 314 among the first to fourth semiconductor chips 311, 312, 313, and 314, as shown in FIG. 3. It arrives first, and arrives in order of the third semiconductor chip 313, the second semiconductor chip 312, and the first semiconductor chip 311. Therefore, the clock signal CLOCK reaching the fourth semiconductor chip 314 located at the lowermost part is compared with the clock signal CLOCK arriving at the first semiconductor chip 311 located at the uppermost part. Skew and jitter occur between The skew and jitter are factors that degrade the performance of a three-dimensional integrated circuit system.

4 is a cross-sectional view illustrating a clock signal distributed to clock terminals of each semiconductor layer through a single clock distribution path.

Referring to FIG. 4, the flow of the clock signal CLOCK is illustrated by an arrow including a dotted line. The clock signal CLOCK generated by the clock generator 410 is transferred to the wiring layer 401 of the silicon interposer 403 through the through silicon vias 415 of the digital circuit 405. Bumps 417 may be formed between the digital circuit 405 and the wiring layer 401 of the silicon interposer 403 to connect the through silicon vias 415 and the wiring layer 401, with an underfill layer around them. 418 may be formed.

The clock signal CLOCK transferred to the lower portion of the logic die 460 in which the semiconductor chips 420, 430, 440, and 450 are stacked through the wiring layer 401 may be first to fourth through the single clock distribution path 480. Transferred to the semiconductor chips 420, 430, 440, and 450. An underfill layer 490 may be formed between the logic die 460 and the wiring layer 401. The single clock distribution path 480 includes first through fourth semiconductor chips 420, 430, 440, 450 and through silicon vias 421, 431, 441, 451, 461 through the logic die 460. do. The single clock distribution path 480 may include bumps 422, 432, 442, 452, 462 connecting the through silicon vias 421, 431, 441, 451, 461. The clock signal CLOCK is transmitted to the clock terminals 470 included in the first to fourth semiconductor chips 420, 430, 440, and 450 through the single clock distribution path 480.

As shown in FIG. 4, when the single clock distribution path 480 is used, the clock signal CLOCK is most closely applied to the fourth semiconductor chip 450 among the first to fourth semiconductor chips 420, 430, 440, and 450. First, the first semiconductor chip 440, the second semiconductor chip 430, and the first semiconductor chip 420 are reached in this order. Therefore, the clock signal CLOCK reaching the clock terminal of the fourth semiconductor chip 440 located at the lowermost part is compared with the clock signal CLOCK reaching the clock terminal of the first semiconductor chip 420 located at the uppermost part. Skew and jitter occur between the two clock signals CLOCK. The skew and jitter are factors that degrade the performance of a three-dimensional integrated circuit system.

5 is a perspective view illustrating an example of a 3D integrated circuit system including a tree clock distribution path according to an embodiment of the present invention.

Referring to FIG. 5, a three-dimensional integrated circuit system 50 according to an embodiment of the present invention may include a digital circuit 505, first to fourth semiconductor chips 521, 522, 523, and 524, and first to fourth materials. Three interposer layers 531, 532, 533. The three-dimensional integrated circuit system 50 includes a logic die 540, a silicon interposer 550, a microelectromechanical system 560, an analog circuit 260, and a package 270.

The digital circuit 505 may include a clock generator 510. The clock signal CLOCK generated by the clock generator 510 of the digital circuit 505 is output through the clock terminal 515 of the digital circuit and passes through the silicon interposer 550 and the logic die 540 to be first. To fourth semiconductor chips 521, 522, 523, and 524. In FIG. 2, the clock signal CLOCK is illustrated by an arrow composed of dotted lines. Referring to FIG. 5 in detail, the clock signal CLOCK first passes through the logic die 540, the fourth semiconductor chip 524, the third interposer layer 533, and the third semiconductor chip 523, and then the second interlayer. A foamer layer 532 is reached. The clock signal CLOCK is branched through a wiring path above the second interposer layer 532 to pass through the second semiconductor chip 522 to reach the first interposer layer 531, and the third semiconductor chip ( Pass 523 to reach third interposer layer 533. The branched clock signals CLOCK each branch again to reach the first semiconductor layer 521, the second semiconductor layer 522, the third semiconductor layer 523, and the fourth semiconductor layer 524. In the 3D integrated circuit system 50 including the tree clock distribution path according to an embodiment of the present invention, since the clock signal CLOCK is transmitted through the tree clock distribution path, the first to fourth semiconductor chips 521, 522, Skew and jitter of the clock signal CLOCK reaching 523 and 524 is minimized.

In FIG. 5, a three-dimensional integrated circuit system in which four first to fourth semiconductor chips 521, 522, 523, and 524 are stacked is illustrated, but includes a tree clock distribution path according to an embodiment of the present invention. The three-dimensional integrated circuit system may include at least two semiconductor chips, that is, the tree clock distribution path may be used in a three-dimensional integrated circuit system including two or more semiconductor chips. As the jitter and skew of the signal increases, the utility of the tree clock distribution path can be increased.

In order to describe in more detail the tree clock distribution path of the three-dimensional integrated circuit system 50 according to an embodiment of the present invention, a description of a part of the cross-sectional view shown by the cross section D2 will be described later with reference to FIG. 6. do.

6 is a cross-sectional view illustrating a clock signal distributed to each semiconductor layer through a tree clock distribution path according to an embodiment of the present invention.

6 shows a tree clock distribution path of a three-dimensional integrated circuit system 60 in which four first to fourth semiconductor chips 611, 612, 613, and 614 are stacked. As described above, the three-dimensional integrated circuit system 60 in which the first to fourth semiconductor chips 611, 612, 613, and 614 are stacked is included in one embodiment of the present invention, and various numbers of semiconductor chips are stacked. The tree clock distribution path may also be applied to a three-dimensional integrated circuit system.

Referring to FIG. 6, a three-dimensional integrated circuit system 60 includes a tree clock distribution path for transferring a clock signal, a substrate 640, at least one semiconductor chip 611, 612, 613, and 614 and the semiconductor chips 611. At least one interposer layers 621, 622, 623 positioned between 612, 613, and 614.

The tree clock distribution path includes a first clock path 681, a second clock path 682, and a wiring path (not shown).

The first clock path 681 is composed of at least one first through-silicon vias passing through the semiconductor chips 611, 612, 613, and 614 and the interposer layers 621, 622, and 623 so that the clock signal ( CLOCK) is transferred from the substrate 640 side in the first direction toward the semiconductor chip side.

The second clock path 682 is composed of at least one second through silicon via penetrating through the semiconductor chips and the interposer layers so that a clock signal CLOCK is opposite to the first direction and the second direction and the Transfer in the first direction. That is, the clock signal CLOCK is branched from the second clock path 682 and transmitted to the direction of the first semiconductor chip 611 located on the upper side and the direction of the fourth semiconductor chip 614 located on the lower side. Through the above process, since the path lengths of the clock signals transmitted to the plurality of stacked semiconductor chips are the same, skew and jitter of the clock signals may be effectively reduced.

A wiring path (not shown), that is, a first wiring path connects the first clock path 681 and the second clock path 682. That is, in the embodiment of FIG. 6, the first wiring path is formed between the second interposer layer 622 and the second semiconductor chip 612 to form the first clock path 681 and the second clock path 682. Can connect

In the embodiment of FIG. 6, the through silicon vias constituting the first clock path 681 may include a logic die 630, a fourth semiconductor chip 614, a third interposer layer 623, and a third semiconductor chip 613. And up to the second interposer layer 622. However, for ease of processing, through silicon vias are formed up to the second semiconductor chip 612, the first interposer layer 621, and the first semiconductor chip 611 to collectively form via holes and through silicon vias. May be In this case, since the through silicon vias constituting the first clock path 681 are not directly connected to the clock terminals of the respective semiconductor chips, there is no difference in the path through which the clock signal CLOCK is transmitted to each semiconductor chip. That is, in order to form the first clock path 681, through silicon vias must be formed from the substrate 640 to at least the second interposer layer 622, and the through silicon vias are formed on the second interposer layer 622. May be further formed.

In the embodiment of FIG. 6, since the 3D integrated circuit system 60 includes four semiconductor chips, a tree clock distribution path according to an embodiment of the present invention may be used to distribute clock signals CLOCK to the four semiconductor chips. Third clock paths 683 and 684 and second wiring paths (not shown) are further included. The second wiring paths are respectively formed between the first interposer layer 621 and the first semiconductor chip 611 and between the third interposer layer 623 and the third semiconductor chip 613, respectively. The second wiring path formed between the first interposer layer 621 and the first semiconductor chip 611 connects the second clock path 682 and the third clock path 683, and the third interposer layer ( The second wiring path formed between the 623 and the third semiconductor chip 613 connects the second clock path 682 and the third clock path 684. The third clock paths 683 and 684 branch clock signals CLOCK transmitted from the first clock path 682, respectively. The third clock paths 683 and 684 transfer the branched clock signals CLOCK to the first to fourth semiconductor chips 611, 612, 613, and 614, respectively. Terminals for transferring the transferred clock signals CLOCK to the clock terminals 650 of the semiconductor chips 611, 612, 613, and 614 on the first to fourth semiconductor chips 611, 612, 613, and 614. The wires 660 may be further included.

As described below with reference to FIGS. 8 through 11, each of the semiconductor chips 611, 612, 613, and 614 may include a plurality of clock terminals 650, so that the tree clock distribution path includes a plurality of second clock channels. It may include a clock path and a plurality of third clock paths. The first semiconductor chip 611 also includes a plurality of through silicon vias 670, and the plurality of through silicon vias 670 form a plurality of third clock paths 683 that are different from each other. That is, although one third clock path 683 is illustrated in FIG. 6 to transfer the clock signal CLOCK to the first semiconductor chip 611, more clock paths may be included as part of the tree clock distribution path. have.

In order to minimize skew and jitter of clock signals CLOCK transmitted to each of the semiconductor chips 611, 612, 613, and 614, the semiconductor chips 611, 612, and 613 of the 3D integrated circuit according to an exemplary embodiment of the present invention are provided. , 614 may be the same thickness. In addition, the thicknesses of the interposer layers 621, 622, and 623 may also be the same, and the thicknesses of the interposer layers 621, 622, and 623 may be the same as the thicknesses of the semiconductor chips 611, 612, 613, and 614. have. In addition, the interposer layers 621, 622, 623 may be comprised of silicon interposers.

The material constituting the through silicon vias included in the tree clock distribution structure of the 3D integrated circuit according to the exemplary embodiment of the present invention may be a material having good conductivity to quickly transmit the clock signal CLOCK. That is, the material constituting the through silicon vias may be any one of metal materials such as copper, aluminum, tungsten, or polysilicon.

According to one or more exemplary embodiments, a method of forming a tree clock distribution path of a three-dimensional integrated circuit includes determining a location of a first through silicon via and a second through silicon via formed in a semiconductor chip, and stacking the semiconductor chip on the semiconductor chip. Determining positions of third through silicon vias and fourth through silicon vias formed in the interposer layer to be formed; forming the first through silicon vias and the second through silicon vias in the semiconductor chip; Forming an interposer layer thereon, forming a third through silicon via connected to the first through silicon via and a fourth through silicon via connected to the second through silicon via on the interposer layer And forming a wiring path on the interposer layer to connect the third through silicon via and the fourth through silicon via. And a step.

Determining positions of the first through silicon via and the second through silicon via corresponds to a part of the process of forming the first clock path 681 and the second clock path 682. Referring to FIG. 6, the first clock path 681 and the second clock path 682 are commonly included in the second interposer layer 622 and the third semiconductor chip 613. That is, in order to form the first clock path 681 and the second clock path 682, the through silicon vias must be formed in at least one semiconductor chip and the interposer layer. The via may be part of the first clock path 681 and the second through silicon via may be part of the second clock path 682. Accordingly, the positions of the first through silicon via and the second through silicon via are determined based on the positions of the first clock path 681 and the second clock path 682 included in the entire 3D integrated circuit.

Determining positions of the third through silicon via and the fourth through silicon via formed in the interposer layer stacked on the semiconductor chip, and also forming the first clock path 681 and the second clock path 682. Corresponds to a part of. Referring to FIG. 6, the first clock path 681 and the second clock path 682 are commonly included in the second interposer layer 622 and the third semiconductor chip 613. Therefore, the position of the third through silicon via and the fourth through silicon via formed in the interposer layer may be determined by a method similar to the method of determining the positions of the first through silicon via and the second through silicon via formed in the semiconductor chip. have. In this case, the third through silicon via may be part of the first clock path 681 and the fourth through silicon via may be part of the second clock path 682.

The forming of the first through silicon via and the second through silicon via in the semiconductor chip may include forming the first through silicon via and the first through silicon via, respectively. A second through silicon via is formed. In this case, the first through silicon via and the second through silicon via may be formed based on the determined positions of the first through silicon via and the second through silicon via.

The forming of the interposer layer on the semiconductor chip may be performed by stacking the interposer layer on the semiconductor chip on which the first and second through silicon vias are formed. In this case, the interposer layer may comprise a silicon interposer.

The forming of the third through silicon via connected to the first through silicon via and the fourth through silicon via connected to the second through silicon via in the interposer layer may include: The third through silicon via and the fourth through silicon via may be formed based on the determined positions of the third through silicon via and the fourth through silicon via. In this case, the third through silicon via may be connected to the first through silicon via to form a first clock path 681, and the fourth through silicon via may be connected to the second through silicon via to form a second Clock path 682 may be formed.

The forming of a wiring path connecting the third through silicon via and the fourth through silicon via to the interposer layer may include forming the third through silicon via and the fourth through silicon via on the interposer layer. It can be carried out by a method for forming a metal wiring layer. Bumpers or pads may be formed on the third through silicon vias and the fourth through silicon vias, and the bumps or pads may be connected to a metal wiring layer. The first clock path 681 and the second clock path 682 are connected through the above process.

In one embodiment, the method of forming a tree clock distribution path of the three-dimensional integrated circuit, after forming a wiring path connecting the third through silicon via and the fourth through silicon via on the interposer layer, The method may further include forming another semiconductor chip and interposer layer including at least one through silicon via.

The above process is repeatedly performed to form a tree clock distribution path and a three-dimensional integrated circuit including the same.

In example embodiments, the method of forming the tree clock distribution path of the 3D integrated circuit may further include forming a terminal wiring path connecting the clock terminal of the at least one semiconductor chip and the second clock path. .

According to another aspect of the present invention, there is provided a method of forming a tree clock distribution path of a three-dimensional integrated circuit, including determining a location of a first clock path and a second clock path, and determining the location of the first clock path and the second clock path. Determining a wiring path connecting the first clock path and the second clock path based on a position; at least one semiconductor chip based on the determined first clock path, a position of the second clock path, and a wiring path; Stacking at least one or more interposer layers and at least one wiring layer, a via hole penetrating the stacked semiconductor chips, interposer layers and wiring layers based on the determined position of the first clock path and the second clock path And forming a through silicon via by filling a conductive material in the formed via hole. .

Unlike forming through silicon vias individually for each semiconductor chip or interposer layer to form a tree clock distribution path, the feature of the method is that at least one through silicon vias penetrating through at least one semiconductor chip or interposer layer at a time To form. Therefore, first, the positions of the first clock path and the second clock path are determined based on the structure of the 3D integrated circuit, and the wiring path connecting the first clock path and the second clock path is determined based thereon. After determining the wiring path, the semiconductor chip, the interposer layer, and the wiring layer are stacked. The wiring pattern of the wiring layer is formed based on the wiring path. A via hole penetrates the stacked semiconductor chip, the interposer layer, and the wiring layer. The via hole is filled with a conductive material constituting the through silicon via.

According to an embodiment, when the number of the semiconductor chips is three or more, at least one or more third clock paths 682 and 683 may be needed as illustrated in FIG. 6. In this case, a wiring layer for connecting the at least one third clock path 682 and 683 and the second clock path 682 may be formed. After all of the semiconductor chips, the interposer layers, and the wiring layer are stacked, the vias penetrate through all of the first to third semiconductor chips 611, 612, and 613 and the first to third interposer layers 621, 622, and 623. Holes may be formed, and a third clock path 683 may be formed by filling a conductive material in the via holes formed in the third interposer layer 623 and the third semiconductor chip 613. Via holes formed in the second interposer layer 622 and the second semiconductor chip 612 to electrically insulate the two third clock paths 683 after the third clock path 683 is formed. The insulating material can be filled. After the insulating material is filled, the third clock path 682 may be formed by filling a conductive material in the via holes formed in the first interposer layer 621 and the first semiconductor chip 611. Through the above process, a plurality of third clock paths 682 and 683 may be formed.

7 is a cross-sectional view illustrating a clock signal distributed to clock terminals of each semiconductor layer through a tree clock distribution path according to an embodiment of the present invention.

Referring to FIG. 7, the flow of the clock signal CLOCK is illustrated by an arrow including a dotted line. The clock signal CLOCK generated by the clock generator 710 is transferred to the wiring layer 701 of the silicon interposer 703 through the through silicon vias 715. Bumps 717 may be formed between the wiring layer 701 and the silicon vias 715, and an underfill layer 718 may be formed around the wiring layer 701 and the silicon vias 715.

FIG. 8 is a diagram illustrating a structure of a second interposer layer of FIG. 6.

8 and 6, the second interposer layer 622 includes a first clock path 681, four second clock paths 682a, 682b, 682c, and 682d and a first wiring path 691. Is formed. The clock signal output from the clock generator is transferred to the first interposer layer 622 through the first clock path 681 of the tree clock distribution path. The clock signal is transferred to four second clock paths 682a, 682b, 682c, and 682d through the first wiring path 691. Clock signals transmitted to the second clock paths 682a, 682b, 682c, and 682d are branched and delivered to the first interposer layer and the third interposer layer, respectively. Referring to FIG. 6, a first interposer layer 621 is positioned above the second interposer layer 622, and a third interposer layer 623 is positioned below the second interposer layer 622. have. Accordingly, the first interposer layer 621 and the third interposer layer 623 have the same structure, and the structure of the first interposer layer 621 will be described later with reference to FIG. 9. An illustration of the structure of the third interposer layer 623 is omitted.

FIG. 9 is a diagram illustrating a structure of a first interposer layer of FIG. 6.

9 and 6 together, the first interposer layer 621 has four second clock paths 682a, 682b, 682c, 682d, eight third clock paths 684a, 684b, 684c, 684d, 684e, 684f, 684g, 684h and four second wiring paths 692 are formed. Clock signals transferred to the first interposer layer 621 through the second clock paths 682a, 682b, 682c, and 682d are eight third clock paths 684a and 684b through the second wiring path 692. , 684c, 684d, 684e, 684f, 684g, 684h). The clock signal transferred to the third clock paths 684a, 684b, 684c, 684d, 684e, 684f, 684g, and 684h is branched to the first semiconductor chip 611 and the second semiconductor chip 612.

The clock signal is transferred to the third interposer layer 623 by the same process as described with respect to the first interposer layer 621.

FIG. 10 is a diagram illustrating a structure of the first semiconductor chip of FIG. 6.

10 and 6, the first semiconductor chip 611 may include eight third clock paths 684a, 684b, 684c, 684d, 684e, 684f, 684g, and 684h, and 16 clock terminals 801. ) And eight terminal wirings are formed. Clock signals transferred to the first semiconductor chip 611 through the third clock paths 684a, 684b, 684c, 684d, 684e, 684f, 684g, and 684h are transferred to the clock terminals 801 through terminal wires. .

The clock signal is transferred to the clock terminal through the same process as that described for the first semiconductor chip 611 for the second semiconductor chip 612 to the fourth semiconductor chip 614.

FIG. 11 is a perspective view illustrating a structure of a first interposer layer of FIG. 8, a second interposer layer of FIG. 9, and a semiconductor chip of FIG. 10.

As illustrated in FIGS. 11 and 6, the clock signal transmitted from the clock generator is transferred to the second interposer 622 through the first clock path 681, and the first wiring path 691 and the second wire. Passed through the clock paths 682a, 682b, 682c, and 682d to the first interposer 621, the second wiring path 692 and the third clock paths 684a, 684b, 684c, 684d, 684e, 684f. , 684g and 684h are transferred to the first semiconductor chip 611. In addition, clock signals transmitted through the third clock paths 684a, 684b, 684c, 684d, 684e, 684f, 684g, and 684h are transferred to the clock terminals 801 through terminal wires on the first semiconductor chip 611. do.

The tree clock distribution path in the case where the semiconductor chips including 16 clock terminals are stacked has been described above, but this is merely an example. Various decisions can be made as required. Even in such a case, a tree clock distribution path according to an embodiment of the present invention may be used to minimize skew and jitter of the clock signal.

12 is a graph illustrating a skew of a three dimensional integrated circuit system including a single clock distribution path and four semiconductor layers.

To obtain the results of FIGS. 12-15, through-silicon vias of 110 μm in height were used, and the thicknesses of the plurality of stacked semiconductor chips and interposer layers were all simulated in the same environment.

Referring to FIG. 12, a simulation result of a voltage value of a clock signal reaching a clock terminal of each semiconductor chip in a three-dimensional integrated circuit system including four semiconductor chips is illustrated. The clock signal has a minimum of 0V and a maximum of 1.8V. 12 shows only a part of the clock signal that changes periodically. That is, the graph of FIG. 12 shows a part of the rising period of the clock signal.

In FIG. 12, the clock generated from the clock generator reaches the first chip CASE 1, the second chip CASE 2, the third chip CASE 3, and the fourth chip CASE 4 through a single clock distribution path. A clock signal is shown. That is, four semiconductor chips were stacked one after the other without interposer layers being used. Unlike in FIGS. 2 to 4, the first chip CASE 1 is a chip stacked on the lowermost part of the four semiconductor chips. That is, a graph in which the first chip CASE 1, the second chip CASE 2, the third chip CASE 3, and the fourth chip CASE 4 are stacked in order from the substrate side is illustrated in FIG. 12. . Since the first chip CASE 1 is located at the bottom of the four semiconductor chips and is closest to the clock generator, the clock signal reaches the first chip CASE 1 first. Subsequently, the clock signals reach the second chip CASE 2 and the third chip CASE 3 in sequence, and the fourth chip CASE 4 is located farthest from the clock generator, so that the fourth chip CASE 4 The clock signal arrives last. The skew, which is the difference in the time that the clock signal of each semiconductor chip reaches the 0.9V point in the clock rising period, becomes 4.1 pico seconds.

FIG. 13 is a graph illustrating an eye diagram of a three dimensional integrated circuit system including a single clock distribution path and four semiconductor layers.

The eye diagram represents a cumulative or superimposed voltage waveform of an electrical signal. The output waveform looks like an eye when viewed with a signal waveform analyzer.

Referring to FIG. 13, timing jitter for a clock signal when using a single clock distribution path is shown. In a voltage waveform of overlapping clock signals, a single clock distribution path is used to measure the width between the fastest time to reach 0.9V at the maximum value and the latest time to reach 0.9V at the minimum value. Case 14.1 Pico second timing jitter occurs.

14 is a graph illustrating a skew of a three-dimensional integrated circuit system according to an embodiment of the present invention.

Referring to FIG. 14, a simulation result of a voltage value of a clock signal reaching a clock terminal of each semiconductor chip in a three-dimensional integrated circuit system including four semiconductor chips is illustrated. The clock signal has a minimum of 0V and a maximum of 1.8V. Fig. 14 shows only a part of the clock signal that changes periodically. That is, the graph of FIG. 14 shows a part of the rising period of the clock signal.

In FIG. 14, a clock generated from a clock generator reaches a first chip CASE 1, a second chip CASE 2, a third chip CASE 3, and a fourth chip CASE 4 through a tree clock distribution path. A clock signal is shown. When the clock signal is transferred to each of the semiconductor chips through the tree clock distribution path, the skew may be minimized because the tree clock distribution path delivers the clock signal through the path of the same distance even though the positions of the semiconductor chips are different. That is, as shown in FIG. 14, a skew, which is a difference in time when the clock signal of each semiconductor chip reaches a 0.9V point in a clock rising period, becomes 0 pico sec. Since the result is a simulation result, different results may be obtained when an actual three-dimensional integrated circuit system is implemented. In this case, it may be predicted that less skew will be achieved than when the clock is transmitted through a single clock distribution path.

FIG. 15 is a graph illustrating an eye diagram of a 3D integrated circuit system according to an exemplary embodiment.

Referring to FIG. 15, timing jitter of a clock signal when a tree clock distribution path is used according to an embodiment of the present invention is illustrated. Using a tree clock distribution path, timing jitter of 9.4 picoseconds occurs in a three-dimensional integrated circuit system with four semiconductor layers. As described above, the timing jitter is reduced to 9.4 picoseconds when the tree clock distribution path according to an embodiment of the present invention is used, whereas the timing jitter of 14.1 pico seconds occurs when using a single clock distribution path. It can be seen that the system performance is also improved.

In the tree clock distribution path 3D integrated circuit and the power pin arrangement method of the 3D integrated circuit according to the embodiments of the present invention, since the inductance of the power pin is effectively reduced, the influence of the power supply noise may be reduced. It can be applied to the design field of a circuit.

As described above, the present invention has been described with reference to a preferred embodiment of the present invention, but those skilled in the art may vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be understood that modifications and changes can be made.

Claims (16)

3. A three-dimensional integrated circuit comprising a tree clock distribution path for carrying a clock signal, a substrate, at least one semiconductor chip formed on the substrate, and at least one interposer layers positioned between the semiconductor chips, wherein the tree clock The distribution path is
A first clock path composed of at least one first through silicon vias penetrating the semiconductor chips and the interposer layers to transfer the clock signal in a first direction, the direction from the substrate side to the semiconductor chip side;
A second clock path composed of at least one second through silicon via penetrating the semiconductor chips and the interposer layers to transfer the clock signal in a second direction opposite to the first direction and in the first direction ; And
And a wiring path connecting the first clock path and the second clock path. The method of claim 1, wherein the tree clock distribution path further comprises a terminal wiring path connecting the second clock path and a clock terminal of the at least one semiconductor chip to transfer the clock signal to the clock terminal. 3D integrated circuit. Claim 3 has been abandoned due to the setting registration fee. The 3D integrated circuit of claim 1, wherein the at least one semiconductor chip has the same thickness. Claim 4 has been abandoned due to the setting registration fee. 4. The three-dimensional integrated circuit of claim 3, wherein the thickness of the interposer layers is the same as the thickness of the semiconductor chips. Claim 5 was abandoned upon payment of a set-up fee. The 3D integrated circuit of claim 1, wherein the interposer layer is a silicon interposer. Claim 6 has been abandoned due to the setting registration fee. The three-dimensional integrated circuit of claim 1, wherein the material forming the first through silicon vias and the second through silicon vias is any one of copper, aluminum, tungsten, and polysilicon. delete delete delete delete delete delete delete delete A system comprising a three-dimensional integrated circuit, a central processing unit, and at least one input / output device formed on a substrate, wherein a plurality of semiconductor chips and interposer layers are alternately stacked and distribute clock signals by a tree clock distribution path. ,
The tree clock distribution path includes a first clock path passing through the plurality of semiconductor chips and interposer layers, a second clock path, and a wiring path connecting the first clock path and the second clock path;
The first clock path is comprised of at least one first through silicon vias passing through the semiconductor chips and the interposer layers to transfer the clock signal in a first direction from the substrate side towards the semiconductor chips side,
The second clock path is comprised of at least one second through silicon via that penetrates the semiconductor chips and the interposer layers to direct the clock signal in a second direction and the first direction opposite to the first direction. Conveying system. Claim 16 has been abandoned due to the setting registration fee. The system of claim 15, wherein the plurality of semiconductor chips are memory chips.

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