KR101182504B1 - Array substrate for LCD and the fabrication method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device capable of improving image quality while reducing the number of data lines and a manufacturing method thereof.

According to the present invention, two adjacent pixels share one data line, and the capacitor capacity of the entire pixel is kept constant corresponding to misalignment of a mask for forming the data line.

Therefore, even when the source electrode and the drain electrode pattern are distorted due to misalignment of the mask for forming the data line, the capacitor capacity of the entire pixel can be kept constant, so that the image quality of each pixel of the liquid crystal display device is uniform and the image quality of the entire surface of the liquid crystal panel. Can improve.

Capacitors, Common Data Lines

Description

Array substrate for LCD and manufacturing method thereof

1 is a plan view showing a pixel structure of a conventional liquid crystal display device.

FIG. 2 is an equivalent circuit diagram of a pixel structure of the liquid crystal display of FIG. 1. FIG.

3 is a plan view showing a portion of an array substrate for a liquid crystal display according to an embodiment of the present invention.

4A is an enlarged view of a thin film transistor of an array substrate for a liquid crystal display according to the present invention.

4B is an enlarged view of a thin film transistor formed by shifting a pattern of a source electrode and a drain electrode upward in an array substrate for a liquid crystal display according to the present invention.

<Description of Signs for Main Parts of the Present Invention>

111a, 111b: first and second gate lines 112: common data line

113a and 113b: pixel electrodes 116a and 116b: semiconductor layer

121a and 121b: gate electrode 122a and 122b: source electrode

124a and 124b: drain electrode 131a and 131b: auxiliary gate electrode

134a and 134b: auxiliary drain electrodes

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device capable of improving image quality while reducing the number of data lines and a manufacturing method thereof.

Recently, as the information society develops, the demand for display devices is increasing in various forms, and in recent years, the liquid crystal display device (LCD), plasma display panel (PDP), electro luminescent display (ELD), and VFD ( Various flat panel display devices such as Vacuum Fluorescent Display have been studied.

Among them, LCD is the most used, replacing the CRT (Cathode Ray Tube) for the use of mobile image display devices because of its excellent image quality, light weight, thinness, and low power consumption. In addition to the purpose, various developments are being made for a television and a computer monitor for receiving and displaying broadcast signals.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the arrangement of molecules can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light polarized by optical anisotropy may be arbitrarily modulated to express image information.

Currently, active matrix liquid crystal displays (AM-LCDs) in which thin film transistors and pixel electrodes connected to the thin film transistors are arranged in a matrix manner are attracting the most attention because of their excellent resolution and ability to implement video.

Hereinafter, a pixel structure of a conventional liquid crystal display device configured as described above will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a pixel structure of a conventional liquid crystal display.

As shown in FIG. 1, the liquid crystal display according to the related art includes a plurality of gate lines 11 and a plurality of data lines crossing the gate lines 11 and defining a pixel region P at regular intervals. 12) is formed.

A thin film transistor TFT is formed at an intersection point of each of the gate lines 11 and each data line 12, and the thin film transistor TFT includes a gate electrode 21 that protrudes from the gate line 11, and A semiconductor layer 16 formed on the gate electrode 21 with a gate insulating layer (not shown) therebetween, and a source electrode 22 formed on the semiconductor layer 16 and protruding from the data line 12. ) And a drain electrode 24 spaced apart from the source electrode 22 by a predetermined interval, and a pixel electrode 13 connected to the drain electrode 24 is formed in the pixel region P.

FIG. 2 is an equivalent circuit diagram of a pixel structure of the liquid crystal display of FIG. 1.

As shown in FIG. 2, the intersections of the plurality of gate lines GL1, GL2,..., GLn-1, GLn and the plurality of data lines DL1, DL2, DL3,. A thin film transistor TFT is provided and is connected to the drain electrode of the thin film transistor to form a liquid crystal capacitor C _LC . The liquid crystal capacitor C _LC is not a separate device, but a pixel electrode on the lower substrate and a common electrode on the upper substrate as first and second electrodes, and a liquid crystal formed between the upper and lower substrates as a dielectric. At this time, it is the role of the liquid crystal capacitor C _{LC to} maintain a data voltage value charged in each pixel electrode for a predetermined time.

Although not shown in the drawing, a separate storage capacitor Cst is formed between the pixel electrode and the common electrode to adjust the charging time of the liquid crystal.

Referring to the operation of the conventional liquid crystal display, the driving voltage (pulse signal) is sequentially applied to each of the gate lines GL1, GL2,..., GLn-1, GLm. The thin film transistor TFT connected to GL2, ..., GLm-1, GLm is turned on, during which the data voltage applied to each data line DL1, DL2, DL3, ..., DLn is applied to the pixel electrode. Is applied to charge the data voltage. At this time, the data voltage is charged in one frame period for each pixel electrode 13 and maintained until the next signal is applied.

That is, the gate voltage is sequentially applied to each gate line every one frame time, and in the selected pixel to which the gate voltage is applied, the voltage of the gate electrode of the thin film transistor connected to the gate line becomes high, and the thin film transistor is turned on. In this case, the liquid crystal driving voltage is applied to the liquid crystal from the data line via the drain and the source of the thin film transistor to charge the pixel capacitance combined with the liquid crystal capacitance and the auxiliary capacitance. By repeating this operation, a voltage corresponding to the video signal is applied to the pixel capacitance on the front panel for each frame time.

Recently, the resolution of such an active matrix liquid crystal display device has been considerably increased. Accordingly, in the case of a high resolution liquid crystal display device, the number of gate lines and data lines constituting pixels increases.

Therefore, a plurality of gate driver ICs and data drive ICs corresponding to the number of the gate lines and the data lines must be mounted.

However, in the case of XGA (1024 × 768) class, since 3 sub pixels of data line 3072 (R, G, B constitute one pixel, 384 pins are required to correspond to 1024 × 3) and 768 gate lines. Data Driver IC with 8 Gates with 256 Pins

Three Iber ICs are required.

Here, since the data driver IC is more expensive than the gate driver IC, the data driver IC consumes about 100 mW, and the gate driver IC consumes about 20 mW, so that the data driver IC consumes more data than the gate driver IC. The manufacturing cost and power consumption are determined by the driver IC.

In addition, when a high resolution is realized in a panel of the same size, the width of each pixel becomes smaller, and as the ultra-miniaturization progresses, the driving circuit of the liquid crystal display device and the liquid crystal panel are connected in order to mount a drive IC corresponding to the pixel structure. This is getting harder.

In order to solve this problem, research on an array structure for reducing the number of data lines has been actively conducted.

The present invention provides an array substrate for a liquid crystal display device and a manufacturing method thereof, in which two adjacent pixels share one data line and maintain a constant capacitor capacity of the entire pixel in response to misalignment of a mask for forming the data line. The purpose is to provide a method.

In order to achieve the above object, an array substrate for a liquid crystal display device according to the present invention comprises: first and second gate lines formed adjacent to each other; A common data line crossing the first and second gate lines to define first and second pixels; A gate electrode formed to protrude from the first and second gate lines and an auxiliary gate electrode extending from the gate electrode; A semiconductor layer formed on the gate electrode; A source electrode protruding from the common data line to the gate electrode, a drain electrode spaced apart from the source electrode at a predetermined interval and overlapping the gate electrode; An auxiliary drain electrode extending from the drain electrode and overlapping the auxiliary gate electrode; And a pixel electrode connected to the drain electrode and formed in the first and second pixels, respectively.

In addition, in order to achieve the above object, a method of manufacturing an array substrate for a liquid crystal display device according to the present invention includes a gate line, a gate electrode protruding from the gate line, and an auxiliary gate electrode extending from the gate electrode. Forming a; Forming a semiconductor layer on the gate electrode; Forming a data line crossing the gate line to define a pixel; A source electrode protruding from the data line to the gate electrode, a drain electrode spaced apart from the source electrode by a predetermined interval, and extending from the drain electrode and the drain electrode to form an auxiliary drain electrode overlapping the auxiliary gate electrode; Making a step; And forming a pixel electrode in the pixel by connecting to the drain electrode.

The data line jointly applies a data signal to a neighboring pixel.

A capacitor is formed in an overlapping region of the gate electrode and the drain electrode.

An auxiliary capacitor may be formed in an overlapping region of the auxiliary gate electrode and the auxiliary drain electrode.

The sum of the capacities of the capacitor and the auxiliary capacitor may be kept constant.

The drain electrode overlaps the gate electrode in a first direction in a second direction, and the auxiliary drain electrode overlaps the auxiliary gate electrode in a second direction in a first direction.

Hereinafter, a liquid crystal display device will be described with reference to the accompanying drawings.

3 is a plan view showing a portion of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

As illustrated in FIG. 3, an array substrate for a liquid crystal display according to the present invention has a structure in which pixels disposed adjacent to left and right share a data line and time-dividing data to each pixel.

That is, the array substrate for a liquid crystal display according to the present invention includes the first and second gate lines 111a and 111b and the first and second gate lines provided to each of the neighboring first and second pixels P1 and P2. A common data line 112 that vertically intersects 111a and 111b and supplies a time-divided data signal to the first and second pixels P1 and P2 is formed, and the first and second gate lines 111a and 111b are formed. First and second thin film transistors TFT1 and TFT2 are formed at an intersection point of the data line 112.

The first and second gate lines 111a and 111b are spaced apart from each other with the pixel interposed therebetween, and the first and second thin film transistors TFT1 and TFT2 are alternately symmetrical with the common data line 112 interposed therebetween. Is formed.

The first thin film transistor TFT1 includes a gate electrode 121a protruding from the first gate line 111a, a semiconductor layer 116a formed on the gate electrode 121a, and the semiconductor layer 116a. And a source electrode 122a and a drain electrode 124a in contact with a predetermined region on the substrate, and a pixel electrode 113a formed in the first pixel P1 in contact with the drain electrode 124a.

The first thin film transistor TFT1 forms a first gate-source capacitor Cgs1 between the gate electrode 121a and the drain electrode 124a and extends from the gate electrode 121a. A first auxiliary gate-source capacitor Cx1 is formed between the gate electrode 131a and the auxiliary drain electrode 134a which extends over the auxiliary gate electrode 131a.

At this time, the arrangement of the gate electrode 121a and the drain electrode 124a forming the first gate-source capacitor Cgs1 and the auxiliary gate electrode 131a forming the first auxiliary gate-source capacitor Cx1 are formed. ) And the auxiliary drain electrode 134a are opposite to each other.

For example, when the drain electrode 124a forming the first gate-source capacitor Cgs1 overlaps the gate electrode 121a in a first direction and a second direction, the first auxiliary gate-source capacitor The auxiliary drain electrode 134a forming the Cx1 overlaps the auxiliary gate electrode 131a in the first direction in the second direction.

Therefore, during the photo process for forming the source electrode and the drain electrode pattern, a case in which the photo mask is twisted so that the source electrode and the drain electrode pattern are twisted up, down, left, and right may occur, and thus, the first thin film The increase or decrease of the value of the first gate-source capacitor Cgs1 of the transistor TFT1 may be compensated by the first auxiliary gate-source capacitor Cx1 proposed in the present invention.

Meanwhile, in the neighboring second pixel P2 which shares the common data line 112 with the first pixel P1, the second thin film transistor TFT2 protrudes from the second gate line 111b. A gate electrode 121b, a semiconductor layer 116b formed on the gate electrode 121b, a source electrode 122b and a drain electrode 124b in contact with a predetermined region on the semiconductor layer 116b, and the drain And a pixel electrode 113b formed in the first pixel P1 in contact with the electrode 124b.

Here, the second thin film transistor TFT2 forms a second gate-source capacitor Cgs2 between the gate electrode 121b and the drain electrode 124b, and extends from the gate electrode 121b. A second auxiliary gate-source capacitor Cx2 is formed between the gate electrode Cx2 and the auxiliary drain electrode 134b extending over the auxiliary gate electrode 131b.

At this time, the arrangement of the gate electrode 121b and the drain electrode 124b forming the second gate-source capacitor Cgs2 and the auxiliary gate electrode 131b forming the second auxiliary gate-source capacitor Cx2 are formed. ) And the auxiliary drain electrode 134b are opposed to each other.

For example, if the drain electrode 124b forming the second gate-source capacitor Cgs2 overlaps the gate electrode 121b in a first direction in a second direction, the second auxiliary gate-source capacitor The auxiliary drain electrode 134b forming Cx2 overlaps the auxiliary gate electrode 131b in the first direction and the second direction.

Therefore, in the photo process for forming the source electrode and the drain electrode pattern, a photo mask may be distorted so that the source electrode and the drain electrode pattern may be displaced up, down, left, and right, and thus, the second thin film. The increase and decrease of the value of the second gate-source capacitor Cgs2 of the transistor TFT2 may be compensated by the second auxiliary gate-source capacitor Cx2 proposed in the present invention.

Therefore, in the first and second pixels P1 and P2 using the common data line 112, patterns of the source electrodes 122a and 122b and the drain electrodes 124a and 124b branched from the common data line 112 may be formed. Values of the first and second gate-source capacitors Cgs1 and Cgs2 formed in the first and second thin film transistors TFT1 and TFT2 when shifted in one of the up, down, left, and right directions, respectively. Since is compensated by the first and second auxiliary gate-source capacitors Cx1 and Cx2, the overall gate-source capacitor capacity is uniform in the first and second pixels P1 and P2, and quality defects can be prevented.

4A is an enlarged view of a thin film transistor of an array substrate for a liquid crystal display according to the present invention, and FIG. 4B is a thin film formed by shifting a pattern of a source electrode and a drain electrode upward in an array substrate for a liquid crystal display according to the present invention. An enlarged view of a transistor.

As shown in FIGS. 4A and 4B, the gate electrode 121a formed in the thin film transistor TFT1, the auxiliary gate electrode 131a formed by the predetermined extension of the gate electrode 121a, and the gate electrode 121a are disposed on the gate electrode 121a. The formed source electrode 122a and the drain electrode 124a which are patterned with the same material as the source electrode 122a and spaced apart from each other by a predetermined interval are formed, and the auxiliary drain electrode 124a formed so as to overlap the auxiliary gate electrode 121a. .

The drain electrode 124a and the auxiliary drain electrode 134a are overlapped with the gate electrode 121a and the auxiliary gate electrode 121a in a direction symmetrical with each other, and the gate electrode 121a and the drain electrode 124a may be overlapped with each other. A gate-source capacitor Cgs1 is formed at an overlapping portion, and an auxiliary gate-source capacitor Cx1 is formed at an overlapping portion of the auxiliary gate electrode 131a and the auxiliary drain electrode 134a.

As shown in FIG. 4B, when the patterns of the source electrode 122a and the drain electrode 124a are shifted upward, the value of the gate-source capacitor Cgs1 decreases, and the auxiliary gate-source capacitor The value of (Cx1) is increased.

Therefore, when the reduction capacity of the gate-source capacitor Cgs1 and the increase capacity of the auxiliary gate-source capacitor Cx1 are substantially matched, the overall capacitor capacity of the thin film transistor does not change even though the photomask is distorted. Therefore, the image quality of each pixel is uniform and the image quality of the entire liquid crystal panel is improved.

As mentioned above, the present invention has been described in detail with reference to specific embodiments, which are intended to specifically describe the present invention, and the array substrate for a liquid crystal display device and a method of manufacturing the same according to the present invention are not limited thereto. It is apparent that modifications and improvements are possible by those skilled in the art.

According to the present invention, since two adjacent pixels share one data line in the liquid crystal display, the number of data lines of the liquid crystal panel can be reduced, thereby increasing the resolution.

In addition, in the present invention, even when the source electrode and the drain electrode pattern are distorted due to misalignment of the mask for forming the data line, the capacitor capacity of the entire pixel can be kept constant, so that the image quality of each pixel is uniform and the image quality of the entire liquid crystal panel is uniform. This has the effect of being improved.

Claims (12)

First and second gate lines; A common data line crossing the first and second gate lines to define first and second pixels; A gate electrode branched from the first and second gate lines, and an auxiliary gate electrode extending from the gate electrode; A semiconductor layer formed on the gate electrode; A source electrode branched from the common data line to the gate electrode; A drain electrode facing the source electrode and overlapping the gate electrode; An auxiliary drain electrode extending from the drain electrode and overlapping the auxiliary gate electrode and protruding in a direction opposite to the drain electrode; A pixel electrode connected to the drain electrode and formed in the first and second pixels, respectively; A capacitor is formed in an overlapping region of the gate electrode and the drain electrode, an auxiliary capacitor is formed in an overlapping region of the auxiliary gate electrode and the auxiliary drain electrode, and the sum of the capacitances of the capacitor and the auxiliary capacitor is the same for each pixel. An array substrate for a liquid crystal display device, which is held. delete delete The method of claim 1, And the drain electrode overlaps the gate electrode in a first direction in a second direction and the auxiliary drain electrode overlaps the auxiliary gate electrode in a second direction in a first direction. The method of claim 1, And the source electrode is a U-shaped structure. delete Forming a gate line, a gate electrode branched from the gate line, and an auxiliary gate electrode extending from the gate electrode on a substrate; Forming a semiconductor layer on the gate electrode; Forming a data line crossing the gate line to separate pixel areas; Forming a source electrode branched from the data line to the gate electrode; Forming a drain electrode facing the source electrode and overlapping the gate electrode and an auxiliary drain electrode extending from the drain electrode and overlapping the auxiliary gate electrode and protruding in a direction opposite to the drain electrode; Forming a pixel electrode in the pixel by connecting to the drain electrode; A capacitor is formed in an overlapping region of the gate electrode and the drain electrode, an auxiliary capacitor is formed in an overlapping region of the auxiliary gate electrode and the auxiliary drain electrode, and the sum of the capacitances of the capacitor and the auxiliary capacitor is the same for each pixel. It is hold | maintained, The manufacturing method of the array substrate for liquid crystal display devices. According to claim 7, And said data line jointly applies a data signal to a neighboring pixel. delete delete delete 8. The method of claim 7, Fabrication of an array substrate for a liquid crystal display device, characterized in that the drain electrode overlaps the gate electrode in a first direction in a second direction and the auxiliary drain electrode overlaps the auxiliary gate electrode in a second direction in a first direction. Way.

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