KR101179460B1 - Semiconductor device and method for fabricating the same - Google Patents

Abstract

The present invention is to provide a semiconductor device and a method of manufacturing the same that can prevent the degradation of the GIDL characteristics due to the work function difference between the gate electrode and the junction region, the present invention for this purpose is a gate including a conductive film having an intermediate work function electrode; And a junction region having a hetero-doping structure overlapping the gate electrode and having a first conductive impurity region and a second conductive impurity region sequentially disposed.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a semiconductor device and a method of manufacturing the same, which can improve gate induced drain leakage (GIDL) characteristics.

As the degree of integration of a semiconductor memory device, for example, DRAM, increases, parasitic capacitance between word lines and bit lines increases. As a result, a sensing margin for cell operation is reduced, resulting in a deterioration of DRAM operating characteristics. In order to prevent deterioration of operating characteristics due to parasitic capacitance between word lines and bit lines, buried gates (BGs) for embedding gate electrodes are introduced in the substrate.

1 is a cross-sectional view of a semiconductor device having a buried gate according to the prior art.

As illustrated in FIG. 1, the active region 13 is defined by the device isolation layer 12 formed on the substrate 11, and the buried gate is formed in the active region 13 and the junction region is formed in both substrates 11. Junction Region (JR) is formed. The junction region JR is composed of an impurity region 18 doped with an impurity on a substrate. The buried gate includes a trench 14 formed in the substrate 11, a gate insulating film 15 formed on the surface of the trench 14, a gate electrode 16 partially filling the trench 14 on the gate insulating film 15, and The sealing film 17 fills the remaining trenches 14 on the gate electrode 16.

In the prior art, the buried gate forms the gate electrode 16 with a metal film in order to reduce the resistance of the gate electrode 16 which is a structural disadvantage. In this case, the gate electrode 16 is formed of a metal film having a mid gap work function that can be applied to both NMOS and PMOS for cost-effective process development.

However, the gate electrode 16 of the buried gate is formed of a metal film having an intermediate work function as compared with the case where the gate electrode 16 is formed of an N-type metal film (NMOS case) or a P-type metal film (PMOS case). In this case, the GIDL characteristic is rapidly deteriorated due to the difference in the work function between the gate electrode 16 and the junction region JR.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems of the prior art, and provides a semiconductor device and a method for manufacturing the same, which can prevent deterioration of GIDL characteristics due to a difference in work function between a gate electrode and a junction region. have.

According to an aspect of the present invention, there is provided a gate electrode including a conductive film having an intermediate work function; And a junction region having a hetero-doping structure overlapping the gate electrode and having a first conductive impurity region and a second conductive impurity region sequentially disposed.

According to another aspect of the present invention, there is provided a buried gate formed in a substrate; First impurity regions of a first conductivity type formed on both sides of the buried gate; And a second impurity region of a second conductive type spaced apart from the buried gate by a predetermined distance and formed in the first impurity region.

According to another aspect of the present invention for achieving the above object is a step of forming a buried gate in the substrate; Forming a first impurity region by implanting impurities of a first conductivity type into the substrate on both sides of the buried gate; And forming a second impurity region by ion implanting a second conductive type impurity into a portion of the first impurity region so as to be spaced apart from the buried gate by a predetermined distance.

In addition, the method of manufacturing a semiconductor device of the present invention may further include forming an amorphous region by ion implanting a diffusion preventing element in a region where the second impurity region is to be formed before forming the second impurity region. .

The present invention based on the above-described problem solving means, by providing a junction region consisting of impurity regions having a hetero-doping structure, it is possible to prevent the degradation of the GIDL characteristics due to the work function difference between the gate electrode and the junction region There is.

1 is a cross-sectional view showing a semiconductor device having a buried gate according to the prior art.
2A and 2B are cross-sectional views illustrating a semiconductor device having a buried gate according to an embodiment of the present invention.
Figure 3 is a cross-sectional view showing a junction region consisting of impurity regions having a hetero-doping structure according to an embodiment of the present invention.
4A to 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device having a buried gate according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The present invention, which will be described later, provides a semiconductor device capable of preventing degradation of GIDL characteristics due to a work function difference between a gate electrode and a junction region in a semiconductor device having a buried gate, and a method of manufacturing the same. Here, GIDL means that a leakage current is generated by an electric field generated by a work function difference between the gate electrode and the junction region (that is, the source region and the drain region). As the work function difference between the gate electrode and the junction region increases, the magnitude of the electric field generated between them increases, causing the GIDL characteristics to deteriorate (that is, the leakage current increases), and in general, a high voltage is applied to the source region. Occurs in the drain region.

In case of forming a gate electrode with a metal film having a mid gap work function that can be applied to both NMOS and PMOS for efficient CMOS development in terms of manufacturing cost and process of a semiconductor device having a buried gate. As a result, an electric field is generated due to a work function difference between the gate electrode and the junction region. Therefore, the present invention is intended to mitigate the electric field generated by the work function difference between the gate electrode and the junction region to prevent deterioration of GIDL characteristics. For reference, the metal film having an intermediate work function means a metal material having a work function of about 4.5 eV.

Hereinafter, for convenience of description, an NMOS used as a DRAM cell transistor will be described. Therefore, the first conductive type and the second conductive type are complementary to each other, the first conductive type is N type, and the second conductive type is P type.

2A and 2B are cross-sectional views illustrating a semiconductor device having a buried gate according to an embodiment of the present invention. 2A illustrates a case where the drain region has a hetero doping structure, and FIG. 2B illustrates a case where both the source region and the drain region have a hetero doping structure.

As shown in FIGS. 2A and 2B, a semiconductor device according to an exemplary embodiment of the present inventive concept is formed on a substrate 31 to define an active region 33 and a substrate of an isolation region 32 and an active region 33. And a junction region (JR) formed in the buried gate 31 and partially overlapping the gate electrode 36 of the buried gate.

The buried gate includes a trench 34 formed in the substrate 31, a gate insulating film 35 formed on the surface of the trench 34, and a gate electrode 36 and a gate electrode partially filling the trench 34 on the gate insulating film 35. A sealing film 37 for filling the remaining trenches 34 on 36 is included. The gate electrode 36 may be a conductive film having an intermediate work function, for example, a tungsten film (W). For reference, the work function of tungsten is 4.5 eV.

The junction region JR includes an impurity region formed by doping impurities into the substrate 31. For example, as illustrated in FIG. 2A, the junction region (JR, source region) formed on the other side of the buried gate substrate 31 may include an N-type (ie, first conductive type) first impurity region 38. A junction region (JR, drain region) formed in the buried gate one side substrate 31 is formed in the first impurity region 38 and the first impurity region 38, and is formed of a P type (ie, a Two-conductive) second impurity region 39 may be included. That is, the junction region (JR, drain region) formed in the buried gate one side substrate 31 is the N-type first impurity region 38 / P-type second impurity region 39 in the horizontal direction parallel to the surface of the substrate 31. The / N type first impurity region 38 is formed of an impurity region having a hetero-doping structure in which the / N-type first impurity region 38 is sequentially arranged.

As another example, as shown in FIG. 2B, the junction region JR formed on one side of the buried gate and the other substrate 31 is formed in the first impurity region 38 and the first impurity region 38, and is buried. The second impurity region 39 may be spaced apart from the gate by a predetermined distance. That is, all of the junction regions JR formed on both sides of the buried gate are impurity regions having heterogeneous doping structures.

The second impurity region 39 formed in the first impurity region 38 in the junction region JR having an impurity region having a heterologous doping structure is such that the line width of the second impurity region 39 between processes is extended more than necessary. It may include a diffusion prevention element to prevent. The diffusion preventing element may include carbon.

In the semiconductor device according to the embodiment of the present invention having the above-described structure, since the junction region JR has a hetero-doping structure, the conductive film (or metal film) having the intermediate work function as the gate electrode 36 of the buried gate is formed. Even when using, the GIDL characteristic can be prevented from deteriorating. This will be described in more detail with reference to FIG. 3.

3 is a cross-sectional view showing a junction region composed of an impurity region having a heterologous doping structure according to an embodiment of the present invention, in which a junction region composed of impurity regions having a heterogeneous doping structure prevents degradation of GIDL characteristics. Figure is shown.

As shown in FIG. 3, an electric field is generated between the gate electrode 36 made of the conductive film having the intermediate work function and the N-type first impurity region 38 due to their work function difference. Specifically, when the first impurity region 38 is formed by ion implantation of phosphorus (P) or arsenic (As) on the silicon substrate, the first impurity region 38 has a work function of about 4.1 eV and is formed into a tungsten film. When the gate electrode 36 is formed, the gate electrode 36 has a work function of about 4.5 eV. At this time, an electric field is generated from the first impurity region 38 toward the gate electrode 36 due to the work function difference (about 0.4 eV) between the gate electrode 36 and the first impurity region 38. Hereinafter, the electric field generated in the first impurity region 38 in the direction of the gate electrode 36 is abbreviated as 'first electric field 100'.

A first depletion region, ie, a PN junction, is formed between the first impurity region 38 and the second impurity region 39 disposed between the gate electrode 36 and the P-type second impurity region 39. do. At this time, an electric field is generated in the first depletion region from the first impurity region 38 to the second impurity region 39. Hereinafter, the electric field generated in the direction of the second impurity region 39 in the first impurity region 38 will be abbreviated as 'second electric field 101'.

Here, since the first electric field 100 and the second electric field 101 are electric fields acting in different directions, the first electric field 100 may be offset by the second electric field 101. In other words, the second electric field generated inside the first depletion region may cause the first electric field 100 to act as a cause of deterioration of the GIDL characteristics due to the difference in the work function between the gate electrode 36 and the first impurity region 38. By canceling through 101), deterioration of GIDL characteristics can be prevented. In this case, the size of the second electric field 101 may be controlled by adjusting the doping concentration, the line width, and the like of the physical properties of the first depletion region, that is, the first and second impurity regions 38 and 39. In this case, the first electric field 100 and the second electric field 101 are forces acting in opposite directions with respect to the first impurity region 38 located inside the second impurity region 29 as a working point.

Meanwhile, a depletion region, that is, a second depletion region is formed between the second impurity region 39 and the first impurity region 38 disposed outside the second impurity region 39, and the first depletion region is formed inside the second impurity region. An electric field is generated in the impurity region 38 in the direction of the second impurity region 39. Hereinafter, the electric field generated in the direction of the second impurity region 39 in the first impurity region 38 will be abbreviated as 'third electric field 102'. The second electric field 101 and the third electric field 102 are forces acting in directions facing each other, and the first and second electric fields 100 and 101 are forces different from each other. Therefore, the third electric field 102 acts to increase the size of the second electric field 101 with respect to the first electric field 100 by acting a force in a direction facing each other with the second electric field 101. Characteristic deterioration can be prevented more effectively.

In consideration of the space in which the first depletion region and the second depletion region are to be generated, the line width W2 of the second impurity region 39 is the first impurity region 38 between the second impurity region 39 and the gate electrode 36. It is preferable to form larger than the line width W1 of (). In addition, since the line width W3 of the first impurity region 39 located outside the second impurity region 29 is a place where a contact is made with a plug (not shown), the line width W2 of the second impurity region 39 is formed. And larger than the line width W1 of the first impurity region 38 located inside the second impurity region 39 (W1, W2 < W3).

4A through 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device having a buried gate according to an embodiment of the present invention. Here, the manufacturing method of the semiconductor device shown in FIG. 2A will be described by way of example.

As shown in FIG. 4A, the device isolation layer 52 is formed on the substrate 51 to define the active region 53. The device isolation layer 52 may be formed by a shallow trench isolation (STI) process.

Next, a buried gate is formed in the substrate 51 of the active region 53. The buried gate forms a trench 54 in the substrate 51, forms a gate insulating film 55 on the surface of the trench 54, and then fills a portion of the trench 54 on the gate insulating film 55. 56 may be formed through a series of processes for forming a sealing film 57 filling the remaining trench 54 on the gate electrode 56. In this case, the gate electrode 56 may be formed of a conductive film having an intermediate work function, for example, tungsten.

As shown in FIG. 4B, the impurity ion implantation and heat treatment are sequentially performed on both of the buried gate substrates 51 to form the first impurity region 58 of the first conductivity type (ie, N-type) serving as a junction region. Form. The first impurity region 58 may be formed by ion implantation of any one selected from the group consisting of phosphorus (P), arsenic (As), and antimony (Sb).

The first impurity region 58 may be formed to partially overlap the gate electrode 56 of the buried gate.

As shown in FIG. 4C, the diffusion preventing element is ion-implanted into a portion of the first impurity region 58 formed on one side of the buried gate to form the amorphous region 58A. In this case, the amorphous region 58A is formed at a position spaced apart from the trench 54 by a predetermined interval, and carbon may be used as the diffusion preventing element.

The amorphous region 58A is a region in which a second impurity region of a second conductivity type (that is, P-type) having a conductivity type complementary to that of the first impurity region 58 is to be formed, and is used to form the second impurity region. It prevents excessive diffusion of the impurity implanted in the ion implantation process and improves the activity of the impurity implanted.

As shown in FIG. 4D, the impurity ion implantation and heat treatment of the second conductive type are sequentially performed in the amorphous region 58A to form the second impurity region 59 of the second conductive type. As a result, a junction region JR including an impurity region having a heterogeneous doping structure may be formed in the buried gate one side substrate 51.

The second impurity region 59 may be formed by ion implanting boron (B) into the amorphous region 58A.

The semiconductor device formed through the above-described process includes a junction region JR formed of an impurity region having a hetero-doping structure, thereby deteriorating GIDL characteristics due to a work function difference between the gate electrode 56 and the junction region JR. Can be prevented.

In the above, the NMOS has been described for convenience of description, but the technical details of the present invention can be equally applied to the PMOS. In this case, the first conductive type is P type and the second conductive type is N type.

The technical idea of the present invention has been specifically described according to the above preferred embodiments, but it should be noted that the above embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments within the scope of the technical idea of the present invention are possible.

31 substrate 32 device isolation film
33: active area 34: trench
35 gate insulating film 36 gate electrode
37: sealing film 38: the first impurity region
39: second impurity region JR: junction region

Claims (16)

Gate electrode; And
A junction region having a hetero-doping structure overlapping with the gate electrode and having a first conductive impurity region and a second conductive impurity region alternately arranged;
And the junction region having a hetero doped structure is a drain region.
Claim 2 has been abandoned due to the setting registration fee. The method of claim 1,
And the second conductive impurity region has a structure spaced apart from the gate electrode.
Claim 3 has been abandoned due to the setting registration fee. The method of claim 1,
The drain region,
The heterogeneous doping structure in which the first conductive impurity region, the second conductive impurity region, and the first conductive impurity region are sequentially arranged in the gate electrode outer direction;
The line width of the second conductive impurity region is greater than the line width of the first conductive impurity region between the second conductive impurity region and the gate electrode and is located outside the second conductive impurity region. The line width of the impurity region is larger than the line width of the second conductive impurity region.
A buried gate formed in the substrate;
First impurity regions of a first conductivity type formed on both sides of the buried gate; And
A second impurity region of a second conductivity type formed in the first impurity region on one side of the buried gate and spaced apart from the buried gate by a predetermined interval;
And a first impurity region in which the second impurity region is located is a drain region.
Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein
The second impurity region further comprises a diffusion preventing element.
Claim 6 has been abandoned due to the setting registration fee. The method of claim 5,
The diffusion preventing element comprises a carbon.
Claim 7 was abandoned upon payment of a set-up fee. The method of claim 4, wherein
The drain region,
The heterogeneous doping structure in which the first impurity region, the second impurity region, and the first impurity region are sequentially disposed in the buried gate outward direction;
The line width of the second impurity region is greater than the line width of the first impurity region between the second impurity region and the buried gate, and the line width of the first impurity region located outside the second impurity region is the second impurity region. Semiconductor devices larger than line width.
Claim 8 was abandoned when the registration fee was paid. The method of claim 4, wherein
The buried gate is
A trench formed in the substrate;
A gate insulating film formed on the trench surface;
A gate electrode partially filling the trench on the gate insulating layer;
A sealing film filling the remaining trench on the gate electrode
≪ / RTI >
Claim 9 has been abandoned due to the setting registration fee. 9. The method of claim 8,
And the gate electrode comprises a tungsten film.
Forming a buried gate in the substrate;
Forming a first impurity region by implanting impurities of a first conductivity type into the substrate on both sides of the buried gate; And
Forming a second impurity region by ion implanting impurities of a second conductivity type into the first impurity region on one side of the buried gate so as to be spaced apart from the buried gate by a predetermined distance;
The first impurity region in which the second impurity region is located is a drain region.
Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 10,
Before forming the second impurity region,
And forming an amorphous region by ion implanting a diffusion preventing element into a region where the second impurity region is to be formed.
Claim 12 is abandoned in setting registration fee. The method of claim 11,
The diffusion preventing element comprises a semiconductor device manufacturing method.
Claim 13 was abandoned upon payment of a registration fee. The method of claim 10,
And the drain region is formed to have a hetero-doping structure in which the first impurity region, the second impurity region and the first impurity region are sequentially arranged in an outer direction of the buried gate.
Claim 14 has been abandoned due to the setting registration fee. The method of claim 13,
The line width of the second impurity region in the drain region is larger than the line width of the first impurity region between the second impurity region and the buried gate, and the line width of the first impurity region is located outside the second impurity region. The semiconductor device manufacturing method of claim 2, wherein the second impurity region is formed larger than the line width.
Claim 15 is abandoned in the setting registration fee payment. The method of claim 10,
Forming the buried gate,
Selectively etching the substrate to form a trench;
Forming a gate insulating film on the trench surface;
Forming a gate electrode partially filling the trench on the gate insulating layer; And
Forming a sealing film filling the remaining trench on the gate electrode
≪ / RTI >
Claim 16 has been abandoned due to the setting registration fee. 16. The method of claim 15,
And the gate electrode comprises a tungsten film.

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