KR101179267B1 - Reflective type phase delay mask and manufacturing method for the same - Google Patents

Abstract

A transparent substrate on which the incident illumination light of wavelength λ has an incidence angle θ, the light shielding layer patterns disposed on the substrate backside at a pitch P of (λ / 4) / sinθ; And a reflective phase delay mask including reflection phase delay parts formed on two opposite sides of two neighboring light blocking layer patterns and reflecting incident light by λ / 2 phase delay.

Description

Reflective phase delay mask and manufacturing method for the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to photolithography technology, and more particularly, to a reflective phase delay mask and a method for manufacturing super resolution.

In order to form highly integrated semiconductor devices and to form small-sized circuit patterns on wafers, efforts are being made to improve resolution in the photolithography process. In order to form a fine pattern shape, modified illumination is applied to an exposure process to inject illumination light into a photomask.

In the case of employing the incidence illumination, the light passing through the light shielding layer pattern formed as a mask pattern on the photo mask causes constructive interference to form a pattern image on the wafer. Therefore, the pitch pitch P which can form an image is determined by P = ((lambda) / 2) / sin (theta) with respect to the wavelength (lambda) and the incidence angle (theta) of illumination light. Since the resolution, which is the ability to transfer the pattern in the exposure process, is half the pattern pitch P, the resolution is = (λ / 4) / sinθ. Although the case of using a shorter wavelength light source by reducing the wavelength of the illumination light to increase the resolution can be considered, there are significant problems to overcome when applying a new light source of a shorter wavelength band to the exposure process. Accordingly, there is a need to develop a method of improving the structure of the photo mask and overcoming the exposure resolution limitation by applying modified illumination such as incident light.

The present invention proposes a photomask structure and a manufacturing method which can improve the exposure resolution.

According to an aspect of the present invention, there is provided a transparent substrate on which incident light of incident light of wavelength λ has an incident angle θ; Light blocking layer patterns disposed on a rear surface of the substrate at a pitch P of (λ / 4) / sinθ; And a reflective phase delay mask formed on two opposite sides of two neighboring light blocking layer patterns to reflect the incident light by delaying [lambda] / 2 phase.

The reflective phase delay unit includes a recess formed by recessing a middle portion of two opposite side surfaces of the light blocking layer patterns, and two surfaces facing up and down of the recess form a top and bottom mirror surface. The recessed side surface of the concave portion forms a side mirror surface so that the incident light is sequentially reflected to the upper and lower mirror surfaces and the side mirror surface to be emitted after phase retardation.

The height of the side mirror surface may be an odd multiple of (λ / 2 × cos (θ)) / 2, and the width of the upper and lower mirror surfaces may be an odd multiple of (λ / 2 × sin (θ)) / 2.

The concave portion is recessed in a lateral direction of the second light blocking layer among the first light blocking layer, the second light blocking layer, and the third light blocking layer sequentially stacked to form the light blocking layer patterns, and thus the recessed side surface of the second light blocking layer. The side mirror surface is formed, and the first light blocking layer portion and the second light blocking layer portion exposed by the recess form the upper and lower mirror surfaces.

The first light blocking layer and the third light blocking layer may include a tantalum (Ta) layer, and the second light blocking layer may include a chromium (Cr) layer.

The reflective phase delay unit may include a phase delay layer formed of a layer covering two opposite side surfaces of the light blocking layer patterns to delay a phase of the light incident and reflected from the side of the light blocking layer pattern.

Another aspect of the invention, the step of introducing a transparent substrate to which the incident light incident light of the wavelength λ has an incident angle θ; Forming light blocking layer patterns disposed on a rear surface of the substrate at a pitch P of (λ / 4) / sinθ; And forming reflective phase delay parts reflecting the light incident on two opposite side surfaces of two neighboring light blocking layer patterns by lambda / 2 phase retardation.

The forming of the light blocking layer patterns may include sequentially forming a first tantalum light blocking layer, a chromium light blocking layer, and a second tantalum light blocking layer on a rear surface of the substrate; And sequentially etching the first tantalum light shielding layer, the chrome light shielding layer, and the second tantalum light shielding layer to form a first tantalum light shielding layer pattern, a chrome light shielding layer pattern, and a second tantalum light shielding layer pattern. The forming of the type phase delay unit may include forming an etch mask that alternately exposes and fills the light blocking layer patterns; And selectively etching side surfaces of the chromium light shielding layer pattern exposed to the etch mask to form recesses.

The forming of the light shielding layer patterns may include forming a chromium light shielding layer pattern using the light shielding layer pattern, and the forming of the reflective phase delay unit may cover an opposite side surface of the chromium light shielding layer patterns. Forming a phase delay layer.

Embodiments of the present invention can improve the structure of the photo mask, and by applying a modified illumination, such as incidence illumination in the exposure process can improve the exposure resolution limit due to diffraction by 2 times. Accordingly, it is possible to expose the pattern having a size reduced by 1/2 times compared to the minimum line width of the pattern transferable pattern in the existing exposure equipment currently applied. Thereby, it is possible to manufacture a semiconductor element in a pattern of finer size.

1 to 4 are diagrams illustrating a reflective phase delay mask and a manufacturing method according to the first embodiment of the present invention.
5 and 6 are diagrams for explaining an interference phenomenon in the reflective phase delay mask according to the first embodiment of the present invention.
7 is a view showing a concave portion structure of the reflective phase delay mask according to the first embodiment of the present invention.
8 is a view showing a reflective phase delay mask and a manufacturing method according to a second embodiment of the present invention.

In the embodiments of the present invention, when the incident light having a wavelength λ is disposed on the transparent substrate on which the incident light is incident at the incident angle θ, the light shielding layer patterns are shielded so that the pitch P of the light shielding layer patterns is (λ / 4) / sinθ. Place the layer patterns. In this case, since primary light beams of two lights related to two neighboring light shielding layer patterns cause destructive interference, the light cannot be imaged as a whole. That is, two neighboring primary light beams have a phase difference of λ / 2, causing mutual interference. Accordingly, the limitation of the light technology using the conventional incidence modified illumination light limits the pitch P of the light shielding layer patterns to (λ / 2) sinθ.

In order to overcome this limitation, embodiments of the present invention provide a reflective phase delay portion that reflects light incident on side surfaces of two adjacent light blocking layer patterns by half wavelength λ / 2. To place. The reflective phase delay unit is not disposed on the side of the light shielding layer pattern opposite to the side where the reflective phase delay unit is disposed. Since the light reflected and emitted by the reflective phase delay unit is delayed in phase by λ / 2, constructive interference occurs unlike primary light of two lights related to two neighboring light shielding layer patterns. .

In the absence of the reflective phase delay unit, two neighboring primary lights have a phase difference of λ / 2. In addition to the phase difference λ / 2, the phase difference λ / 2, which is phase delayed by the reflective phase delay unit, is increased. Accordingly, the phase difference between two neighboring primary light beams is λ / 2 + λ / 2, that is, λ, so that the two neighboring primary light beams cause mutually constructive interference, so that the image of the light shielding layer patterns is placed on the wafer. It is missing. Therefore, the embodiments of the present invention can realize the exposure resolution of (λ / 8) / sinθ, which is twice as large as the existing exposure resolution limit of (λ / 4) / sinθ, thereby allowing the exposure transfer of a finer size pattern. have.

1 to 4 are diagrams illustrating a reflective phase delay mask and a manufacturing method according to the first embodiment of the present invention.

Referring to FIG. 1, in the reflective phase delay mask according to the first embodiment of the present invention, a light shielding layer pattern is formed on a transparent quartz substrate 100 to which incident light of incident light of wavelength λ has an incident angle θ. A plurality of light shielding layers 210, 230, and 250 are sequentially formed. For example, the first light shielding layer 210 is formed to have a thickness of about 10 nm as a tantalum (Ta) layer, and chromium (Cr) is approximately 50 nm to the second light shielding layer 230 on the first light shielding layer 210. Form to the thickness of about. Subsequently, the same tantalum layer as the first light blocking layer 210 is formed as the third light blocking layer 250 to have a thickness of about 10 nm. As described above, when the triple light shielding layers 210, 230, and 250 are formed in a concave shape structure for the reflective phase delay part in a subsequent process, the concave structure is formed by the difference in the etching rate by selective etching. To induce as much as possible.

Referring to FIG. 2, the triple shielding layers 210, 230, and 250 are selectively etched to form the shielding layer patterns 200. The light blocking layer patterns 200 are disposed to have a pitch P depending on the wavelength λ and the incident angle θ of the incident illumination light. For example, the light blocking layer patterns 200 are selectively etched to be arranged at a pitch P of (λ / 4) / sinθ.

Referring to FIG. 3, a reflective phase retarder 204 is formed on two opposite side surfaces 201 of two adjacent light blocking layer patterns 200 to reflect incident light by retarding λ / 2 phases, and the opposite surface. An etch mask 260 including an photoresist layer is formed to form an etch mask 260 that alternately exposes and fills the two light blocking layer patterns 200 facing each other so as not to be formed in the 203. do. An etching process of etching the exposed sidewalls of the light blocking layer pattern 200 exposed to the etching mask is performed. In this case, the pattern side surface of the second light blocking layer 230 including the chromium layer may be selectively wet-removed by using a wet etch selectivity between the tantalum layer and the chromium layer. By the selective etching, the side surface of the second light blocking layer 230 is recessed, and thus, the recess 204 is formed on the sidewall of the light blocking layer pattern 200. The side of the recess 204, that is, the side of the second light blocking layer 230 forms a side mirror surface 205, and the upper surface portion of the third light blocking layer 250 exposed to the recess 204 is a lower mirror. The lower surface portion of the first light blocking layer 210 that forms the surface 206 is exposed to form the upper mirror surface 207. The light incident on the concave portion 204 is sequentially reflected on the lower mirror surface 206, the side mirror surface 205, and the upper mirror surface 207, and the phase is delayed by λ / 2 or an odd number thereof and emitted.

Thereafter, the etching mask 260 is selectively removed as shown in FIG. 4. The constructive destructive interference of the reflective phase delay mask provided as described above will be described with reference to FIGS. 5 and 6.

Referring to FIG. 5, light related to the light blocking layer patterns 200 disposed at a pitch P of (λ / 4) / sinθ is incident at an incident incident angle θ. At this time, the light A, B, C, D and E have a phase difference of λ / 4. Therefore, the zero-order light of A and E light has constructive interference with a phase of λ, and the primary light has constructive interference with a phase of λ + λ. The 0th order light of B light has a phase of 3λ / 4 + λ / 4 = λ and constructively interferes, and the primary light is λ, which is a component delayed by the reflective phase delay unit 204 at a phase of 3λ / 4 + λ / 4. / 2 is added to have a phase of 3λ / 4 + λ / 4 + λ / 2 = 2λ and constructively interfere. The zero-order light of C light has constructive interference with a phase of λ / 2 + λ / 2 = λ, and the primary light has constructive interference with a phase of λ / 2 + λ / 2. The 0th order light of D light has a phase of λ / 4 + 3λ / 4 = λ and constructively interferes, and the primary light is λ, which is a component delayed by the reflective phase delay unit 204 at a phase of λ / 4 + λ / 4 / 2 is added to have a phase of λ / 4 + 3λ / 4 + λ / 2 = 2λ and constructively interfere. Since the primary light of the D light, which is the DD 'path, and the primary light of the E light (or the primary light of the C light, of the CC' path) of the EE 'path are in phase, they are constructively interfered with each other.

In contrast, when the reflection type phase delay unit 204 is not introduced, the first order light of the D light of the DD 'path and the first light of the E light of the EE' path generate a phase difference of λ / 2 between each other. do. That is, as shown in FIG. 6, the primary phase light of the DD 'path is delayed by λ / 2 compared to the light of the DD' 'path by the reflective phase delay unit 204 included in the light shielding layer pattern 200. However, the primary light of the DD 'path and the light of the EE' 'path may cause constructive interference, but the primary light of the DD' 'path and the primary light of the EE' path cancel each other because they cause destructive interference.

Therefore, in the first embodiment of the present invention, by introducing the reflective phase delay unit 204 and retarding the phase of [lambda] / 2, the primary light beams can all be induced to cause constructive interference. Accordingly, the limit resolution can be realized by λ / 8 × sin (θ).

Referring to FIG. 7, considering the modified illumination light 300 that is incident on the substrate 100 of the reflective phase delay mask according to the first embodiment of the present invention at an incident angle θ, that is, a structure that forms a phase delay path, that is, In the recess structure of the reflective phase delay unit 204, the height T of the pattern of the second light blocking layer 230, that is, the height of the side mirror surface 205 is (λ / 2 × cos (θ)). The width W of the upper and lower mirror surfaces 206 and 207, that is, the width W of the exposed surfaces of the first and third light blocking layers 210 and 250 is (λ / 2 x). It is set to an odd multiple of sin (θ)) / 2. Therefore, the height T in the concave structure of the reflective phase delay unit 204 required to realize the phase delay of λ / 2 is calculated to be 49.24 nm as the minimum size when the incident angle is 10 degrees in the ArF light source. The width W is set to a minimum size of 8.68 nm. Thus, the etching process for forming the recess is controlled to adjust the wet time to laterally recess by 8.68 nm or an odd number thereof. In addition, the thickness of the second light blocking layer 230 is deposited to have a thickness of 49.24 nm or an odd number thereof.

Referring to FIG. 8, in the reflective phase delay mask according to the second exemplary embodiment of the present invention, light blocking layer patterns 1200 include a chromium (Cr) layer on the transparent substrate 1100. When the incident illumination light having the wavelength λ is incident with the incident angle θ, the light shielding layer patterns 1200 are formed at a pitch P of (λ / 4) / sinθ. In this case, the phase delay layer 1240 is formed of a layer covering two opposite sides of the light blocking layer patterns 1200 to form a reflective phase delay unit. In this case, the phase retardation layer 1240 has a low reflectance, high transmittance, and is formed to reflect incident light at an interface with the chromium (Cr) layer. At this time, the phase retardation layer 1240 is formed to have a thickness such that the emitted light has a λ / 2 phase delay compared to the incident light. The phase delay layer 1240 may include a molybdenum (Mo) layer or a molybdenum silicon (MoSi) layer. As described with reference to FIG. 5, since the phase delay layer 1240 serves as a reflective phase delay unit for inducing a λ / 2 phase delay, a limit resolution of λ / 8 × sin (θ) can be realized. Accordingly, when the reflective phase delay mask of the present invention is applied to an existing ArF exposure apparatus, a fine pattern having a size reduced by 1/2 times may be exposed. Accordingly, it is possible to implement scale down of the semiconductor device without improving the exposure equipment.

100: transparent substrate, 200: light shielding layer pattern,
204: reflective phase delay unit, 205: side mirror surface,
206: lower mirror surface, 207: upper mirror surface,
1240: phase delay layer.

Claims (9)

A transparent substrate on which the incident illumination light having the wavelength λ has an incident angle θ;
Light blocking layer patterns disposed on a rear surface of the substrate at a pitch P of (λ / 4) / sinθ; And
And reflective phase delay parts formed on two opposite sides of two adjacent light blocking layer patterns to reflect the incident light by λ / 2 phase retardation.
And a reflective phase delay mask in which the reflective phase delay portion is not formed on the other side of the opposite side opposite to the side surface of the light blocking layer pattern in which the reflective phase delay portion is formed. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1,
The reflective phase delay unit
A center portion of two opposite side surfaces of the light blocking layer patterns is recessed to form a recess;
Two surfaces facing up and down the concave portion form an up and down mirror surface, and the recessed side of the concave portion forms a side mirror surface so that the incident light is sequentially reflected on the upper and lower mirror surfaces and the side mirror surface. Reflective phase delay mask emitted after the phase delay. Claim 3 has been abandoned due to the setting registration fee. The method of claim 2,
The height of the side mirror surface is an odd multiple of (λ / 2 x cos (θ)) / 2,
And a width of the upper and lower mirror surfaces is an odd multiple of (λ / 2 x sin (θ)) / 2. Claim 4 has been abandoned due to the setting registration fee. The method of claim 2,
The recess is
Recessed in a lateral direction of the second light blocking layer among the first light blocking layer, the second light blocking layer, and the third light blocking layer sequentially stacked to form the light blocking layer patterns
The recessed side surface of the second light blocking layer forms the side mirror surface,
And the first and second light blocking layer portions exposed by the recess form the upper and lower mirror surfaces. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein
The first light blocking layer and the third light blocking layer include a tantalum (Ta) layer,
The second light blocking layer includes a chromium (Cr) layer. Claim 6 has been abandoned due to the setting registration fee. The method of claim 1,
The reflective phase delay unit
And a phase delay layer formed of a layer covering two opposite side surfaces of the light blocking layer patterns and retarding a phase of the light incident and reflected from the side of the light blocking layer pattern. Introducing a transparent substrate having an incident angle θ having an incident angle θ, the incident light having a wavelength λ;
Forming light blocking layer patterns disposed on a rear surface of the substrate at a pitch P of (λ / 4) / sinθ; And
Forming reflective phase delay parts reflecting the light incident on two opposite sides of two neighboring light shielding layer patterns by lambda / 2 phase retardation;
The reflective phase delay mask manufacturing method of claim 2, wherein the reflective phase delay unit is not formed on the other side of the opposite side of the light blocking layer pattern on which the reflective phase delay unit is formed. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein
Forming the light blocking layer patterns
Sequentially forming a first tantalum shielding layer, a chromium shielding layer, and a second tantalum shielding layer on the back surface of the substrate; And
Sequentially etching the first tantalum light shielding layer, the chrome light shielding layer, and the second tantalum light shielding layer to form a first tantalum light shielding layer pattern, a chrome light shielding layer pattern, and a second tantalum light shielding layer pattern,
Forming the reflective phase delay unit
Forming an etch mask that alternately exposes and fills the light blocking layer patterns; And
And selectively etching side surfaces of the chromium light shielding layer pattern exposed to the etch mask to form recesses. Claim 9 has been abandoned due to the setting registration fee. The method of claim 7, wherein
Forming the light blocking layer patterns
Forming a chromium light shielding layer pattern using the light shielding layer pattern;
Forming the reflective phase delay unit
And forming a phase delay layer covering the mutually opposite side surfaces of the chromium light blocking layer patterns.

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