KR101172891B1 - Digital proportional integral loop filter - Google Patents

Abstract

The present invention relates to a digital proportional integral loop filter. A digital proportional integral loop filter according to the present invention comprises: a first proportional amplifier for outputting a value obtained by multiplying a phase error value by a first proportional loop gain; A first integrating amplifier for outputting a value obtained by multiplying a phase error accumulation value by a first integrating loop gain; A second proportional amplifier for outputting a value obtained by multiplying the phase error value by a second proportional loop gain; A second integrating amplifier for outputting a value obtained by multiplying the accumulated phase error value by a second integrating loop gain; A first offset generation unit generating a first offset obtained by multiplying a phase error average value by the first proportional loop gain minus the second proportional loop gain; A second offset generator for generating a second offset obtained by multiplying a phase error cumulative average value by the first integral loop gain minus the second integral loop gain; A first adder for adding an output of the first proportional amplifier and an output of the first integral amplifier; A second adder for adding the output of the second proportional amplifier, the output of the second integral amplifier, the output of the first offset generator and the output of the second offset generator; And

It includes a mux for outputting any one of the output of the first adder or the second adder.

Phase Error, Gear Shift, ADPLL, Loop Filter

Description

Digital proportional integral loop filter

The present invention relates to a digital proportional integral loop filter for fast settling time, and more particularly, by including an average value of phase error and phase error accumulation in the offset generation, even if the change of the loop filter gain value is large. It is a device that can change gain by changing switching, and locks at a desired frequency at one time to shorten the settling time.

The present invention is derived from research conducted as part of the IT source technology development project of the Ministry of Knowledge Economy. [Task Management Number: 2008-F-008-01, Title: Development of Advanced Digital RF Technology for Next Generation Wireless Fusion Terminal]

Phase-frequency detectors, charge pumps and RC loop filters in traditional analog PLLs have been replaced by time-to-digital converters and simple digital loop filters in the ADPLL. This is because the signal can be processed by a digital circuit, which can avoid the dependence on the minute voltage resolution of the analog circuit. By applying this digital signal processing method to the loop filter, we propose a new technique for the ADPLL digital loop filter with fast frequency acquisition time while maintaining excellent phase noise characteristics and spurious performance.

1 is a diagram of a proportional loop filter 100 using a conventional gear-shift technique. The proportional loop filter 100 using the gear shift technique includes the bit shifters 120 and 121, the multipliers and dividers 140 and 143, and the α ₁ ? Φ _E [k] (130) signal when the tracking mode control signal is 0. Is 1, it is composed of a mux 150 for exporting the sum of α ₂ ~ Φ _E [k] (131) and ΔNTW (142).

The output of the phase detector 101 becomes the input of the proportional loop filter 100. To reduce the settling time of the ADPLL quickly, the PLL loop gain must be increased. To achieve good phase noise, the PLL loop gain must be reduced. The gear shift technique is used to satisfy both of these opposing characteristics.

When the tracking mode control signal is '0' using the MUX, it means that a fast settling time is to be obtained, and α ₁ ? Φ _E [k] (130) value is selected by selecting α ₁ which widens the bandwidth of the ADPLL. To the loop filter output. It means when desired excellent phase noise characteristics when the the tracking mode control signal "1", and to cut down on noise by narrowing the bandwidth of the loop provide the α _1> α ₂ of _{α 2 α 2? Φ E [} k] (131 )

However, suddenly changing the output from α ₁ Φ _E [k] 130 to α ₂ Φ _E [k] 131 may unlock the frequency of the ADPLL.

α ₁ ? Φ _E [k] (130) = α ₂ ? Φ _E [k] (131) + ΔNTW

Therefore, when the ΔNTW (142) offset is added to Equation 1, even if the loop filter gain is changed, the ΔNTW offset plays a role of maintaining the phase error value as before the change. To reduce the

ΔNTW (142) = (α ₁ -α ₂ )? Φ _E [k]

The offset value can be obtained by using Equation 1 using the condition of Equation 1.

 Since multipliers and divisions have a large hardware size, using α, which is a power of 2, enables bit shifts (120, 121) to reduce hardware size and complexity.

The output of the mux is an output 151 of the loop filter and becomes an input of the digitally controlled oscillator (DCO) 160. The loop filter applied with this gear shift can add more noise at the moment of gear shift switching, and if the difference between α ₁ and α ₂ is large, the gear shift cannot find the frequency corresponding to α ₂ at a time and the desired frequency value. Settling time for this also has a disadvantage. Therefore, the loop filter gain value used to shorten the settling time and increase the phase noise characteristics has to be changed sequentially such as 2 ^-2 ⇒ 2 ^-4 ⇒ 2 ^-6 to increase the number of shift switching. In addition, since the gear shift of the loop filter gain is applied only to the structure of the proportional loop filter, there may be a problem in stability of the ADPLL.

Accordingly, the present invention is to solve the problems of the prior art as described above, by using the average value of the phase error and phase error accumulation in the offset generation, even if the change in the loop filter gain value is large, the desired frequency can be output in one gain change. It is to provide a digital proportional integral loop filter for fast settling time that is locked at a desired frequency at a time to reduce the settling time.

According to an aspect of the present invention, there is provided a digital proportional integral loop filter for fast settling time, comprising: a first proportional amplifier for outputting a phase error value multiplied by a first proportional loop gain; A first integrating amplifier for outputting a value obtained by multiplying a phase error accumulation value by a first integrating loop gain; A second proportional amplifier for outputting a value obtained by multiplying the phase error value by a second proportional loop gain; A second integrating amplifier for outputting a value obtained by multiplying the accumulated phase error value by a second integrating loop gain; A first offset generation unit generating a first offset obtained by multiplying a phase error average value by the first proportional loop gain minus the second proportional loop gain; A second offset generator for generating a second offset obtained by multiplying a phase error cumulative average value by the first integral loop gain minus the second integral loop gain; A first adder for adding an output of the first proportional amplifier and an output of the first integral amplifier; A second adder for adding the output of the second proportional amplifier, the output of the second integral amplifier, the output of the first offset generator and the output of the second offset generator; And a mux for outputting any one of the output of the first adder and the second adder.

Digital proportional integral loop filter for fast settling time according to the present invention offsets the problem that the number of gear shift switching increases when the loop filter gain value is large in the conventional gear shift method. This was solved by inclusion in the production.

In addition, even if the change of the loop filter gain value is large, it is locked at a desired frequency at one time, and thus, the settling time is also short. In addition, the stability of the ADPLL is increased by using a proportional integral loop filter.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. In the following detailed description of the preferred embodiments of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In the drawings, like reference numerals are used throughout the drawings.

In addition, throughout the specification, when a part is 'connected' to another part, it is not only 'directly connected' but also 'indirectly connected' with another element in between. Include. Also, to "include" an element means that it may include other elements, rather than excluding other elements, unless specifically stated otherwise.

2 is a diagram showing the configuration of a digital proportional integral loop filter according to an embodiment of the present invention.

The digital proportional integral loop filter according to the embodiment of the present invention may include a first proportional amplifier 210, a first integral amplifier 220, a first adder 230, a second proportional amplifier 240, and a second proportional amplifier 240. The integrated amplifier 250 includes a first offset generator 260, a second offset generator 270, a second adder 280, and a mux 290.

The first proportional amplifier 210 and the second proportional amplifier 240 output a value obtained by multiplying the phase error by the proportional loop gain by inputting the phase error.

The first integrating amplifier 220 and the second integrating amplifier 250 generate a phase error accumulation by accumulating the phase error, and then output a value obtained by multiplying the integral loop gains by the phase error accumulation.

The first offset generator 260 generates a phase error average value by averaging phase errors for a predetermined period of time when the average enable signal is activated, and then subtracts the phase from the first proportional loop gain to the value obtained by subtracting the second proportional loop gain. A value obtained by multiplying the error average value is generated as the first offset and output.

The second offset generator 270 generates a phase error cumulative average value by averaging phase error accumulations for a predetermined period during which the average enable signal is activated, and then subtracting the second integration loop gain from the first integration loop gain. A value obtained by multiplying the phase error cumulative average value is generated and output as a second offset.

The first adder 230 adds the output of the first proportional amplifier 210 and the output of the first integral amplifier 220 and outputs the output to the mux 290.

The second adder 280 outputs the output of the second proportional amplifier 240, the output of the second integral amplifier 250, the output of the first offset generator 260, and the second offset generator 260. The output of 270 is added and output to the mux 290.

The mux 290 outputs the output of the first adder 230 when the gain conversion enable control signal is 0, and outputs the output of the second adder 280 when 1.

3 illustrates a specific configuration of a digital proportional integral loop filter according to the embodiment described in FIG. 2. Hereinafter, a description will be given with reference to FIGS. 2 and 3.

Where α ₁ represents the first proportional loop gain, α ₂ represents the second proportional loop gain, β ₁ represents the first integral loop gain, and β ₂ represents the second integral loop gain. (ΔNTW1 is first offset, ΔNTW2 is second offset)

2 and 3, the digital proportional integral loop filter according to the present embodiment takes a phase error Φ _E [k], 301 as an input and consists of an adder 340 and a feedback loop 341. The accumulation LF_temp [k] generator 342 may be shared by the second integrating amplifier 250 and the first and second offset generators 260 and 270.

The first proportional amplifier 210 may include one amplifier 310. Since the first proportional loop gain α ₁ is multiplied by the phase error Φ _E [k], α ₁ ˜Φ _E [k] may be the output of the first proportional amplifier 210.

The first integral amplifier 220 may include the phase error accumulator 342 and one amplifier 312. The phase error Φ _E [k] passes through the phase error accumulation generator 342 to generate a phase error cumulative accumulation LF_temp [k] and multiplies the first integral loop gain β ₁ by β. ₁ ? LF_temp [k] may be an output of the first integrating amplifier 220.

The output of the first proportional amplifier 210 and the output of the first integral amplifier 220 are summed by the adder 314 so that the gain conversion enable signal is 0 (the state before the gain conversion) in the mux 315. If the loop filter output is

LF_output [k] = α ₁ ? Φ _E [k] + β ₁ ? LF_temp [k]

This can be

The second proportional amplifier 240 may include two amplifiers 310 and 334. Since the phase error Φ _E [k] is multiplied by α ₁ and (α ₂ / α ₁ ), α ₂ ˜ Φ _E [k] may be the output of the second proportional amplifier 240.

The second integrating amplifier 250 may include the phase error accumulator 342 and two amplifiers 312 and 364. Since the phase error Φ _E [k] passes through the phase error accumulator 342, a cumulative phase error LF_temp [k] is generated and multiplied by β ₁ and (β ₂ / β ₁ ) in turn. β ₂ ? LF_temp [k] may be an output of the second integrating amplifier 250.

The first offset generator 260 may include a phase error averager 320, two amplifiers 330 and 332, and one adder 331. The first offset ΔNTW1 when the phase error averager 320 is deactivated and activated is as follows.

ΔNTW1 = (α ₁ -α ₂ ) Φ _E [k]

ΔNTW1 _ave = (α ₁ -α ₂ ) Φ _{E_ ave} [k]

The second offset generator 270 may include a phase error accumulator 350, two amplifiers 360 and 362, and one adder 361. The second offset ΔNTW2 when the phase error accumulator 350 is deactivated and activated is as follows.

ΔNTW2 = (β ₁ -β ₂ ) LF_temp [k]

ΔNTW2 _ave = (β ₁ -β ₂ ) LF_temp _ave [k]

In this case, the phase error average Φ _{E_ave} [k] and the phase error cumulative average LF_temp _ave [k] are the phase error Φ _E [k] and the phase error during a period where the average enable signal is 1. Accumulated (LF_temp [k]) is a value obtained by dividing it by the cumulative number of times.

The output of the second proportional amplifier 240, the output of the second integral amplifier 250, the output of the first offset generator 260, and the output of the second offset generator 270 are an adder ( If the gain conversion enable signal is 1 (state after gain conversion) in the MUX 315, the output of the loop filter is

When the phase error averager 320 and the phase error accumulator 350 are deactivated

LF_output [k] = α ₂ ? Φ _E [k] + ΔNTW1 + β ₂ LF_temp [k] + ΔNTW2

And if enabled

LF_output [k] = α ₂ ? Φ _E [k] + ΔNTW1 _ave + β ₂ ? LF_temp [k] + ΔNTW2 _ave

.

Looking at the operation of the digital proportional integral loop filter according to the present invention by comparing the output before and after the gain conversion as follows.

When the gain conversion enable signal is 0 (pre-gain conversion state), that is, the output of the loop filter before the loop filter gain conversion is

LF_output [k] = α ₁ ? Φ _E [k] + β ₁ ? LF_temp [k]

When the phase error averager 320 and the phase error cumulative average 350 are deactivated and the gain conversion enable signal is 1 (a state after the gain conversion), that is, the output of the loop filter after the loop filter gain conversion is

LF_output [k] = α ₂ ? Φ _E [k] + ΔNTW1 + β ₂ LF_temp [k] + ΔNTW2

.

In addition, the two offsets are as follows.

ΔNTW1 = (α ₁ -α ₂ ) Φ _E [k]

ΔNTW2 = (β ₁ -β ₂ ) LF_temp [k]

Therefore, the output before and after the loop filter gain conversion is the same, so that frequency locking is not solved during the gain conversion. In addition, the stability of the ADPLL can be improved by using the proportional integral loop filter compared to the proportional loop filter.

Another feature of the digital proportional integral loop filter according to an embodiment of the present invention is that, unlike the conventional gear shifting method, the phase shifting unit does not use the phase error Φ _E [k] as the input of the gear shift in the proportional amplifier. The error mean (Φ _{E_ave} [k]) is used. In addition, instead of the phase error accumulation (LF_temp [k]), the phase error cumulative average (LF_temp _ave [k]) is used as the input of the gear shift in the integral amplifier.

Therefore, the two offsets using these averages

ΔNTW1 _ave = (α ₁ -α ₂ ) Φ _{E_ ave} [k]

ΔNTW2 _ave = (β ₁ -β ₂ ) LF_temp _ave [k]

At this time, the loop filter output after the loop filter gain conversion is

LF_output [k] = α ₂ ? Φ _E [k] + ΔNTW1 _ave + β ₂ ? LF_temp [k] + ΔNTW2 _ave

.

By generating the offset using the average value as described above, even if the change in the loop filter gain value is large, the desired frequency can be output with one gain change.

FIG. 4 is a graph illustrating a simulation result illustrating changes in ADPLL output frequency to which a digital proportional integral loop filter according to the present invention is added.

Phase error average (Φ _{E_ave} [k]) and phase error cumulative average (LF_temp) in the phase error _averager and phase error accumulator in the first and second offset generators during the phase error average interval 420 before the gain conversion of the loop filter. _ave [k])

And the moment that the enable control signal is a gain converter that ^{_{1 α 1 = 2 -3, β}} 1 = 2 - in the ⁷ α ₂ = ₂ ^-8, β ₂ is the loop filter gain values are converted to a = ^2-15.

Referring to A graph of FIG. 4 showing the DCO input signal, it can be seen that a DCO input close to a desired frequency occurs at a time after the loop filter gain conversion is performed.

In addition, in the B graph of FIG. 4 showing the DCO output signal, it can be seen that a frequency corresponding to a desired frequency range is generated at one time after the loop filter gain conversion is performed.

The digital proportional integral loop filter according to the present invention solves the problem of increasing the number of gear shift switching times when the loop filter gain value is large in the conventional gear shift method. . In addition, even if the change of the loop filter gain value is large, it is locked at a desired frequency at one time, and thus, the settling time is also short. In addition, the stability of the ADPLL is increased by using a proportional integral loop filter.

The present invention is not limited by the above-described embodiment and the accompanying drawings. It will be apparent to those skilled in the art that the present invention may be substituted, modified, and changed in accordance with the present invention without departing from the spirit of the present invention.

1 is a view showing the configuration of a type-I loop filter using a conventional gear shift technique.

2 is a diagram showing the configuration of a digital proportional integral loop filter according to an embodiment of the present invention.

3 is a diagram illustrating a specific configuration of a digital proportional integral loop filter according to the embodiment disclosed in FIG. 2.

4 is a diagram illustrating a simulation result graph illustrating changes in ADPLL output frequency to which a digital proportional integral loop filter is added.

<Code Description of Main Parts of Drawing>

210: first proportional amplifier 220: first integral amplifier

230: first adder 240: second proportional amplifier

250: second integrated amplifier 260: first offset generator

270: second offset generator 280: second adder

290: mux

Claims (7)

A first proportional amplifier for outputting a phase error value multiplied by a first proportional loop gain; A first integrating amplifier for outputting a value obtained by multiplying a phase error accumulation value by a first integrating loop gain; A second proportional amplifier for outputting a value obtained by multiplying the phase error value by a second proportional loop gain; A second integrating amplifier for outputting a value obtained by multiplying the accumulated phase error value by a second integrating loop gain; A first offset generation unit generating a first offset obtained by multiplying a phase error average value by the first proportional loop gain minus the second proportional loop gain; A second offset generator for generating a second offset obtained by multiplying a phase error cumulative average value by the first integral loop gain minus the second integral loop gain; A first adder for adding an output of the first proportional amplifier and an output of the first integral amplifier; A second adder for adding the output of the second proportional amplifier, the output of the second integral amplifier, the output of the first offset generator and the output of the second offset generator; And And a mux for outputting any one of the output of the first adder and the second adder. The method of claim 1, wherein the first offset generator, A phase error averager for finding an average value of phase errors in a section in which the average enable control signal is activated; A first amplifier multiplying the output of the phase error averager by a value of (first proportional loop gain / second proportional loop gain); A third adder configured to output a value obtained by subtracting the output of the phase error averager from the output of the first amplifier; And A second amplifier multiplying the output of the third adder by the second proportional loop gain Digital proportional integral loop filter comprising a. The method of claim 1, wherein the second offset generator, A phase error accumulator for finding an average value of the phase error accumulators within a period in which the average enable control signal is activated; A third amplifier multiplying the output of the phase error accumulator by a value of (first integral loop gain / second integral loop gain); A fourth adder configured to output a value obtained by subtracting the output of the phase error accumulator from the output of the third amplifier; And A fourth amplifier multiplying the output of the fourth adder by the second integral loop gain Digital proportional integral loop filter comprising a. The method of claim 1, wherein the digital proportional integral loop filter, One phase error accumulation generator that generates a phase error accumulation value by inputting a phase error / RTI &gt; And the first integral amplifier, the second integral amplifier, and the second offset generator share the phase error accumulator. The method of claim 4, wherein the phase error accumulation generator, A fifth adder for adding the phase error value and the output of the feedback loop; And A feedback loop providing an output of the fifth adder as an input of the fifth adder Digital proportional integral loop filter comprising a. The method of claim 1, First to third phase error accumulators each of which is formed in the first integral amplification unit, the second integral amplification unit, and the second offset generation unit, and generates a phase error accumulation value by inputting a phase error; Digital proportional integral loop filter comprising a. The method of claim 1, wherein the mux, Outputting the first adder when the gain conversion enable control signal is in the pre-gain conversion state, and outputting the output of the second adder when the gain conversion enable control signal is in the post-gain conversion state. Digital Proportional Loop Filter.

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