KR101172046B1 - Thin film transistor, method for manufacturing the same and array substrate for liquid crystal display using it - Google Patents

Abstract

The present invention is to reduce the feed-through voltage (ΔVp) in the liquid crystal display device, and to improve the image quality by reducing the flicker or afterimage, the gate electrode formed on the transparent insulating substrate, the gate insulating film covering the gate insulating film, the gate insulating film A formed semiconductor layer, a source electrode formed to overlap the gate electrode on the semiconductor layer, a drain electrode formed on the semiconductor layer to face the source electrode and not overlapping the gate electrode, and formed at an interface between the drain electrode and the semiconductor layer. A thin film transistor including an ohmic contact layer, a method of manufacturing the same, and an array substrate for a liquid crystal display device using the same are provided.

Liquid Crystal Display, Thin Film Transistor, Gate Electrode, Parasitic Capacitance

Description

Thin film transistor, method for manufacturing the same and array substrate for liquid crystal display using it}

1 is a plan view schematically illustrating some pixels of a conventional array substrate for a liquid crystal display device.

FIG. 2 is a plan view illustrating the thin film transistor of FIG. 1.

FIG. 3 is a cross-sectional view illustrating a surface of FIG. 2.

4 is a plan view illustrating some pixels of a liquid crystal display according to an exemplary embodiment of the present invention.

5 is a plan view illustrating the thin film transistor of FIG. 4.

FIG. 6 is a cross-sectional view illustrating the II-II 'surface of FIG. 5.

FIG. 7 is a cross-sectional view illustrating the III-III ′ surface of FIG. 5.

FIG. 8 is a cross-sectional view illustrating a channel portion of a semiconductor layer in FIG. 7.

9 is a flowchart illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention.

10 is a plan view illustrating some pixels of a liquid crystal display according to another exemplary embodiment of the present invention.

11 is a plan view illustrating some pixels of a liquid crystal display according to yet another exemplary embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS (S)

100: transparent insulating substrate 110: gate insulating film

120, 121, 122: gate lines 130, 131, 132: data lines

140: thin film transistor 141: gate electrode

142: source electrode 143: drain electrode

144: semiconductor layer 145, 146: ohmic contact layer

150, 152, and 154: pixel electrodes 151 and 153: pixel lines

160, 162: common line 161, 163: common electrode

CH: contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, a method for manufacturing the same, and an array substrate for a liquid crystal display device using the same, and more particularly, a thin film transistor capable of improving image quality by reducing parasitic capacitance (Cgd), a method for manufacturing the same, and a liquid crystal display using the same. An array substrate for an apparatus.

The liquid crystal display device injects a liquid crystal material having anisotropic dielectric constant between a color filter substrate, which is a transparent insulating substrate, and an array substrate, and adjusts the intensity of an electric field formed in the liquid crystal material to change the molecular arrangement of the liquid crystal material. Through this, the display device expresses a desired image by controlling the amount of light transmitted through the transparent insulating substrate. As the liquid crystal display, a thin film transistor liquid crystal display (TFT LCD) using a thin film transistor (TFT) as a switching element is mainly used.

1 is a plan view schematically illustrating some pixels of a conventional array substrate for a liquid crystal display device.

As shown in FIG. 1, an array substrate for a liquid crystal display device includes a matrix of gate lines 20 that form a row, and data lines 30 that form a column and intersect the gate lines 20. The pixel regions P divided by the gate lines 20 and the data lines 30 intersecting with each other are formed together to form a frame (screen). When the scan pulse is sequentially applied to the gate lines 20, a data voltage is applied to the data lines 30 in response to the scan pulse, and one frame is displayed on the liquid crystal display.

A thin film having a gate electrode 41, a source electrode 42, and a drain electrode 43 in each pixel area P and positioned at an intersection of the gate line 20 and the data line 30 to operate as a switching element. The transistor 40 and the pixel electrode 50 connected to the drain electrode 43 of the thin film transistor 40 are constituted.

The thin film transistor 40 applies a data voltage supplied from the data line 30 to the pixel electrode 50 in response to a scan pulse supplied from the gate line 20.

It corresponds to the difference voltage between the data voltage supplied from the data line 30 and the common voltage during the period in which the thin film transistor 40 is turned on by the gate high voltage VGH of the scan pulse supplied to the gate line 20. The voltage is charged in the pixel electrode 50, and the voltage charged in the pixel electrode 50 is maintained during the period in which the thin film transistor 40 is turned off by the gate low voltage VGL of the scan pulse.

In this case, the gate high voltage VGH is generated between the gate electrode 41 and the drain electrode 43 of the thin film transistor 40 at the falling edge of the scan pulse falling to the gate low voltage VGL. The voltage charged in the pixel electrode 50 by the parasitic capacitor Cgd or the like decreases by? Vp, which is called a feed through voltage or a kick back voltage.

The feed-throw voltage ΔVp is changed in accordance with the data voltage applied to the liquid crystal display, causing flicker or afterimage, thereby degrading the image quality. It is defined as a function.

Here, Cgd is a parasitic capacitance formed between the gate electrode 41 and the drain electrode 43 of the thin film transistor 40, Clc is a liquid crystal capacitance, and Cst is a storage capacitance. DELTA Vg is a difference voltage between the gate high voltage VGH and the gate low voltage VGL forming a scan pulse.

FIG. 2 is a plan view illustrating the thin film transistor of FIG. 1, and FIG. 3 is a cross-sectional view illustrating a plane of FIG. 2.

2 and 3, the thin film transistor 40 on the transparent insulating substrate 10 may include a gate electrode 41, a gate insulating layer 11, a semiconductor layer 44, an ohmic contact layer 45, 46, and a source. The electrode 42, the drain electrode 43, etc. are comprised.

The drain electrode 43 is formed in an I shape and connected to the pixel electrode 50, and the source electrode 42 is formed in a U shape surrounding the drain electrode 43 and connected to the data line 30. have. That is, an asymmetrical shape is formed such that a U-shaped source electrode 42 having a concave groove is formed, and the drain electrode 43 is positioned at regular intervals from the source electrode 42 inside the groove of the source electrode 42. It has a structure.

The drain electrode 43 and the source electrode 42 overlap the gate electrode 41 by a predetermined area R1 and R2.

The U-shaped thin film transistor 40 having such a configuration is used for the purpose of improving the overlay margin or reducing the area occupied by the source and drain electrodes 42 and 43 to improve the aperture ratio.

However, in the thin film transistor 40, parasitic capacitance Cgd exists in proportion to the overlap area R1 between the drain electrode 43 and the gate electrode 41, and a feed write generated due to the parasitic capacitance Cgd. The low voltage ΔVp causes problems such as flicker and afterimage. In addition, increasing the storage capacitance in order to reduce the effect of the feed through voltage (ΔVp), resulting in a decrease in aperture ratio.

On the other hand, a liquid crystal display having an in-plane switching (IPS) structure requires a higher driving voltage than a twisted nematic (TN) structure, so that the feed through voltage (ΔVp) is also increased, resulting in flicker or afterimage. There is a problem that more is induced, and thus the image quality is further reduced.

Accordingly, an object of the present invention is to provide a thin film transistor which minimizes parasitic capacitance Cgd by eliminating an overlap area between a gate electrode and a drain electrode.

Another technical problem to be achieved by the present invention is to provide a method of manufacturing a thin film transistor which can efficiently manufacture such a thin film transistor.

Another object of the present invention is to provide an array substrate for a liquid crystal display device which can improve image quality by reducing a feed through voltage ΔVp and reducing flicker or afterimage by using such a thin film transistor. will be.

Technical problems to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned above will be clearly understood by those skilled in the art from the following description. Could be.

A thin film transistor according to an embodiment of the present invention for achieving the technical problem is a gate electrode formed on a transparent insulating substrate, a gate insulating film formed on the front surface of the transparent insulating substrate covering the gate electrode, and on the gate insulating film A semiconductor layer formed of an undoped amorphous silicon material and having a region corresponding to the gate electrode forming a channel portion, a source electrode formed to overlap the gate electrode on the semiconductor layer, and positioned on the semiconductor layer N +, which is formed at an interface between the source electrode and the source electrode and the source electrode, the drain electrode and the semiconductor layer, which are formed to face the source electrode at regular intervals and do not overlap the gate electrode. A resistive contact layer made of hydrogenated amorphous silicon material is included And it characterized in that.

In the thin film transistor according to the exemplary embodiment of the present invention, the source electrode and the drain electrode are preferably symmetrical to face each other, and more preferably a bar-shaped center portion.

A method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention includes forming a gate electrode on a transparent insulating substrate, forming a gate insulating film on an entire surface of the transparent insulating substrate covering the gate electrode, and forming the gate insulating film. Depositing an undoped amorphous silicon layer and an n + hydrogenated amorphous silicon layer heavily doped with n-type impurities, followed by etching leaving a region corresponding to the gate electrode to form a semiconductor layer And depositing a metal layer on the semiconductor layer, and etching the metal layer to form a source electrode overlapping the gate electrode and a drain electrode not overlapping the gate electrode to face each other, and a part corresponding to the gate electrode. The n + hydrogenated amorphous silicon layer is etched to expose the semiconductor layer of the region. Defined channel portion, it characterized in that it comprises the step of forming the ohmic contact layer.

In the method of manufacturing a thin film transistor according to an embodiment of the present invention, the source electrode and the drain electrode are preferably in a symmetrical shape facing each other, and more preferably in the shape of a bar with a central portion bent.

An array substrate for a liquid crystal display according to an exemplary embodiment of the present invention includes a transparent insulating substrate, a gate line arranged on the transparent insulating substrate, a data line defining a pixel region orthogonal to the gate line, and the gate line. A gate electrode connected to the gate electrode, a semiconductor layer formed on the gate electrode, a source electrode branched from the data line, and overlapping the gate electrode on the semiconductor layer, and positioned on the semiconductor layer at regular intervals. A thin film transistor facing the gate electrode, the drain electrode formed to not overlap the gate electrode, the thin film transistor positioned at an intersection of the gate line and the data line, and a pixel electrode formed in the pixel area and in contact with the drain electrode. It is characterized by including.

An array substrate for a liquid crystal display device according to another embodiment of the present invention includes a transparent insulating substrate, a gate line arranged on the transparent insulating substrate, a data line defining a pixel region orthogonal to the gate line, and the gate line. And a common line facing the gate line with the pixel region interposed therebetween, a gate electrode connected to the gate line, a semiconductor layer formed on the gate electrode, and branched from the data line. A source electrode formed on the layer to overlap the gate electrode, a source electrode disposed on the semiconductor layer to face the source electrode at regular intervals and not to overlap the gate electrode, wherein the gate line and the data A thin film transistor positioned at an intersection of the lines and the crab A pixel line arranged to be in contact with the drain electrode while being arranged in parallel with a line, a pixel electrode which is branched from the pixel line, and which is formed to be parallel to the data line on the pixel area, and is branched from the common line, And a common electrode formed on the region to cross the pixel electrode.

An array substrate for a liquid crystal display device according to another exemplary embodiment of the present invention has a transparent insulating substrate, a gate line arranged in rows on the transparent insulating substrate, and a central portion thereof bent, and form a column with the gate line. A data line crossing and defining a pixel region, a common line formed to surround the pixel region, a gate electrode connected to the gate line, a semiconductor layer formed on the gate electrode, and branched from the data line, A source electrode formed on the semiconductor layer to overlap the gate electrode, a drain electrode disposed on the semiconductor layer to face the source electrode at regular intervals, and not to overlap the gate electrode, wherein the gate line and the data line are provided. A thin film transistor positioned at an intersection of the gate and the gate la A pixel line arranged to be in contact with the drain electrode, the pixel line formed to contact the drain electrode; And a common electrode formed on the region to cross the pixel electrode.

In an array substrate for a liquid crystal display device according to an embodiment, another embodiment, or another embodiment of the present invention, the source electrode and the drain electrode preferably have a symmetrical shape facing each other, and the center of the liquid crystal display device may have a bar shape having a centered shape. More preferred.

Specific details of other embodiments are included in the detailed description and the drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. Like reference numerals refer to like elements throughout.

Hereinafter, a thin film transistor, a manufacturing method thereof, and an array substrate for a liquid crystal display device using the same according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a plan view illustrating some pixels of the liquid crystal display according to the exemplary embodiment, and illustrates the pixel region P of the array substrate for the liquid crystal display device applied to the TN structure.

Referring to FIG. 4, the pixel region P is a region where the gate line 120 and the data line 130 cross each other, and the thin film transistor (P) is formed at the intersection of the gate line 120 and the data line 130. 140 is configured.

The pixel area P is made of a transparent conductive metal having a relatively high transmittance of light such as indium-tin-oxide (ITO) to contact the thin film transistor 140 through the contact hole CH. The electrode 150 is configured.

The detailed configuration of the thin film transistor 140 will be described with reference to FIGS. 5 to 8.

FIG. 5 is a plan view illustrating the thin film transistor of FIG. 4, FIG. 6 is a cross-sectional view illustrating the II-II 'surface of FIG. 5, and FIG. 7 is a cross-sectional view showing the III-III' surface of FIG. 5.

5 to 7, the thin film transistor 140 may include a gate electrode 141 formed on the transparent insulating substrate 100, a gate insulating layer 110 formed on the gate electrode 141, and a semiconductor layer 144. ), The ohmic contacts 145 and 146, the source electrode 142, the drain electrode 143, and the like.

The semiconductor layer 144 is formed on the gate insulating layer 110 and is made of an undoped amorphous silicon material.

The source electrode 142 is formed on the semiconductor layer 144 so as to overlap some regions R3 and R5 of the gate electrode 141, and the drain electrode 143 forms the channel portion 144_1 of the semiconductor layer 144. It is formed so as not to overlap the gate electrode 141 while facing the source electrode 142 at regular intervals between them (see R4 and R6).

Here, the gate electrode 141 is formed as part of the gate line 120 shown in FIG. 5, and the source electrode 142 branching from the data line 130 near the gate electrode 141 is the gate electrode 141. It is formed so as to overlap by a predetermined area (R3, R5), the drain electrode 143 is formed in a position facing the source electrode 141.

The portion overlapping with the drain electrode 143 on the gate electrode 141 is removed by etching so that the gate electrode 141 overlaps the source electrode 142 by a predetermined area (R3, R5) and the drain electrode 143. Do not overlap with (see R4, R6).

Through this structure, the parasitic capacitance Cgd between the gate electrode 141 and the drain electrode 143 may be minimized to lower the feed through voltage ΔVp.

That is, since the gate electrode 141 does not exist at the bottom of the drain electrode 143 connected to the pixel electrode 150, as shown in FIGS. 6 and 7, the gate electrode having the gate insulating layer 110 interposed therebetween ( The parasitic capacitance Cgd formed by the 141 and the drain electrode 143 is not generated.

When the value of the parasitic capacitance Cgd is 0, the value of the feed through voltage DELTA Vp becomes 0 as a result of Equation 1, so that the DC voltage remaining in the liquid crystal display is reduced, thereby improving afterimages. have.

In this way, the overlap area between the drain electrode 143 and the gate electrode 141 is eliminated to induce the parasitic capacitance Cgd generated in the overlap area to have a value of 0, and decrease ΔVp caused by the parasitic capacitance Cgd to reduce the image quality. Is to implement

Ohmic contact layers 145 and 146 are formed at the interface between the source electrode 142 and the drain electrode 143 and the semiconductor layer 144, and n + hydrogenated amorphous silicon in which n-type impurities are heavily doped. Made of matter.

Although not shown, a protective film made of an inorganic insulating material or an organic insulating material such as silicon nitride film (SiNx) is formed on the thin film transistor 140, and the contact hole CH exposing the drain electrode 143 is formed in the protective film. The pixel electrode 150 is formed on the upper surface of the pixel electrode 150 to be in contact with the drain electrode 143 through the contact hole CH.

Here, the source electrode 142 and the drain electrode 143 is configured to have a symmetrical shape facing each other as shown in Figure 5, it is preferable to optimize to reduce the area occupied by the two electrodes (142, 143), the center It is more preferable to comprise in the shape of a curved bar.

More specifically, the source electrode 142 and the drain electrode 143 are configured such that opposite portions except for portions respectively connected to the data line 130 and the pixel electrode 150 have symmetrical shapes. A portion of the drain electrode 143 formed in the gate line 120 side is formed in a curved bar shape, and a portion formed in the pixel electrode 150 side extends to have a larger area to form the contact hole CH. Make sure you have a range.

Such a symmetrical structure is obtained when a carrier is transferred from the data line 130 to the pixel electrode 150 through the symmetrical shapes of the source electrode 142 and the drain electrode 143 and the data line at the pixel electrode 150. When the carrier is transferred toward the 130, the condition is geometrically identical in the distance between electrodes or the width of the electrodes forming the channel part 144_1.

By reducing the distance between the electrodes and extending the width of the electrodes, shortening the length of the channel portion 144_1 on the semiconductor layer 144 and increasing the width of the channel portion 144_1 has a significant effect on image quality. Since the operation of the structure is improved, the shape of the source electrode 142 and the drain electrode 143 may be modified into a symmetrical structure to configure the channel portion 144_1 having a short length and a large width, thereby improving the operation of the thin film transistor.

On the other hand, since the current flowing when the voltage is applied is proportional to the electrode width to the distance between the electrodes, the electrode width is maintained to a certain degree to ensure a certain amount or more of the current flowing from the source electrode 142 to the drain electrode 143. .

FIG. 8 is a cross-sectional view illustrating a channel portion of a semiconductor layer in FIG. 7.

Referring to FIG. 8, the semiconductor layer 144 has a carrier formed by the light emitted from the primary channel region 144_2 formed by the voltage applied to the gate electrode 141 and the backlight unit BL disposed below. It may be divided into the generated secondary channel region 144_3.

The secondary channel region 144_3 is a portion which does not overlap with the gate electrode 141, and there is no gate electrode 141 at the bottom of the drain electrode 143, so that the primary channel region 144_2 of the semiconductor layer 144 is more conventional than the conventional one. Carrier in silicon located in the secondary channel region 144_3 formed by the backlight unit BL at the bottom compensates it even if it is not greatly opened to the bottom of the drain electrode 143.

Conventionally, accurate switching control of the thin film transistor has been difficult due to the light leakage current generated by the backlight unit. However, in the present invention, the overlap area between the gate electrode 141 and the drain electrode 143 is eliminated, and thus the current reduced is reduced. By replacing with leakage current, malfunctions caused by conventional optical leakage current can be minimized.

9 is a flowchart illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention.

First, in step S100, after the gate electrode layer is deposited on the transparent insulating substrate 100, the gate electrode 141 is formed by patterning the gate electrode layer deposited by a photolithography process and an etching process using a first mask.

Next, in step S110, the gate insulating layer 110 is formed on the entire surface of the transparent insulating substrate 100 including the gate electrode 141.

Next, in step S120, the ohmic contact layer 145 or 146 of the n + hydrogenated amorphous silicon material in which the semiconductor layer 144 of the undoped amorphous silicon material and the n-type impurities are heavily doped on the gate insulating layer 110 is formed. The semiconductor layer 144 and the ohmic contact layer 145 except for the region corresponding to the gate electrode 141 and the region where the source and drain electrodes 142 and 143 are to be formed using the second mask. 146) is etched and patterned.

Next, in step S130, after depositing the metal layer, a portion of the region overlaps with the gate electrode 141 by etching the deposited metal layer using the third mask, and does not overlap the gate electrode 141. The drain electrodes 143 are formed to face each other.

Next, in step S140, back channel etching (BCE) is performed on the ohmic contacts 145 and 146 in the region corresponding to the gate electrode 141 using the source and drain electrodes 142 and 143 as masks. The channel portion 144_1 of the semiconductor layer 144 is defined by removing a process to expose a portion of the semiconductor layer 144 to complete the ohmic contacts 145 and 146.

Thereafter, an insulating material is coated to form a protective film, and a contact hole CH exposing the drain electrode 143 is formed in the protective film by using a fourth mask. The transparent conductive layer is deposited and the pixel electrode 150 connected to the drain electrode 143 through the contact hole CH is formed using the fifth mask.

The thin film transistor 140 described with reference to FIGS. 5 through 9 has not only a TN structure as shown in FIG. 4 but also a liquid crystal having various structures such as IPS (In-Plane Switching) or S-IPS II (Super In-Plane Switching II) structure. It can be extended to the display device.

In the case of the IPS or S-IPS II structure, since the driving voltage is relatively higher than that of the TN structure, and the feed through voltage ΔVp is also increased, the thin film transistor 140 of the present invention is applied to the parasitic capacitance Cgd. The increase in the feed through voltage DELTA Vp can be suppressed more efficiently.

10 and 11 are modified examples of the array substrate for the liquid crystal display device to which the thin film transistor 140 is applied.

FIG. 10 is a plan view illustrating some pixels of a liquid crystal display according to another exemplary embodiment, and illustrates a pixel area P of an array substrate for a liquid crystal display device applied to an IPS structure.

Referring to FIG. 10, in an array substrate for a liquid crystal display according to another exemplary embodiment, the gate lines 121 and the common lines 160 are arranged in parallel in the horizontal direction, and the data lines 131 in the vertical direction. The gate line 121 and the common line 160 are vertically arranged.

On the pixel area P, the common electrodes 161 branched from the common line 160 and the pixel electrodes 152 branched from the pixel line 151 in contact with the thin film transistor 140 are alternately formed.

FIG. 11 is a plan view illustrating some pixels of a liquid crystal display according to another exemplary embodiment, and illustrates a pixel region P of an array substrate for a liquid crystal display device applied to an S-IPS II structure.

The gate line 122 and the data line 132 are formed to cross each other to define the pixel region P, and the thin film transistor 140 is formed at the intersection of the two lines 122 and 132. The common line 162 includes two horizontal lines arranged in parallel with the gate line 122 and two vertical lines formed in a curved structure to connect the common lines 162 to surround the pixel area P. The pixel electrode 154 and the common electrode 163 are alternately formed on (P) to implement a wide viewing angle.

In more detail, the gate line 122 and the two lines of the common line 162 are parallel to each other, and the curved data line 132 is parallel to the other two lines of the common line 162. In the common line 162, the pixel electrode 154 is branched from the pixel line 153 in which the common electrode 163 is disposed in parallel with the gate line 122.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. You will understand that.

Therefore, it should be understood that the above-described embodiments are provided so that those skilled in the art can fully understand the scope of the present invention. Therefore, it should be understood that the embodiments are to be considered in all respects as illustrative and not restrictive, The invention is only defined by the scope of the claims.

Since the thin film transistor according to the preferred embodiment of the present invention has no overlapping area between the gate electrode and the drain electrode, the parasitic capacitance Cgd may be minimized.

The method for manufacturing a thin film transistor according to a preferred embodiment of the present invention can efficiently manufacture such a thin film transistor.

The array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention may improve the image quality by reducing the feed through voltage ΔVp and resolving flicker or afterimage using the thin film transistor.

Claims (15)

A gate electrode formed on the transparent insulating substrate; A gate insulating film formed on an entire surface of the transparent insulating substrate covering the gate electrode; A semiconductor layer formed on the gate insulating layer and formed of an undoped amorphous silicon material, wherein the region corresponding to the gate electrode forms a channel portion; A source electrode formed on the semiconductor layer to overlap the gate electrode; A drain electrode disposed on the semiconductor layer to face the source electrode at a predetermined interval and not overlap with the gate electrode; And A resistive contact layer formed at an interface between the source electrode and the drain electrode and the semiconductor layer, the resistive contact layer comprising an n + hydrogenated amorphous silicon material doped with a high concentration of n-type impurities, wherein the source electrode and the drain electrode face each other; The thin film transistor according to claim 1, wherein the symmetric shape is a point symmetric shape. delete The method of claim 1, The source electrode and the drain electrode, A thin film transistor, characterized in that the center is a curved bar. Forming a gate electrode on the transparent insulating substrate; Forming a gate insulating film on an entire surface of the transparent insulating substrate covering the gate electrode; After depositing an undoped amorphous silicon layer on top of the gate insulating layer and an n + hydrogenated amorphous silicon layer doped with a high concentration of n-type impurities, the semiconductor layer is etched while leaving a region corresponding to the gate electrode. Forming; After depositing a metal layer on the semiconductor layer, etching the metal layer to form a source electrode overlapping the gate electrode and a drain electrode not overlapping the gate electrode; And Etching the n + hydrogenated amorphous silicon layer to expose a semiconductor layer of a portion corresponding to the gate electrode to define a channel portion, and forming an ohmic contact layer, wherein the source electrode and the drain electrode face each other. And forming a symmetrical shape, wherein the symmetrical shape is a point symmetrical shape. delete 5. The method of claim 4, The source electrode and the drain electrode, A method of manufacturing a thin film transistor, characterized in that the center portion is formed in the shape of a curved bar. Transparent insulating substrates; A gate line arranged on the transparent insulating substrate; A data line defining a pixel area orthogonal to the gate line; A gate electrode connected to the gate line, a semiconductor layer formed on the gate electrode, a source electrode branched from the data line and formed to overlap the gate electrode on the semiconductor layer, and positioned on the semiconductor layer at regular intervals A thin film transistor facing the source electrode and having a drain electrode formed so as not to overlap the gate electrode and positioned at an intersection of the gate line and the data line; And And a pixel electrode formed in the pixel region and in contact with the drain electrode, wherein the source electrode and the drain electrode are symmetrical to face each other. Transparent insulating substrates; A gate line arranged on the transparent insulating substrate; A data line defining a pixel area orthogonal to the gate line; A common line formed to be parallel to the gate line and facing the gate line with the pixel region therebetween; A gate electrode connected to the gate line, a semiconductor layer formed on the gate electrode, a source electrode branched from the data line, and formed on the semiconductor layer so as to overlap the gate electrode, and positioned on the semiconductor layer at a predetermined interval A thin film transistor facing the source electrode and having a drain electrode formed so as not to overlap with the gate electrode and positioned at an intersection of the gate line and the data line; A pixel line arranged in parallel with the gate line and in contact with the drain electrode; A pixel electrode branched from the pixel line and formed to be parallel to the data line on the pixel area; And A common electrode branched from the common line, the common electrode formed on the pixel region so as to cross the pixel electrode, and wherein the source electrode and the drain electrode are symmetrical to face each other. . Transparent insulating substrates; Gate lines arranged in rows on the transparent insulating substrate; A data line having a center shape bent and intersecting with the gate line in a column to define a pixel area; A common line formed to surround the pixel area; A gate electrode connected to the gate line, a semiconductor layer formed on the gate electrode, a source electrode branched from the data line, and formed on the semiconductor layer so as to overlap the gate electrode, and positioned on the semiconductor layer at a predetermined interval A thin film transistor facing the source electrode and having a drain electrode formed so as not to overlap with the gate electrode and positioned at an intersection of the gate line and the data line; A pixel line arranged to be parallel to the gate line and formed to contact the drain electrode; A pixel electrode branched from the pixel line and formed to be parallel to the data line on the pixel area; And A common electrode branched from the common line, the common electrode formed on the pixel region so as to cross the pixel electrode, and wherein the source electrode and the drain electrode are symmetrical to face each other. . delete The method according to any one of claims 7 to 9, The source electrode and the drain electrode, An array substrate for a liquid crystal display device, characterized by a symmetrical shape facing each other and having a bar shape in which a central portion thereof is bent. delete delete The method according to any one of claims 7 to 9, The symmetrical shape is a point symmetrical shape, the array substrate for a liquid crystal display device. 12. The method of claim 11, The symmetrical shape is a point symmetrical shape, the array substrate for a liquid crystal display device.

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