KR101163855B1 - CMOS Image Sensors with Floating Base Readout Concept - Google Patents

Abstract

The present invention is a solid-state CMOS image sensor, specifically only two signal lines per pixel, pinned photodiodes for sensing light and floating base bipolar transistors for sensing charge. A CMOS image sensor pixel having a base bipolar transistor and not having a reset transistor and an address transistor will be described in detail. Floating base bipolar transistors provide pixels with significant gains, which increase pixel sensitivity and reduce noise. The pixel also has a vertical blooming control structure integrated therein for efficient blooming suppression. The pixel outputs are connected to a common column signal line, which is limited by special current sensing CDS circuits, which are used to reduce emitter leakage currents. Thus, pixels have high sensitivity, high response uniformity, low noise, very efficient layout, and can be substantially reduced in size as compared to conventional pixels.

Description

CMOS Image Sensors with Floating Base Readout Concept

The present invention relates to solid state image sensors, in particular CMOS image sensors having high resolution, high performance, and very small pixel sizes. In particular, the present invention relates to pixels having only one address line and only one column output line and vertical blooming per pixel, and no additional charge transfer and reset lines. The invention also relates to a pixel with an integrated bipolar gain stage wherein the charge received from the pinned photodiode is multiplied several times before the signal is transferred onto a common column output line and processed by the current sense CDS circuit. will be.

Conventional image sensors sense light by converting colliding photons into electrons that are integrated (assembled) in the sensor pixels. After completion of the integration cycle, the collected charge is converted to a voltage, which is supplied to the output terminal of the sensor. In conventional CMOS image sensors, charge-voltage conversion is achieved directly at the pixels themselves, and analog pixel voltages are transferred to the output terminals through various pixel addressing and scanning schemes. The analog signal may also be on-chip converted to a digital signal before reaching the chip output. The pixel has a source follower that drives the sense line connected to the pixel by a suitable addressing transistor. After the charge-to-voltage conversion is completed and the resulting signal is transmitted to the pixel, the pixel is reset to prepare for the accumulation of new charge. For a pixel using a floating diffusion (FD) as the charge detection node, the reset is achieved by turning on a reset transistor that instantaneously conductively connects the FD node to a reference voltage. This step removes the collected charges. However, this step generates kTC-reset noise as is well known in the art. kTC noise must be removed from the signal by a correlated double sampling (CDS) signal processing technique to achieve the desired low noise performance. Conventional CMOS sensors using the CDS concept should have four transistors (hereinafter referred to as "4T") in the pixel. An example of a 4T pixel circuit can be found in Guidash US Pat. No. 5.991,184.

1 is a simplified illustration of a cross-sectional view of a prior art pinned photodiode (photosensitive device) and associated pixel circuitry. The p-type silicon substrate 101 disposed over the p + substrate 123 has a shallow trench isolation (STI) region 102 etched at its surface and filled with silicon dioxide 103. Silicon dioxide 103 also covers the remaining surface of the pixel. The shallow P + doped region 104 passivates not only the pixel surface but also the walls and bottom of the STI region. Photo-generated charge collects in the n-type doped region 105 of the pinned photodiode. Once the charge integration cycle is complete, charge from this region is transferred to the floating diffusion (FD) region 106 by momentarily turning on the gate 107. FD is reset to the appropriate potential Vdd by transistor 118, and a change in the FD potential is sensed by transistor 114. A capacitor (Cs) 119 connected between node 117, which is Vdd, and node 113, which is FD, is used to adjust the conversion gain of the pixel. This capacitor can be omitted from the circuit if necessary. The pixel is addressed via the select transistor 115. The control signal is supplied to the pixel via the transfer gate bus (Tx) 112, the reset gate bus (Rx) 120, and the address gate bus (Sx) 121. The output from the pixel is supplied to the pixel column bus 116. When photons 122 impinge on the pixels, photons 122 penetrate into the silicon bulk and produce electron-hole pairs depending on their wavelength. Electrons are generated in the depleted region 108 as well as in the depleted region of silicon. Next, electrons 110 generated in the non-depletion region of silicon diffuse to the edge 109 of the depletion region, where the electrons are quickly swept into the dislocation wall located in the n-type region 105. In addition, electrons generated in the neutral non-depletion region may also diffuse horizontally to contribute to pixel cross talk. For this reason, the depletion region depth Xd is formed at a suitable value such that this unwanted phenomenon is minimized.

As described above, with 4T integrated into the pixel, the pixel has a reset line 120, a charge transfer line 112 and an address line 121 in a row direction for its operation, and the column It has 117 and Vout lines 116 in the column direction. It is possible to share the corresponding transistors and some of these lines between neighboring pixels, but this creates another difficult problem with interconnect lines in the pixels. An increased number of row lines and column lines consume significant pixel area, thereby significantly reducing the pixel active area that could have been used for charge storage and light sensing.

After all, the minimum size of a pixel is determined by the minimum line width and space.

It is an object of the present invention to overcome the limitations of the prior art.

Another object of the present invention is to provide a practical application having a pixel having a very small pixel size and having only one row address line and only one column output line per pixel (or photosite) and no reset transistor and no address transistor. It is to provide a CMOS image sensor.

Yet another object of the present invention is to use a pinned photodiode for light sensing in conjunction with a floating base bipolar transistor integrated in each pixel, providing a charge gain and thus reducing pixel noise while increasing pixel sensitivity. It is to provide an image sensor.

Yet another object of the present invention is to have a vertical blooming control scheme integrated into each pixel and to include a current sensing CDS circuit connected at the interface with the horizontal readout circuit to reduce emitter leakage current and column-column nonuniformity. It is to provide a CMOS image sensor to achieve a minimum of.

1 is a simplified cross-sectional view and associated pixel circuit diagram of a prior art CMOS image sensor pixel having a pinned photodiode used in a four transistors (4T) pixel structure.
Figure 2 is a floating base bypass according to one embodiment of the invention, having a pinned photodiode and associated column current sensing CDS circuitry necessary to reduce column leakage current and minimize fixed pattern noise (FPN) of the column. Simplified cross-sectional view of a polar transistor CMOS image sensor pixel.
3 is a simplified diagram and timing diagram of an output waveform for operating a new floating base bipolar transistor CMOS image sensor pixel that includes the operation of a column current sensing CDS circuit.
4 is a simplified illustration of one possible implementation of a floating base bipolar transistor CMOS sensor pixel as it is disposed in a conventional image sensor array (the figure is not scaled and of any structure that may be located on a silicon substrate). Does not show features).

In the present invention, different approaches are described for constructing a small pixel size CMOS image sensor, which addresses this difficulty and provides a simpler and more practical solution than conventional approaches. The present invention provides smaller pixels with improved charge storage capacity, increased light aperture response and increased sensitivity.

Unlike the prior art, an important point in the present invention is to remove the reset transistor and the address transistor from the pixel and replace the charge sensing transistor with a bipolar transistor with a floating base. Thus, it is possible to operate a pixel having only one row address line and only one column output line. The column output line is common for all pixel emitters in one column line, thus no addressing transistor is required.

In addition, by integrating the bipolar transistor into the pixel, it is possible to obtain a significant charge gain before the signal is transferred onto the column output line, thereby increasing the sensor sensitivity. As the new pixel does not have a reset transistor, no kTC noise occurs and improved noise performance is achieved. Similar ideas have previously been proposed for using bipolar transistors to sense charge. For example, US 6064053, US 5587596 or US 5608243 to Chi. Other similar patents do not have a pinned photodiode or still have a reset transistor or an address transistor. Using a pinned photodiode in this new floating base pixel allows full charge transfer without leaving charge on the photodiode, so that no kTC noise occurs.

Another important aspect of the present invention, distinguished from the prior art and capable of actual design, is blooming control. Pixel blooming control is achieved by vertically draining excess charge to a particular n + buried electrode located at a depth in the silicon bulk beneath each photodiode. It also eliminates the need for upper blooming control bias lines, thus maintaining the minimum number of control lines per pixel.

Finally, it is important to distinguish the present invention from the prior art by implementing a special column current read CDS circuit at the column line interface with horizontal readout circuits. This circuit reduces the emitter-base leakage current of all column bipolar transistors and senses only the photo-induced charge transferred from the pinned diode to the floating base of the specially selected bipolar transistor. This circuit is also important for removing response nonuniformity between columns.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 illustrates a cross-sectional view of a pixel and associated column interface circuitry in accordance with the present invention. P-type silicon substrate 201 disposed over p + substrate 214 has a shallow trench isolation (STI) region 202 etched at its surface and filled with silicon dioxide 203. Silicon dioxide 203 also covers the remaining surface of the pixel. The shallow P + doped region 204 passivates not only the pixel surface but also the walls and bottom of the STI region.

In addition, P + doped region 204 extends below floating base region 213 to provide collector region 204A, such that collector region 204A, emitter region 206 and floating base region 213 are vertical. It forms a floating base bipolar transistor.

Photoelectric charges collect in the n-type doped region 205 of the pinned photodiode. Once the charge integration cycle is complete, charge from this region is transferred to the FB region 213 by momentarily turning on the gate 207. When photons 217 impinge on the pixels, these photons penetrate into the silicon bulk and produce electron-hole pairs depending on their wavelength. Electrons are generated in the depletion region 208 as well as in the non-depletion region of silicon. Next, electrons 210 generated in the non-depletion region of silicon diffuse to the edge 209 of the depletion region, where the electrons are quickly swept into the dislocation wall located in the n-type doped region 205. In addition, another electron 218 generated in the neutral non-depletion region may also spread horizontally, contributing to pixel cross talk. For this reason, the depletion region depth Xd is formed at a suitable value such that this unwanted phenomenon is minimized.

If the photodiode well capacitance overflows with charge, even if the transfer gate 207 is off, this overflow “blooming” signal is below the transfer gate 207 in the FB region 213. It will be possible to flow into). This causes false leakage current in column line 216, which has the opposite effect on normal signals from other pixels connected to the same column line. Therefore, it is desirable to prevent this phenomenon. This is accomplished by placing an n + drain 215 under each pixel. The n + drain 215 for blooming-prevention is biased to a suitable voltage level so that the overflow charge does not flow into the FB region 213 but into the n + drain 215 as desired. The electrical connection to this drain is usually made around the pixel array as the blooming current is very low and no metal lines need to be added to the pixels.

The signal electrons transferred to the FB region 213 of the bipolar transistor cause a decrease in the internal potential barrier in this region 213 followed by hole injection from the emitter region 206 to the FB region 213, and also The hole is lowered into the collector region 204A to meet the majority carrier present in the collector region 204A. The flow of holes through the FB region 213 into the collector region 204A continues until the recombination process of electrons and holes in the FB region 213 removes all transmitted electrons. In essence this changes the potential of the FB region 213. The possibility of electron recombination depends on the doping concentration and the appearance of the FB region 213, which can be made relatively small. As a result, the number of holes required for recombination may be large, whereby a significant gain of the original optoelectronic signal is obtained. This is a well-known principle in the operation of a general bipolar transistor, but here, in the case of a floating base that is not connected to any circuit node. This is an advantage, since the base-emitter capacitance is usually very small, resulting in very small kTC noise.

The emitter region 206 of the floating base bipolar transistor is connected to the current sense CDS circuit 225 via a common column line 216. This circuit 225 is a circuit driving in the digital domain in accordance with a particular multipoint sampling and calculation algorithm. This circuit 225 includes a reference n-channel transistor 227, which sets the reference voltage bias of the column output line 216 according to the bias 226 applied to its gate. The drain of this transistor 227 is connected to a p-channel current mirror formed by transistors 228 and 229, which is biased at the Vdd bias level supplied to the circuit by the Vdd terminal 235. The output of the current mirror is connected to a node 230 having a reset transistor 232 and an integrated capacitor 231 connected thereto. When a pulse is applied to the gate terminal 234 of the reset transistor 232, the capacitor Cs (231) is reset. This is always done before the pixel signal is read. When charge is transferred from the photodiode to the base of the FB transistor, the resulting emitter current is mirrored by the current mirror and charges the integrated capacitor with the corresponding voltage appearing on node 230. This voltage signal is supplied to the CDS circuitry 236 which further processes the signal.

For clarity, a diagram showing the output voltage on node 230 and a timing diagram of the circuit operation are shown in FIG. The pulse 301 represents the reset pulse Vrst applied to the reset terminal 234. Pulse 302 represents the charge transfer pulse Vt applied to pixel transfer gate 207. Pulse 303 is a reference level sampling pulse Vr, pulse 304 is a signal sampling pulse Vs, and these two pulses 303, 304 are applied to the gate of the reference n channel transistor 227 in the CDS circuit 225. Pulse.

Graph 309 represents the voltage appearing on integrated capacitor Cs 231. The function of this circuit is as follows. After the reset pulse 301 turns off, the voltage on capacitor Cs begins to rise due to the leakage current of all emitters connected to the common column output line. This voltage is sampled by pulse 303 at level 306. After this cycle is completed, capacitor Cs 231 is reset and begins to re-integrate the leakage signal. However, after applying the charge transfer pulse 302 to the selected pixel, the voltage on the capacitor begins to rise much faster from the level 307 due to the current corresponding to the leakage current and the signal current from the specially selected FB transistor emitter. . This voltage is sampled by pulse 304 at level 308. Next, the light guidance signal is the difference between level 308 and level 306. However, since there are many emitters connected to one column output line, the leakage current will be significant. To minimize this problem, charge transfer operations from selected pixel rows are applied to the transfer gates of all other unselected sensors. The amplitude of this pulse 311 is directly below the charge transfer threshold of the transfer gate. This pulse causes all unselected FBs to be slightly reverse biased, typically due to the pulses supplied through the capacitance Cgb 219 formed between the transfer gate 207 and the FB region 213. The small reverse bias significantly reduces the total leakage on the sense line and allows only the leakage of the transistor of the selected row to be present.

The role of the CDS circuit 236 described above is to eliminate this remaining leakage signal. Leakage signal reduction is performed by the CDS circuit shown by block 236 and the output is shown at terminal 237. In addition, by changing the signal on the capacitor Cs to a digital value by digital reduction, more complicated signal processing is possible. In addition, the leak signal can be sampled at more instants, such as before and after the charge transfer gate pulse is applied to the pixel, and more sophisticated nonlinear calculations can be used for more accurate leakage current removal from the signal. Can be.

Finally, to clarify the invention, an example of a possible pixel layout embodiment is shown in FIG. The photodiode region 403 that receives light is outlined by an active region boundary 401 and an edge of a poly-silicon transfer gate 402. The floating base of the FB transistor is a region 404 with a p + diffusion emitter region 405. A contact region 406 connects the emitter 405 and the column bus line 407 formed by the first metal layer M1. This metal covers the entire transistor base region and also partially covers the poly-silicon transfer gate 402. This property is important for the light blocking effect and also optical crosstalk. Contact with the poly-silicon transfer gate 402 is achieved through the opening 410, and contact with the second metal layer M2 bus line 408 is also through the M1 pad 409. The nearly circular eight-sided shape of the photosensitive photodiode region with the diagonal arrangement of the FB bipolar transistors is another advantage of this pixel. This property provides a good match with a structure having an efficient light concentrating ability by microlenses, which are usually disposed on photodiodes. The diagonal arrangement of the FB transistors is usually made in the region where the efficiency of the microlens concentration capability is the lowest, and accordingly, no additional light loss occurs by this structure. Of course, other photodiode geometries are also possible with this pixel, which is well known to those skilled in the art, but the diagonal arrangement of charge sensing transistors is particularly effective only with this pixel. to be.

Describes preferred embodiments of a novel CMOS sensor pixel having a pinned photodiode and an FB bipolar transistor for sensing charge, with associated column signal processing circuitry, having only one address line and only one output line per pixel. It is intended to be illustrative and not limiting, and one of ordinary skill in the art may make modifications and variations in light of the above description. It is, therefore, to be understood that changes may be made in the specific embodiments of the invention described which are within the scope and spirit of the invention as defined in the appended claims.

As discussed above, according to the present invention, a practical CMOS image sensor having a very small pixel size and a pixel having only one row address line and only one column output line per pixel and no reset transistor and no address transistor A device is provided and also uses a pinned photodiode for light sensing with a floating base bipolar transistor integrated in each pixel to provide a charge gain and thereby increase pixel sensitivity while reducing noise Is provided.

In describing the present invention in detail and characteristically as required by the patent law, the claims which are preferably protected by a patent document are described in the appended claims.

Claims (20)

Pixel for the image sensor,
A photodiode configured to receive photons and generate charge;
A charge sensing transistor comprising a floating base, a collector, and an emitter; And
A gate of a transfer transistor coupled between the floating base of the charge sensing transistor and the photodiode
Wherein the gate of the transfer transistor is configured to transfer the charge from the photodiode to the floating base of the charge sensing transistor,
The pixel causes the charge transferred to the floating base to produce electron-hole pairs, the electrons to cause the injection of holes from the emitter to the floating base, and the recombination of the electrons and the holes causes the floating Configured on the base,
The pixel is further added so that the flow of holes flowing through the floating base to the collector continues until the recombination of the holes and electrons in the floating base removes the transmitted electrons, thereby changing the potential of the floating base. Consisting of pixels for an image sensor. The method of claim 1,
And the photodiode comprises a pinned photodiode. The method of claim 1,
And the charge sensing transistor comprises a PNP type bipolar transistor. The method of claim 1,
And further comprising an anti-blooming region disposed in a portion of the substrate bulk below the photodiode, the anti-blooming region to drain overflow charge from the photodiode. Pixel configured for the image sensor. The method of claim 4, wherein
And wherein said anti-blooming region comprises an N + type region. The method of claim 1,
And the charge sensing transistor is arranged vertically. The method of claim 1,
The charge sensing transistor and the photodiode are arranged diagonally. The method of claim 1,
And the photodiode is substantially octahedral. The method of claim 1,
And a current sense correlated double sampling circuit coupled to the emitter of the charge sense transistor. The method of claim 9,
And the current sense correlated double sampling circuit is configured to operate in the digital domain according to a multipoint sampling and calculation algorithm. A method for operating a pixel in an image sensor,
Receiving photons at the photodiode;
Generating a charge in the photodiode;
Transferring the charge to a floating base of a charge sensing transistor—the charge transferred to the floating base generates electron-hole pairs, the electrons causing injection of holes from an emitter to the floating base, and the electron Recombination of the holes with the holes occurs at the floating base; And
Changing the potential of the floating base of the charge sensing transistor by the flow of holes flowing through the floating base to the collector—the flow of holes flowing through the floating base to the collector continues until the transferred electrons are removed ?
Comprising a pixel in the image sensor. The method of claim 11,
And the photodiode comprises a pinned photodiode. The method of claim 11,
And the charge sensing transistor comprises a PNP type bipolar transistor. The method of claim 11,
Venting the overflow of the charge to an anti-blooming region disposed in a portion of the substrate bulk below the photodiode. 15. The method of claim 14,
And wherein said anti-blooming region comprises an N + type region. The method of claim 11,
And the charge sensing transistor is arranged vertically. The method of claim 11,
And the charge sensing transistor and the photodiode are arranged diagonally. The method of claim 11,
And the photodiode is substantially octahedral. The method of claim 11,
Coupling a current sense correlated double sampling circuit to the emitter of the charge sense transistor. The method of claim 19,
Operating the current sense correlated double sampling circuit in the digital domain in accordance with a multi-point sampling and calculation algorithm.

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