KR101161399B1 - Led package mounting a led chip - Google Patents

Abstract

PURPOSE: A light emitting diode package in which light emitting diode chips are mounted is provided to drive the package with an alternating current by forming light emitting cells which are serially connected to each other in the light emitting diode chips. CONSTITUTION: A light emitting diode chip is located on a heat sink(13). A pair of lead frames(1) are spaced apart from the heat sink. A package main body(6) fixes the heat sink and the lead frames. A part of the chip mounting region of the heat sink and a part of the lead frames are exposed to the upper side of the package main body. The bottom region(14) of the heat sink is exposed to the lower side of the package main body.

Description

LED package equipped with LED chip {LED PACKAGE MOUNTING A LED CHIP}

The present invention relates to a light emitting diode package equipped with a light emitting diode chip. More particularly, the light emitting diode chip includes a light emitting diode chip having light emitting cells connected in series to be directly connected to an alternating current power source. The present invention relates to a light emitting diode package mounted on top of a sink and having good heat dissipation characteristics.

Recently, the use of light emitting diodes (LEDs) as a light source is increasing. The light output of such light emitting diodes is generally proportional to input power. Therefore, a high light output can be obtained by increasing the power input to the light emitting diode. However, increasing the input power increases the junction temperature of the light emitting diodes. The increase in junction temperature of the light emitting diodes leads to a decrease in photometric efficiency, which indicates the extent to which the input energy is converted into visible light. Therefore, it is required to prevent an increase in the junction temperature of the light emitting diode according to the increase of the input power. Heat sinks may be used in conjunction with the package body to increase heat dissipation efficiency. However, continuous improvement of the structure of such a heat sink is required, and in particular, a heat sink capable of preventing separation from the package body is required.

On the other hand, the light emitting diode is a semiconductor device formed of a semiconductor p-n junction structure, and emits light by recombination of electrons and holes, generally driven by a current in one direction. Thus, the use of light emitting diodes for general lighting requires an AC-DC converter, which makes it difficult to use the light emitting diodes for general lighting. Therefore, in order to use the light emitting diode for general illumination, a light emitting diode capable of driving using an AC power source without an AC-DC converter is required.

An object of the present invention is to provide a light emitting diode package that can be driven using an AC power source without an AC-DC converter.

Another object of the present invention is to provide a light emitting diode package that adopts a heat sink to increase heat dissipation efficiency and prevent the heat sink from being separated from the package body.

In order to achieve the above technical problem, the present invention provides a light emitting diode package equipped with a light emitting diode chip. The light emitting diode package, the heat sink; A light emitting diode chip mounted on the heat sink; A pair of lead frames spaced apart from the heat sink; And a package body fixing the heat sink and the pair of lead frames, wherein the chip mounting portion and the pair of lead frames of the heat sink are exposed to an upper side of the package body, and the package body is exposed. The bottom of the heat sink is exposed to the lower side of the heat sink.

The present invention also provides a light emitting diode package equipped with a light emitting diode chip having light emitting cells connected in series. The light emitting diode package includes a package body having an opening and a through hole exposed by the opening. A pair of lead frames are supported by the package body. The pair of leadframes has a pair of inner frames exposed in the opening of the package body and outer frames extending from each of the inner frames to protrude out of the package body. In addition, a heat sink is coupled through the through hole at the bottom of the package body. The heat sink has an upper surface exposed by the opening. A light emitting diode chip having a light emitting cell array connected in series is mounted on the heat sink. Bonding wires electrically connect the light emitting diode chip to the lead frame. Accordingly, it is possible to provide a light emitting diode package having high heat dissipation efficiency and which can be driven using an AC power source.

Here, the "light emitting cell" means a fine light emitting diode formed in a single light emitting diode chip. In general, the light emitting diode chip has only one light emitting diode, but in the present invention, the light emitting diode chip has a plurality of light emitting cells.

 The package body may be formed by inserting a thermoplastic resin after positioning the pair of lead frames. Thereby, the package main body which has a complicated structure can be formed easily.

The heat sink has a base coupled to the bottom of the package body, and a protrusion protruded upward from a central portion of the base and coupled to the through hole. In addition, the heat sink may have a locking step on the side of the protrusion. The catching jaw is caught by an upper surface of the package body or inserted into a sidewall of the through hole to prevent the heat sink from being separated from the package body.

On the other hand, the light emitting diode chip includes a substrate and light emitting cells electrically insulated from the substrate and spaced apart from each other on the substrate.

In one embodiment of the present invention, the light emitting diode chip may further include wirings for electrically connecting the light emitting cells in series.

In another embodiment of the present invention, a submount may be interposed between the light emitting diode chip and the heat sink. The submount may have electrode patterns corresponding to the light emitting cells, and the light emitting cells may be connected in series by the electrode patterns.

On the other hand, a molding member may cover the upper portion of the light emitting diode chip. The molding member may be located in a groove surrounded by sidewalls of the package body. The molding member may include a first molding member and a second molding member, and phosphors may be contained in the first and / or second molding members. Accordingly, a light emitting diode package emitting white light may be provided using a light emitting diode chip emitting blue light.

On the other hand, a lens may be positioned on the molding member. The lens may have various shapes according to the intended use.

According to embodiments of the present invention, it is possible to increase the heat dissipation efficiency by adopting a heat sink, to form a coupling jaw in the heat sink to prevent the heat sink from being separated from the package body, the light emitting cell array connected in series By mounting a light emitting diode chip having a light emitting diode, it is possible to provide a light emitting diode package which can be driven using a home AC power supply without an AC-DC converter.

1 and 2 are top and bottom perspective views illustrating a light emitting diode package according to an embodiment of the present invention.
FIG. 3 is an exploded perspective view illustrating the light emitting diode package of FIG. 1.
4 is a cross-sectional view of a light emitting diode chip mounted on the light emitting diode package of FIGS. 1 and 2 to explain a light emitting diode package according to an exemplary embodiment of the present invention.
FIG. 5 is a cross-sectional view of a molding member formed on the light emitting diode package of FIG. 4 and a lens mounted thereto. FIG.
6A and 6B are circuit diagrams for describing a light emitting diode chip mounted in a light emitting diode package of the present invention.
7A and 7B are cross-sectional views illustrating a light emitting diode chip according to an embodiment of the present invention.
8A and 8C are cross-sectional views illustrating a light emitting diode chip according to another embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention; The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, widths, lengths, thicknesses, and the like of components may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 and 2 are an upper perspective view and a lower perspective view for explaining a light emitting diode package according to an embodiment of the present invention, Figure 3 is an exploded perspective view for explaining a light emitting diode package according to an embodiment of the present invention. 4 is a cross-sectional view illustrating a light emitting diode chip mounted on the light emitting diode package of FIGS. 1 and 2 and connected with a bonding wire, and FIG. 5 is a molding member formed on the light emitting diode package of FIG. One cross section.

1 to 3, the light emitting diode package of the present invention includes a package body including a first package body 6 and a second package body 9. The first package body and the second package body may be manufactured separately, but may be integrally formed using an insert molding technique. When formed integrally, the package body is not separated into the first package body 6 and the second package body 9, but is shown as separated for convenience of description.

The first package body 6 has an opening 8 and has a recess formed in the upper surface thereof to receive the molding member and surrounded by an inner wall. The opening 8 may have the same area as the recessed portion, but may have a smaller area as shown. A stepped portion 7 may be formed on an inner wall of the first package body to accommodate a molding member to be described later.

The second package body 9 has a through hole 11 exposed by the opening of the first package body 6. In addition, the inner frame receiving groove 10 is formed on the upper surface of the second package body 9, the heat sink mounting groove 12 is formed on the lower surface. The inner frame receiving groove 10 is spaced apart from the through hole 11 and positioned around it.

A pair of lead frames 1 are spaced apart from each other and positioned between the first package body 6 and the second package body. The lead frame 1 has a pair of inner frames 3 exposed by the opening of the first package body 6 and an outer frame 2 extending from the inner frame to protrude out of the package body. The inner frame 3 is formed in a symmetrical structure to form a hollow portion 5 in the central portion. The inner frame 3 is seated in the inner frame receiving groove 10 so that the through hole 11 is located in the hollow part 5.

On the other hand, the inner frame 3 may each have a support 4 extending therefrom. The support 4 serves to support the lead frame 1 when a lead panel (not shown) connected with a plurality of lead frames 1 is used to mass produce a light emitting diode package. Also, as illustrated in FIGS. 1 and 2, the outer frame 2 may be bent to be surface mounted on a printed circuit board.

On the other hand, the lead frame 1 may form a symmetrical structure as shown, but is not limited thereto. In addition, the hollow part 5 surrounded by the inner frame 3 may be hexagonal as shown, but is not limited thereto, and may have various shapes such as a circle or a quadrangle.

The heat sink 13 is coupled to the second package body at the bottom surface of the second package body 9. The heat sink 13 has a base portion 14 seated in the heat sink seating groove 12 of the second package body, and protrudes upward from the center portion of the base portion so that the through hole 11 of the second package body is formed. It has a protrusion 15 inserted into and coupled to the second package body. A locking jaw may be formed on the side of the protrusion 15. The upper surface 16 of the protrusion 15 may be recessed and exposed by the opening 8 of the first package body 6.

The first and second package bodies 6 and 9 may be formed using thermal conductive plastics or high thermal conductive ceramics. The plastic may include ABS (Acrylonitrile Butadiene Styrene), LCP (Liquid Crystalline Polymer), PA (Polyamide), PPS (Polyphenylene Sulfide), TPE (Thermoplastic Elastomer), and ceramics include alumina (Al ₂ O ₃ ), carbonization Silicon (SiC) and aluminum nitride (AlN). Among the ceramics, aluminum nitride (AlN) has the same physical properties as alumina, and is more widely used than alumina in thermal conductivity.

When the first and second package bodies 6 and 9 are made of plastic, the lead frame 1 may be positioned and then formed using an insert molding technique.

On the other hand, in the case where the first and second package bodies 6 and 9 are ceramics, the first package body 6 and the second package body 9 are separately formed and then attached using an adhesive having a high adhesive strength. Can be fixed

Referring to FIG. 4, in the light emitting diode package according to the present invention, the stepped portion 7 may be formed on the inner wall of the first package body 6, which may be used to mold the molding member or to mount the lens. It is to act as necessary fixing jaw.

Meanwhile, the locking jaw 15a of the heat sink 13 may be formed on an outer surface of the protrusion 15 to be inserted and fixed to a recess formed in an inner wall of the through hole 11 of the second package body 9. have. In addition, the locking step 15a may be formed on the upper side of the protrusion 15 and may be fastened to an upper surface of the second package body 9. Accordingly, the heat sink 13 can be prevented from being separated from the package body. The locking jaw may be formed at the bottom side of the heat sink 13.

 The heat sink 13 is formed of a thermally conductive material, and in particular, may be formed of a metal or an alloy such as copper (Cu) or aluminum (Al). In addition, the heat sink 13 may be formed using a molding technique or a press working technique.

The light emitting diode chip 17 is mounted on the upper surface 16 of the heat sink 13. The light emitting diode chip 17 may be made of a compound semiconductor of (Al, In, Ga) N, and is selected to emit light of a desired wavelength. For example, the light emitting diode chip 17 may be a compound semiconductor emitting blue light. The light emitting diode chip 17 has a light emitting cell array connected in series. A light emitting diode chip having the light emitting cell array connected in series will be described in detail with reference to FIGS. 6A to 8C.

 The light emitting diode chip 17 is electrically connected to the internal frames 3a and 3b through bonding wires 19a and 19b. To this end, the light emitting diode chip 17 may have two bonding pads electrically connected to both ends of a series of light emitting cell arrays connected in series. Accordingly, an external power source may be connected to the external frames 2a and 2b to drive the light emitting diode chip 17.

 Meanwhile, a submount (not shown) having an electrode pattern formed between the light emitting diode chip 17 and the heat sink may be interposed. The bonding wires 19a and 19b may connect the submount and the internal frames 3a and 3b, and the light emitting cells may be connected in series by the electrode patterns. This will be described later with reference to FIGS. 8A to 8C.

Referring to FIG. 5, molding members 21 and 23 cover an upper portion of the light emitting diode chip 17 and are molded in a groove of the first package body 6. The molding member may include a first molding member 21 and a second molding member 23. The first and second molding members may be formed of an epoxy resin or a silicone resin, respectively, and may be formed of the same or different materials. It is preferable that the second molding member 23 has a greater hardness value than the first molding member 21. The first and second molding members may be molded in the grooves of the first package body 6 so that an interface is formed near the stepped portion 7a, respectively.

Meanwhile, phosphors may be contained in the first molding member 21 and / or the second molding member 23. In addition, a diffusion agent may be contained in the first molding member 21 and / or the second molding member 23.

The phosphor converts light emitted from the light emitting diode chip 17 into wavelength. For example, when the light emitting diode chip 17 emits blue light, the first and / or second molding member may include a phosphor for converting blue light into yellow light or converting blue light into green light and red light. . As a result, white light is emitted from the light emitting diode package to the outside.

In addition, the lens 25 is positioned on the molding member. The lens 25 is fixed to the upper step portion 7b. The lens 25 may have the shape of a convex lens, as shown in the figure, so that the light emitted from the light emitting diode chip 17 is emitted within a predetermined direction angle, and may have various shapes depending on the purpose of use. .

Hereinafter, a light emitting diode chip having light emitting cells connected in series for use in embodiments of the present invention will be described in detail.

6A and 6B are circuit diagrams for describing an operating principle of a light emitting diode chip having a plurality of light emitting cells according to embodiments of the present invention.

Referring to FIG. 6A, light emitting cells 31a, 31b, and 31c are connected in series to form a first series light emitting cell array 31, and another light emitting cells 33a, 33b, and 33c are connected in series to each other. Two series light emitting cell arrays 33 are formed. Here, the "serial light emitting cell array" means an array in which a plurality of light emitting cells are connected in series.

Both ends of the first and second series arrays 31 and 33 are connected to an AC power source 35 and a ground, respectively. The first and second series arrays are connected in parallel between the AC power source 35 and ground. That is, both ends of the first and second series arrays are electrically connected to each other.

Meanwhile, the first and second series arrays 31 and 33 are disposed to drive the light emitting cells by currents flowing in opposite directions. That is, as shown, the anode and cathode of the light emitting cells included in the first series array 31 and the anode and the cathode of the light emitting cells included in the second series array 33 are opposite to each other. Is placed.

Therefore, when the AC power source 35 is in a positive phase, the light emitting cells included in the first series array 31 are turned on to emit light, and the light emitting cells included in the second series array 33 are turned off. On the contrary, when the AC power source 35 is in a negative phase, the light emitting cells included in the first series array 31 are turned off, and the light emitting cells included in the second series array 33 are turned on.

As a result, the first and second series arrays 31 and 33 alternately turn on and off by AC power, so that the light emitting diode chip including the first and second series arrays is continuously lighted. Emits.

The light emitting diode chips consisting of one light emitting diode may be connected and driven using an AC power source as in the circuit of FIG. 6A, but the space occupied by the light emitting diode chips increases. However, the light emitting diode chip of the present invention can be driven by connecting an AC power source to one chip, so that the occupied space does not increase.

Meanwhile, although the circuit of FIG. 6A is configured such that both ends of the first and second series arrays are connected to the AC power source 35 and the ground, respectively, the both ends may be connected to both terminals of the AC power source. In addition, the first and second series arrays are each composed of three light emitting cells, but this is only an example to help explain, and the number of light emitting cells may be further increased as necessary. In addition, the number of the serial arrays may be further increased.

Referring to FIG. 6B, the light emitting cells 41a, 41b, 41c, 41d, 41e, and 41f constitute a series light emitting cell array 41. Meanwhile, a bridge rectifier including diode cells D1, D2, D3, and D4 is disposed between the AC power source 45, the series light emitting cell array 41, and the ground and the series light emitting cell array 41. The diode cells D1, D2, D3, and D4 may have the same structure as the light emitting cells, but are not limited thereto and may not emit light. An anode terminal of the series light emitting cell array 41 is connected to a node between the diode cells D1 and D2, and a cathode terminal is connected to a node between diode cells D3 and D4. Meanwhile, the terminal of the AC power supply 45 is connected to a node between the diode cells D1 and D4, and the ground is connected to a node between the diode cells D2 and D3.

When the AC power supply 45 has a positive phase, the diode cells D1 and D3 of the bridge rectifier are turned on and the diode cells D2 and D4 are turned off. Thus, the current flows to ground through the diode cell D1 of the bridge rectifier, the series light emitting cell array 41 and the diode cell D3 of the bridge rectifier.

On the other hand, when the AC power supply 45 has a negative phase, the diode cells D1 and D3 of the bridge rectifier are turned off and the diode cells D2 and D4 are turned on. Thus, current flows through the diode cell D2 of the bridge rectifier, the series light emitting cell array 41 and the diode cell D4 of the bridge rectifier to the AC power source.

As a result, by connecting the bridge rectifier to the series light emitting cell array 41, it is possible to continuously drive the series light emitting cell array 41 using the AC power supply 45. Here, although the terminals of the bridge rectifier are configured to be connected to the AC power source 45 and the ground, the terminals of the bridge rectifier may be configured to be connected to both terminals of the AC power source. Meanwhile, as the series light emitting cell array 41 is driven using an AC power source, ripple may occur, and an RC filter may be connected to prevent the ripple.

According to the present embodiment, one series of light emitting cell arrays may be electrically connected to and driven by an AC power source, and the use efficiency of the light emitting cells may be improved as compared to the light emitting diode chip of FIG. 6A.

The light emitting cells described with reference to FIG. 6A or 6B are arranged in a single light emitting diode chip. Hereinafter, a light emitting diode chip having light emitting cells connected in series will be described in detail.

7A and 7B are cross-sectional views illustrating a light emitting diode chip having light emitting cells connected in series according to an embodiment of the present invention.

7A and 7B, a plurality of light emitting cells 100-1 are spaced apart from each other on a substrate 20 and serially connected by wirings 80-1 through 80-n. To 100-n). That is, in the LED chip, the N-type semiconductor layer 40 and the P-type semiconductor layer 60 of the adjacent light emitting cells 100-1 to 100-n are electrically connected to each other, and the light emitting cells 100-n at one end thereof are electrically connected. A plurality of N-type pads 95 are formed on the N-type semiconductor layer 40, and the P-type pads 90 are formed on the P-type semiconductor layer 60 of the light emitting cell 100-1 at the other end. It includes a light emitting cell 100.

The N-type semiconductor layer 40 and the P-type semiconductor layer 60 of the adjacent light emitting cells 100-1 to 100-n are electrically connected through the metal wiring 80. In addition, in the present invention, it is effective to connect the light emitting cells 100-1 to 100-n in series to form the number of voltages capable of AC driving. According to the present invention, the number of light emitting cells 100 connected in series may vary depending on a voltage / current for driving a single light emitting cell 100 and an AC driving voltage applied to a light emitting diode chip for illumination. For example, in the 220V AC driving, 66 to 67 unit light emitting cells of 3.3V are connected in series to a constant driving current to manufacture a light emitting diode chip. In addition, in the 110V AC driving, 33 to 34 3.3V unit light emitting cells are connected in series to a constant driving current to manufacture a light emitting diode chip.

For example, as shown in FIG. 7A, in a light emitting diode chip in which the first to nth light emitting cells 100-1 to 100-n are connected in series, the P-type semiconductor layer of the first light emitting cell 100-1 ( 60, a P-type pad 90 is formed, and the N-type semiconductor layer 40 of the first light emitting cell 100-1 and the P-type semiconductor layer 60 of the second light emitting cell 100-2 are formed. It is connected via the 1st wiring 80-1. In addition, the N-type semiconductor layer 40 of the third light emitting cell 100-3 and the P-type semiconductor layer (not shown) of the fourth light emitting cell (not shown) are connected through the second wiring 80-2. . The n-type semiconductor layer (not shown) of the n-th light emitting cell (not shown) and the P-type semiconductor layer 60 of the n-th light emitting cell 100-n-1 are connected to the n-1 wiring ( N-type semiconductor layer 40 of n-th light emitting cell 100-n-1 and P-type semiconductor layer 60 of n-th light emitting cell 100-n, which are connected via 80-n-1; ) Is connected via the n-th wiring 80-n. In addition, an N-type pad 95 is formed in the N-type semiconductor layer 40 of the n-th light emitting cell 100-n.

The substrate 20 of the present invention may be a substrate on which a plurality of light emitting diode chips can be manufactured. Thus, A of FIGS. 7A and 7B show cutting regions for individually cutting the plurality of light emitting diode chips.

In addition, the LED chip described above may have rectifying diode cells (D1 to D4 in FIG. 6B) for rectifying an external AC voltage. The diode cells are arranged in the form of a rectifying bridge. Nodes of the diode cells may be connected to the N-type pad and the P-type pad of the light emitting cell, respectively. The diode cells may be light emitting cells having the same structure as the light emitting cells.

Hereinafter, a method of manufacturing a light emitting diode chip having light emitting cells connected in series will be described.

The buffer layer 30, the N-type semiconductor layer 40, the active layer 50, and the P-type semiconductor layer 60 are sequentially grown on the substrate 20. The transparent electrode layer 70 may be further formed on the P-type semiconductor layer 60. The substrate 20 may include sapphire (Al ₂ O ₃ ), silicon carbide (SiC), zinc oxide (ZnO), silicon (Si), gallium arsenide (GaAs), gallium phosphide (GaP) 0, and lithium-alumina (LiAl _2). O _{3 )} , boron nitride (BN), aluminum nitride (AlN), or gallium nitride (GaN) substrate, and may be selected according to the material of the semiconductor layer to be formed on the substrate 20. In the case of using a gallium nitride based semiconductor layer, a sapphire or silicon carbide (SiC) substrate is preferable.

The buffer layer 30 is a layer for reducing lattice mismatch between the substrate 20 and subsequent layers during crystal growth, and may be, for example, a gallium nitride layer (GaN). When the SiC substrate is a conductive substrate, the buffer layer 30 may be formed of an insulating layer, and may be formed of semi-insulating GaN. The N-type semiconductor layer 40 is a layer in which electrons are generated, and is formed of an N-type compound semiconductor layer and an N-type cladding layer. In this case, the N-type compound semiconductor layer may use GaN doped with N-type impurities. The P-type semiconductor layer 60 is a layer in which holes are formed, and is formed of a P-type cladding layer and a P-type compound semiconductor layer. In this case, AlGaN doped with P-type impurities may be used for the P-type compound semiconductor layer.

The active layer 50 is a region where a predetermined band gap and a quantum well are made to recombine electrons and holes, and may include an InGaN layer. In addition, according to the kind of material constituting the active layer 50, the emission wavelength generated by electron and hole coupling is changed. Therefore, it is preferable to adjust the semiconductor material contained in the active layer 50 according to the target wavelength.

Thereafter, a portion of the N-type semiconductor layer 40 is exposed by patterning the P-type semiconductor layer 60 and the active layers 50 using a photolithography and an etching process. In addition, a portion of the exposed N-type semiconductor layer 40 is removed to electrically insulate each of the light emitting cells 100. In this case, as shown in FIG. 7A, the exposed surface of the substrate 20 may be exposed by removing the exposed buffer layer 30, and as shown in FIG. 7B, the etching may be stopped in the buffer layer 30. When the buffer layer 30 is conductive, the exposed buffer layer 30 is removed to electrically separate the light emitting cells.

Diode cells for rectifying bridges may also be formed using the same method as the above-described manufacturing process. Of course, it is also possible to form diode cells for rectifying bridge separately using a conventional semiconductor manufacturing process.

Subsequently, the N-type semiconductor layer 40 and the P-type semiconductor layer 60 of the adjacent light emitting cells 100-1 to 100-n are formed through a predetermined bridge process or a step cover process. Conductive wires 80-1 to 80-n for electrically connecting the same. The conductive wires 80-1 to 80-n are formed using a conductive material, but are formed using a silicon compound doped with a metal or an impurity.

The bridge process is also called an air bridge process, and this process will be briefly described. First, after forming a photoresist film on the substrate on which the light emitting cells are formed, a first photoresist pattern having an opening for exposing the exposed N-type semiconductor layer and the electrode layer on the P-type semiconductor layer is formed by using an exposure technique. Thereafter, the metal material layer is thinly formed by using an electron beam evaporation technique. The metal material layer is formed on the entire surface of the opening and the photoresist pattern. Subsequently, a second photoresist pattern is formed on the photoresist pattern to expose regions between adjacent light emitting cells to be connected and the metal layer of the openings. Thereafter, gold and the like are formed using a plating technique, and then the first and second photoresist patterns are removed. As a result, only wirings connecting adjacent light emitting cells remain, and all other metal material layers and photoresist patterns are removed, so that the wirings connect the light emitting cells in a bridge form.

Meanwhile, the step cover process includes forming an insulating layer on a substrate having light emitting cells. The insulating layer is patterned using photolithography and etching techniques to form openings that expose the P-type semiconductor layer and the electrode layer on the N-type semiconductor layer. Subsequently, an electron beam deposition technique or the like is used to form a metal layer filling the opening and covering the insulating layer. Thereafter, the metal layer is patterned using photolithography and etching techniques to form interconnects that connect adjacent light emitting cells. Such a step cover process is possible in various modifications. Using the step cover process, the wiring is supported by the insulating layer, thereby increasing the reliability of the wiring.

Meanwhile, P-type pads 90 and N-type pads 95 are formed in the light emitting cells 100-1 and 100-n located at both ends, respectively, for electrical connection with the outside. The rectifying bridge diode cells may be connected to the P-type pad 90 and the N-type pad 95, respectively, and the bonding wires (19a and 19b of FIG. 4 or 5) may be connected to the P-type pad 90 and the N-type. The pads 95 may be connected to each other.

The manufacturing method of the light emitting diode chip of the present invention described above is only one embodiment, and is not limited thereto. Various processes and manufacturing methods may be changed or added according to the characteristics of the device and the convenience of the process.

For example, a plurality of vertical light emitting cells having a shape in which an N-type electrode, an N-type semiconductor layer, an active layer, a P-type semiconductor layer, and a P-type electrode are sequentially stacked are formed on a substrate, or light-emitting cells having such a structure are formed. Bonding is arranged on a substrate. Thereafter, the N-type electrode and the P-type electrode of adjacent light emitting cells may be connected by wires to connect a plurality of light emitting cells in series to manufacture a light emitting diode chip. Of course, the vertical light emitting cell is not limited to the above-described structure is possible in a variety of structures. In addition, after forming a plurality of light emitting cells on a substrate, by bonding the light emitting cells on a separate host substrate, and separating the substrate using a laser, or by using a chemical mechanical polishing technique to remove on the host substrate It is also possible to form a plurality of light emitting cells. Thereafter, adjacent light emitting cells can be connected in series by wiring.

Each of the light emitting cells 100 includes an N-type semiconductor layer 40, an active layer 50, and a P-type semiconductor layer 60 that are sequentially stacked on the substrate 20, and the buffer layer 30 includes the substrate 20. ) And the light emitting cell 100. Each of the light emitting cells 100 includes a transparent electrode layer 70 formed on the P-type semiconductor layer 60. In addition, the vertical light emitting cell includes an N-type electrode disposed under the N-type semiconductor layer.

The N-type bonding pad and the P-type bonding pad are pads for electrically connecting the light emitting cell 100 to an external metal wiring or bonding wire, and may be formed in a stacked structure of Ti / Au. The bonding pads may be formed on the N-type semiconductor layer and the P-type semiconductor layer of all the light emitting cells. In addition, the transparent electrode layer 70 serves to uniformly transfer the voltage input through the P-type bonding pad to the P-type semiconductor layer 60.

8A to 8C are cross-sectional views illustrating a light emitting diode chip 1000 having light emitting cells connected in series according to another embodiment of the present invention. The LED chip 1000 includes flip chip type light emitting cells, and the LED chip 1000 is coupled to the submount 2000 and mounted on a heat sink (FIG. 4 or 13 of FIG. 5).

Referring to FIG. 8A, a plurality of flip chip type light emitting cells are arranged on a substrate 110 of the light emitting diode chip 1000. Each of the light emitting cells includes an N-type semiconductor layer 130 formed on the substrate 110, an active layer 140 formed on a portion of the N-type semiconductor layer 130, and a P-type semiconductor layer 150 formed on the active layer 140. ). Meanwhile, a buffer layer 120 may be interposed between the substrate 110 and the light emitting cells. In this case, in order to reduce the contact resistance of the P-type semiconductor layer 150, a separate P-type electrode layer 160 may be formed on the P-type semiconductor layer 150. The P-type electrode layer may be a transparent electrode layer, but does not need to be a transparent electrode layer. The light emitting diode chip 1000 may include a P-type metal bumper 170 formed on the P-type electrode layer 150 for bumping and an N-type metal formed on the N-type semiconductor layer 130 for bumping. It further includes a bumper 180. In addition, the P-type electrode layer 160 may further include a reflecting layer (not shown) having a reflectance of 10 to 100%. In addition, a separate ohmic metal layer may be further formed on the P-type semiconductor layer 150 to facilitate supply of current.

The substrate 110, the buffer layer 120, the N-type semiconductor layer 130, the active layer 140, and the P-type semiconductor layer 150 have the same substrate 20 and semiconductor as described with reference to FIGS. 7A and 7B. It may be formed in layers.

The submount substrate 2000 includes a substrate 200 in which a plurality of N regions and P regions are defined, a dielectric film 210 formed on the surface of the substrate 200, and a plurality of electrodes connecting adjacent N and P regions. Pattern 230. The apparatus may further include a P-type bonding pad 240 extending to a P region located at one edge and an N-type bonding pad 250 extending to an N region located at the other edge.

The N region refers to a region to which the N-type metal bumper 180 of the LED chip 1000 is to be connected, and the P region refers to a region to which the P-type metal bumper 170 of the LED chip 1000 is to be connected. do.

In this case, a substrate having excellent thermal conductivity is used as the substrate 200. For example, SiC, Si, germanium (Ge), silicon germanium (SiGe), AlN, or a metal substrate can be used. As the dielectric film 210, any dielectric material through which a current flows below 1 μm may be used. Of course, the present invention is not limited thereto, and an insulating material through which no current flows can be used. In addition, the dielectric film 210 may be formed in multiple layers. When the substrate is nonconductive, the dielectric film 210 may be omitted. As the dielectric layer 210, silicon oxide (SiO ₂ ), magnesium oxide (MgO), or silicon nitride (SiN) may be used.

The electrode pattern 230, the N-type bonding pad 250, and the P-type bonding pad 240 may use a metal having excellent electrical conductivity.

Hereinafter, a manufacturing method of a sub-mount substrate for a light emitting diode chip having a flip chip type light emitting cell will be described.

The substrate 200 is formed in an uneven shape to define the N region and the P region. The N region and the P region may vary in width, height, and shape according to sizes of the N-type metal bumper 180 and the P-type metal bumper 170 of the LED chip 1000 to be bonded. . In this embodiment, the convex portion of the substrate 200 becomes the N region, and the recessed portion of the substrate becomes the P region A. The substrate 200 of this shape may be manufactured using a separate mold, or may be manufactured using a predetermined etching process. That is, after forming a mask exposing the P region on the substrate 200, a portion of the exposed substrate 200 is removed to form a recessed P region. Subsequently, removing the mask forms an N region protruding relatively to the recessed P region. In addition, the recessed P region may be formed through mechanical processing.

Thereafter, the dielectric film 210 is formed on the entire structure. In this case, when the conductive material is not used as the substrate 200, the dielectric film 210 may not be formed. In the case of using a metal substrate having excellent electrical conductivity to improve thermal conductivity, the dielectric film 210 may be formed to provide sufficient insulation.

Electrode patterns 230 are formed on the dielectric layer 210 to connect adjacent N and P regions in a pair. The electrode patterns 230 may be formed by screen printing, or after the electrode layer is deposited, the electrode patterns 230 may be formed by patterning using a photolithography and an etching process.

The P-type metal bumper 170 of the light emitting diode chip 1000 is bonded to the electrode pattern 230 on the P region, and the N-type metal bumper 180 is bonded to the electrode pattern 230 on the N region. The chip 1000 and the submount substrate 2000 are bonded. In this case, the light emitting cells of the LED chip 1000 are connected in series by the electrode patterns 230 to form an array of light emitting cells connected in series. P-type bonding pads 240 and N-type bonding pads 250 are positioned at both ends of the series-connected light emitting cell arrays and are connected to bonding wires (19a and 19b of FIG. 4 or 5, respectively).

In this case, the metal bumps 170 and 180, the electrode patterns 230, and the bonding pads 240 and 250 may be bonded through various bonding methods. For example, the metal bumps 170 and 180 may be bonded using an eutectic method using a eutectic temperature. Can be.

In this case, the number of light-emitting cells connected in series may vary depending on the power source and power to be used, and may be formed in the same number as described with reference to FIGS. 7A and 7B.

Referring to FIG. 8B, instead of arranging a plurality of light emitting cells on the substrate 110 as shown in FIG. 8A, individual light emitting cells 100a to 100c may be separately bonded on the sub-mount substrate 2000. . In addition, in the light emitting diode chip 1000 of FIG. 8A, the substrate 110 may be separated using a laser, or the substrate 110 may be removed using a chemical mechanical polishing technique. At this time, the N-type metal bumper 170 and the P-type metal bumper 180 of the adjacent light emitting cells 100a to 100c are bonded to the electrode patterns 230 formed on the sub-mount substrate 2000 to electrically connect the light emitting cells. Are connected in series.

Referring to FIG. 8C, electrode patterns 230 are formed on the flat substrate 200 on which a plurality of N regions and P regions are defined to connect adjacent N regions A and P regions B, respectively. The light emitting diode chip 1000 may be mounted on the submount substrate 2000. That is, unlike FIG. 8A, the electrode patterns 230 are formed on the substrate 200 on which the predetermined pattern is not formed, and then the N-type metal bumpers 170 of the adjacent light emitting cells of the LED chip 1000 are formed. The P-type metal bumper 180 may be electrically connected.

In addition, the N-type and P-type metal bumpers 170 and 180 are not formed in the light emitting cells in the LED chip 1000, and the metals are formed in the N region B and the P region A on the sub-mount substrate 2000, respectively. Bumpers 170 and 180 may be formed. In this case, a predetermined metal electrode (not shown) may be further formed on the N-type and P-type semiconductor layers 130 and 150 to be bonded to the metal bumpers 170 and 180.

In addition, in the present invention, a separate bridge circuit may be configured in the light emitting diode chip 1000 for use in a home power source. In addition, two or more of the series-connected light emitting cell arrays may be formed so that they may be connected in parallel to be driven by a home power source.

Claims (10)

Heat sink;
A light emitting diode chip mounted on the heat sink;
A pair of lead frames spaced apart from the heat sink; And
And a package body configured to fix the heat sink and the pair of lead frames.
The heat sink is fixed to the coupling through the through hole of the package body in the lower portion of the package body,
At least a portion of the chip mount and the pair of lead frames of the heat sink are exposed to the upper side of the package body, and the base of the heat sink is exposed to the lower side of the package body.
The heat sink is a light emitting diode package having a locking step is formed to prevent the heat sink is separated from the package body. The method according to claim 1,
The pair of lead frames are spaced apart from the top surface of the heat sink LED package. delete The method according to claim 1,
The locking step is a light emitting diode package, characterized in that formed on the outer surface of the chip mounting portion of the heat sink. The method according to claim 1,
The catching jaw is a light emitting diode package, characterized in that formed on the bottom side of the base of the heat sink. The method according to claim 1,
The pair of lead frames includes a pair of inner frames and an outer frame extending from each of the inner frames to protrude out of the package body. The method of claim 6,
The outer frame is a light emitting diode package, characterized in that protruding to the outside through the side of the package body. The method according to claim 1,
The light emitting diode package further comprises a molding member covering an upper portion of the light emitting diode chip. The method according to claim 8,
The molding member includes a first molding member disposed adjacent to the chip and a second molding member spaced apart from the chip package. The method according to claim 9,
The second molding member is a light emitting diode package, characterized in that the hardness value is larger than the first molding member.

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