KR101158751B1 - Sram using charge recycling - Google Patents

Abstract

In an embodiment, a semiconductor memory device may include a write driver providing a first swing voltage to a data bus line pair, a column selection circuit connecting the data bus line pair to a bit line pair selected according to an input address, and A plurality of subblocks connected to a selected bit line pair, each of the plurality of subblocks being configured to sense and amplify the first swing voltage of the selected bit line pair to generate a second swing voltage; And a plurality of memory cells connected to a sub-bit line pair receiving a second swing voltage and storing data according to the second swing voltage of the sub-bit line pair.

Semiconductor memory devices, charge recycling, reading, writing

Description

Semiconductor memory device using charge recycling {SRAM USING CHARGE RECYCLING}

The present invention relates to a low power semiconductor memory device using a charge recycling method.

The present invention is derived from a study conducted as part of the IT source technology development of the Ministry of Knowledge Economy. [Task management number: 2008-F-024-01, Task name: Mobile flexible input and output platform]

Static random access memory (SRAM) is a type of semiconductor memory device. Unlike DRAM, which must be updated periodically, its contents are preserved as long as power is supplied to the memory device. Since the semiconductor memory device is a random access memory, the time taken for input / output is constant regardless of the address at which data is written and read.

Typically, each bit in SRAM is stored in two pairs of inverters of four transistors. Two pairs of inverters keep the values of 0 and 1 stable, and two access transistors perform read and write functions. Thus, six transistors are usually required to store one bit.

Fast SRAMs are faster than DRAMs, so they are often used in speed-sensitive parts such as memory inside the CPU (pipeline, processor registers, cache, etc.). It is also used in external caches, DRAM burst mode circuits, and digital signal processing circuits. Low-speed, low-capacity SRAMs are used where low power and low cost are critical, such as battery-backed backup memory. SRAMs are less dense than DRAMs and are therefore not suitable for high-capacity, cheap storage devices such as main memory in personal computers.

The power consumption of SRAM depends a lot on the clock frequency. High-speed semiconductor memory devices consume more power than DRAM and can consume up to several watts, depending on the design. On the other hand, SRAMs, such as CMOS memory on personal computer motherboards, can maintain content with as little as a few microwatts of power without input and output.

SRAM must charge and discharge the bit line periodically every time data is stored and read in the cell. Since the bit line has a large capacitance, a large power is consumed to charge and discharge. In addition, in order to operate stably, the SRAM cell needs to have sufficient read stability and write margin.

An object of the present invention is to provide a semiconductor memory device that can reduce power consumption during a read or write operation.

Another object of the present invention is to provide a semiconductor memory device capable of lowering a supply voltage and a swing voltage during a read or write operation.

In an embodiment, a semiconductor memory device may include a write driver providing a first swing voltage to a data bus line pair, a column selection circuit connecting the data bus line pair to a bit line pair selected according to an input address, and A plurality of subblocks connected to a selected bit line pair, each of the plurality of subblocks being configured to sense and amplify the first swing voltage of the selected bit line pair to generate a second swing voltage; And a plurality of memory cells connected to a sub-bit line pair receiving a second swing voltage and storing data according to the second swing voltage of the sub-bit line pair.

In example embodiments, the first swing voltage may be lower than the second swing voltage.

The read driver of claim 1, wherein the semiconductor memory device comprises: a read driver configured to provide a third swing voltage to the selected bit line pair according to data stored in an activated memory cell among the plurality of memory cells during a read operation; The circuit may further include a read detector connected to the selected bit line pair and the data bus line pair to sense and amplify the third swing voltage of the data bus line pair to generate a fourth swing voltage.

In example embodiments, the third swing voltage may be lower than the fourth swing voltage.

In an embodiment, the pair of bit lines may be implemented as a bit line of a hierarchical structure.

In example embodiments, the plurality of memory cells may be implemented in a latch structure.

Another semiconductor memory device may include a first memory cell connected to a first bit line pair, a second memory cell connected to a second bit line pair adjacent to the first bit line pair, and the first memory cell. A first write driver for providing a write voltage to the bit line pair, and a second write driver for providing a write voltage to the second bit line pair, wherein a charge used in the first write driver during a write operation is Any one of the first bit line pairs will be electrically connected to any one of the second bit line pairs to be recycled in the second write driver.

In an embodiment, a first read driver coupled to the first memory cell and configured to provide a read voltage to the first pair of bit lines according to data stored in the first memory cell, and a second read driver connected to the second memory cell. And a second read driver for providing a read voltage to the second pair of bit lines according to the data stored in the second memory cell, wherein the charge used in the first read driver during the read operation is the second. Any one of the first bitline pairs will be electrically connected to either one of the second bitline pairs for recycling in a read driver.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

In the semiconductor memory device according to the present invention, the level of the supply voltage and the swing voltage may be lowered by controlling the bit line and the data bus line by a charge recycle technique during a read or write operation. As a result, the semiconductor memory device of the present invention will have reduced power consumption compared with that of the conventional one.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention. Referring to FIG. 1, the semiconductor memory device 100 may include a memory cell array 110, a predecoder 120, a word line decoder 130, a column selection circuit 140, a control circuit 150, and an input / output circuit 160. ), And a compensation circuit 170. The semiconductor memory device 100 of the present invention may include a memory cell array 110 and an input / output circuit 160 for charging / discharging a bit line or a data bus line by a charge recycling method during a read / write operation.

The semiconductor memory device 100 shown in FIG. 1 is an SRAM. However, the semiconductor memory device 100 of the present invention is not necessarily limited to the SRAM. The semiconductor memory device 100 of the present invention may be a memory device capable of charging / discharging bit lines or data bus lines using a charge recycling technique.

The memory cell array 110 may include a plurality of memory blocks MB1 to MBR. Each of the memory blocks MB1 to MBR may be controlled by a timing control signal generated from the control circuit 150.

Each of the memory blocks MB1 to NBR may include a plurality of bit line units BU1 to BUN. Each of the bit line units BU1 to BUN may include a plurality of sub blocks SB1 to SBM connected to each of the bit line pairs (BL1, / BL1) to (BLN, / BLN).

Hereinafter, for convenience of description, one subblock SB1 will be described. The sub block SB1 may include a write detector 111, a read driver 112, and a plurality of memory cells. Here, the plurality of memory cells will be implemented in a latch structure.

The write detector 111 may be connected between the bit line BL1 and the complementary bit line / BL1. The write detector 111 detects a swing voltage between the bit line BL1 and the complementary bit line / BL1 during a write operation on data in a word unit, and amplifies the detected swing voltage to subsubline SBL1. And to the complementary subbit line / SBL1. That is, even if the write detector 111 swings to the bit lines BL1 and / BL1 at a low voltage during a write operation, the data may be stably stored in the memory cell.

The read driver 112 may be connected between the bit line BL1 and the complementary bit line / BL1. The read driver 112 of the present invention will be electrically connected to the read driver of the adjacent bit line unit BU2. As a result, the read drivers of the bit line units BU1 to BUN will be able to charge-charge each other. Detailed description will be made with reference to FIG. 5.

The predecoder 120 receives an address ADDR of K bits (where K is an integer) from the outside and performs block decoding to generate a block address. That is, the predecoder 120 receives an address ADDR to determine a memory block to be activated.

The word line decoder 130 receives a block address generated from the predecoder 120 and a control signal of the control circuit 150 to select one word line among the plurality of blocks BLK1 to BLKR.

The column select circuit 140 may include the bit lines (BL1, / BL1) to (BLN, / BLN) and the data bus lines (DB1 to / DB1) to the selected block under the control of the control circuit 150. (DBN, / DBN)).

The control circuit 150 may control the overall operation of the semiconductor memory device 100.

The input / output circuit 160 may temporarily store data to be written or data to be read. The input / output circuit 160 may include a plurality of write drivers and a plurality of read detectors.

Hereinafter, one read detector 161 and a write driver 162 will be described for convenience of description.

The read detector 161 will be connected between the data busline DB1 and the complementary data busline / DB1. The read detector 161 detects and amplifies a voltage between the data bus line DB1 and the complementary data bus line / DB1 during a read operation. In this case, each of the data bus lines DB1 and / DB1 may be connected to bit lines selected by the column select circuit 140. As a result, the read detector 161 will sense amplify the voltage swinging on the selected bit lines.

The write driver 161 may be connected between the data bus line DB1 and the complementary data bus line / DB1. The write driver 162 will swing the data bus lines DB1 and / DB1 to a low voltage according to the input data pattern. In addition, the write driver 162 may be connected with an adjacent write driver for charge recycling operation to thereby recycle charge. Detailed description will be made with reference to FIG. 3.

The compensation circuit 170 generates reference voltages for the charge recycling operation and keeps them constant.

In the semiconductor memory device 100 of the present invention, the bit lines are implemented in a hierarchical architecture to reduce the capacitance of the bit lines. By using this hierarchy, the bit line capacitance will be reduced. The bit line capacitance of a conventional semiconductor memory device is the sum of the bit line capacitance made of metal and the drain capacitance of a transistor connected to the bit line. However, if the bit line of the present hierarchical structure is used, the capacitance of the bit line will consist only of metal capacitance. This will reduce the overall bit line capacitance.

Further, in the semiconductor memory device 100 of the present invention, the operation will be performed at a low swing voltage on the bit line having a large capacitance and at a high swing voltage on a sub bit line having a low capacitance. As a result, the semiconductor memory device 100 of the present invention will reduce power consumption.

In order to use the charge recycling technique, the present invention requires reference voltages to be the reference of the respective voltages. Simulations show low power consumption and eight charge recycling times for accurate and fast operation. Hereinafter, for convenience of description, the charge recycling recovery N will be described with reference to a semiconductor memory device using a charge recycling technique using eight reference voltages. In other words, in the semiconductor memory device of the present invention, eight charge recycling operations are performed, and power consumption will be reduced by 1/8 ² = 1/64. There is power consumption of the added driver (read driver, write driver), but it is not large.

The semiconductor memory device 100 according to the present invention may include a read driver and a write driver to enable charge recycling during a write / read operation. This will lower the voltage level provided to the bit lines and data bus lines. As a result, the semiconductor memory device 100 of the present invention will reduce power consumption.

2 is an embodiment of a compensation circuit for generating reference voltages of the present invention. Referring to FIG. 2, the compensation circuit 170 may allow the reference voltages to be generated constantly. For example, whenever the reference voltage is shaken, the NMOS transistor NM and the PMOS transistor PM included in each of the reference generators 171 to 17N may operate to maintain a constant voltage.

The reference voltage must be kept constant for charge recycling operation. When the reference voltage is shaken, the NMOS transistor NM and the PMOS transistor PM operate to maintain the voltage. For example, when the voltage is increased, the voltage will be lowered by turning on the PMOS transistor PM, and when the voltage is lowered, the voltage will be increased by turning on the NMOS transistor NM.

In the write operation, 8 bits of data (1 or 0) will be input to the write driver 162 through the output circuit. Each data is combined with the write change reproduction activation signal WCRE according to the pattern of the data, thereby determining whether one of '1' and '0' data is to be transmitted to the bit line. The reference voltages VCR <N> to VCR <N> are used as supply voltages of the data bus lines. When the power supply voltage VDD is used, the K-th reference voltage VCR <K> is {1- (K-0.5) / N}> VDD. When the power supply voltage VDD is 1.8V and N is 8, the difference between adjacent reference voltages is approximately 200mV, and the swing voltages of the bit lines and data bus lines by charge recycling will be 200mV. Eight reference voltages were created for eight charge recycling cycles, and each reference voltage would be used as the reference voltage for charge recycling.

If the data is '1', the bit line is connected to a high reference voltage to have data of '1'. If the data is '0', the bit line is connected to a low reference voltage to have data of '0'. Will be.

The used charge will have to move to the next stage in order to be recycled. To this end, the reference voltage is shared with the next cell block so that charge can be recycled in the next step.

3 is a diagram illustrating a write driver according to an exemplary embodiment of the present invention. Referring to FIG. 3, the write driver 162 will operate as follows.

When the write charge recycle enable signal WCRE is activated, the transistors M1 to M4 are turned on according to the value of the input data DIN. If the input data DIN is '1', the first and fourth transistors M1 and M4 will be turned on. Accordingly, the data bus line DB1 may be connected to the reference voltage VCR <1>, and the complementary data bus line / DB1 may be connected to the reference voltage VCR <2>. As a result, data busline DB1 and data busline / DB1 will swing to the low voltage levels of VCR <1> and VCR <2>.

If the input data DIN is '0', the second and third transistors M2 and M3 will be turned on. Accordingly, the data bus line DB1 may be connected to the reference voltage VCR <2>, and the complementary data bus line / DB1 may be connected to the reference voltage VCR <1>. As a result, data busline DB1 and data busline / DB1 will swing to the low voltage levels of VCR <2> and VCR <1>.

According to the write driver of the present invention, either a data bus line or a complementary data line may be connected to either the data bus line or the complementary data bus line of an adjacent write driver according to input data during a write operation. Thus, the charge used in the write driver will be implemented to be used in the adjacent write driver.

4 is a diagram illustrating a write detector according to an exemplary embodiment of the present invention. Referring to FIG. 4, the write detector 161 will operate as follows.

The write detector 161 may amplify and transmit the voltage swinging on the bit lines BL1 and / BL1 to the sub bit lines SBL1 and / SBL1. In this way, the amplified data will be stably stored in the cell.

For convenience of explanation, the following description will be limited to the write operation on the memory cell belonging to the first bit line unit BU1.

Depending on the input data, the bitline will swing to a low swing voltage. In this case, the write detector 111 senses and amplifies a voltage swinging on the bit lines BL and / BL1 and transmits the amplified voltage to the sub bit lines SBL1 and / SBL1. As a result, the sub bit lines SBL1 and / SBL1 will swing a high swing voltage. In this case, the word line WL may be activated by the word line decoder 130. In the memory cell selected by the activated word line, data according to a high swing voltage swinging on the sub bit lines SBL1 and / SBL1 may be stored. In this way, the data will be stored more stably.

5 is a diagram illustrating a read driver according to an exemplary embodiment of the present invention. Referring to FIG. 5, the read driver 112 may be implemented similarly to the write driver shown in FIG. 3.

When the read charge recycle enable signal RCRE is activated, the transistors M1 to M4 are turned on according to the values of the sub bit lines SBL1 and / SBL1. If the data sensed from the sub-bit lines SBL1 and / SBL1 is '1', the first and fourth transistors M1 and M4 may be turned on. The bit line BL1 is connected to the reference voltage VCR <1>, and the complementary bit line / BL1 is connected to the reference voltage VCR <2>. As a result, the bit lines BL1 and / BL1 will swing to the low voltage levels of VCR <1> and VCR <2>.

If the data sensed from the sub bit lines SBL1 and / SBL1 is '0', the second and third transistors M2 and M3 may be turned on. The bit line BL1 is connected to the reference voltage VCR <2>, and the complementary bit line / BL1 is connected to the reference voltage VCR <1>. As a result, the bit lines BL1 and / BL1 will swing to the low voltage levels of VCR <2> and VCR <1>.

If the data sensed from the sub bit lines SBL1 and / SBL1 is '0', the voltage difference between the bit line BL1 and the complementary bit line / BL1 will be 0V.

According to the read driver of the present invention, either one of a bit line or a complementary bit line may be connected to one of a bit line or a complementary bit line of an adjacent read driver according to data during a read operation. Thus, the charge used in the read driver will be implemented to be used in the adjacent read driver.

6 is a diagram illustrating a read detector according to an exemplary embodiment of the present invention. Referring to FIG. 6, the read detector 161 will be implemented similarly to the write detector shown in FIG. 4.

Hereinafter, for convenience of description, the description will be limited to a read operation on the memory cell of the first bit line unit BU1. The read detector 161 senses and amplifies the data lines DB1 and / DB1 in response to the read activation signal RSAE and outputs the read data DOUT.

In the semiconductor memory device 100 of the present invention, 12-bit addresses are simultaneously input to the row decoder and the column decoder, and the row addresses of the memory cells to be used are determined by combining them. The eight row decoder input data will determine one of a total of 256 word lines. The four column decoder input data will determine any of the sixteen block columns.

In the read operation, when the word line is activated, the data stored in the cell will be transmitted to the sub-bit lines SBL1 and SBL1 with a high swing voltage. The charge recycling read driver 112 may operate to operate the bit lines BL1 and / BL1 at low swing voltages according to the data patterns of the sub bit lines SBL1 and / SBL1. Like the charge recycling write driver 162, the charges used in the bit lines BL1 and / BL1 may be connected to be recycled in an adjacent block.

When data is transferred to the bit lines BL1 and / BL1 (a swing voltage is applied) and the column select circuit 140 operates, the bit lines BL1 and / BL1 and the data bus lines DB1 and / DB1 are applied. ) Will be connected to each other. In this case, the data bus lines DB1 and / DB1 are connected to the read detector 161 so that data is amplified and output by a high swing voltage.

As described above, the read / write operation according to the present invention will be implemented such that the bit lines or data bus lines swing to a low voltage.

7 is a view showing an embodiment of an operation waveform diagram of a control signal during a write operation of the present invention. 1 to 7, the write operation of the semiconductor memory device 100 will proceed as follows.

After the data DIN is input in the write operation, the write charge recycling activation signal WCRE will be activated. The bit lines (BL1, / BL1) ... (BLN, / BLN) will swing to a low voltage. After the data to be written to the bit lines (BL1, / BL1) ... (BLN, / BLN) is completely loaded, the write sense amplification enable signal (WSAE) will be activated. Accordingly, the sub bit lines SBL <1: N> and / SBL <1: N> will swing to high voltages. In this case, the data DIN stored in the cell where the word line is activated will be stored.

8 is a diagram illustrating an embodiment of an operation waveform diagram of a control signal during a read operation of the present invention. 1 to 6 and 8, the read operation of the semiconductor memory device 100 will proceed as follows.

The bit lines (((BL1, / BL1) ... (BLN, / BLN)) and the subbit lines SBL <1: N>, / SBL <1: N> will be controlled by control signals. In operation, the data A and B stored in the cell will be loaded into a pre-charged sub bit line when the word line WL is activated, which will swing to a high voltage.

When the data is fully loaded, the read charge recycling activation signal RCRE will be activated. As a result, the bit line will swing to a low voltage.

After the data is completely loaded into the bitline, the read sense amplification enable signal (RCSA) will be activated. Accordingly, the data DOUT read by the read detector 161 will be output.

The semiconductor memory device 100 needs to charge / discharge the bit line and the data bus line having a large capacitance periodically in every operation. Because of this, the power consumption in the bit line and data bus line is very large.

The semiconductor memory device 100 of the present invention may reduce power consumption by using charge recycling techniques in bit lines and data bus lines during a write operation or a read operation. In the conventional semiconductor memory device, the charge is used only once and then discarded. However, the charge recycling technique of the present invention may be used again to operate another cell. This will greatly reduce power consumption between the bitline and the data busline.

In addition, the semiconductor memory device 100 of the present invention may stably store data by using a high swing voltage only in a portion necessary for a write operation. This would be an advantage of reducing power consumption while maintaining performance.

The charge recycling technique according to the present invention will not be limited to semiconductor memory devices. The charge recycling technique of the present invention may be applied to circuit designs that operate at low power in various digital integrated circuits.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an embodiment of the compensation circuit shown in FIG. 1.

3 is a diagram illustrating a write driver according to an exemplary embodiment of the present invention.

4 is a diagram illustrating a write detector according to an exemplary embodiment of the present invention.

5 is a diagram illustrating a read driver according to an exemplary embodiment of the present invention.

6 is a diagram illustrating a read detector according to an exemplary embodiment of the present invention.

7 is a waveform diagram illustrating a writing method according to an exemplary embodiment of the present invention.

8 is a waveform diagram illustrating a reading method according to an exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100: semiconductor memory device 110: memory cell array

120: predecoder 130: word line decoder

140: column selection circuit 150: control circuit

160: input and output buffer 170: compensation circuit

111: write detector 112: read driver

161: read detector 162: write driver

Claims (8)

A write driver providing a first swing voltage to a pair of data bus lines; A column selection circuit connecting the data bus line pair to a bit line pair selected according to an input address; And A plurality of subblocks connected to the selected bit line pair; Each of the plurality of subblocks, A write detector for sensing and amplifying the first swing voltage of the selected bit line pair to generate a second swing voltage; And And a plurality of memory cells connected to the sub-bit line pair receiving the second swing voltage and storing data according to the second swing voltage of the sub-bit line pair. The method of claim 1, And the first swing voltage is lower than the second swing voltage. The method of claim 1, The semiconductor memory device, A read driver configured to provide a third swing voltage to the selected bit line pair according to data stored in an activated memory cell among the plurality of memory cells during a read operation; And And a read detector coupled to the selected bit line pair and the data bus line pair by the column select circuit, and configured to sense and amplify the third swing voltage of the data bus line pair to generate a fourth swing voltage. Device. The method of claim 3, wherein And the third swing voltage is lower than the fourth swing voltage. The method of claim 1, The bit line pair is a semiconductor memory device implemented as a bit line of a hierarchical structure. The method of claim 1, And the plurality of memory cells have a latch structure. A first memory cell coupled to the first bit line pair; A second memory cell connected to the second bit line pair adjacent to the first bit line pair; A first write driver for providing a write voltage to the first pair of bit lines; And A second write driver for providing a write voltage to the second bit line pair; And any one of the first pair of bit lines is electrically connected to one of the pair of second bit lines so that the charge used in the first write driver is recycled in the second write driver during a write operation. The method of claim 7, wherein A first read driver coupled to the first memory cell and configured to provide a read voltage to the first pair of bit lines according to data stored in the first memory cell; And A second read driver connected to the second memory cell and configured to provide a read voltage to the second bit line pair according to data stored in the second memory cell, And one of the first pair of bit lines is electrically connected to one of the pair of second bit lines so that the charge used in the first read driver is recycled in the second read driver during a read operation.

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