KR101158194B1 - Method for modeling multi layer ceramic capacitor - Google Patents

Abstract

A method of modeling a multilayer ceramic capacitor is disclosed. The method of modeling the multilayer ceramic capacitor may include configuring an equivalent circuit corresponding to a unit layer having a predetermined length in a layer region, calculating a propagation constant and characteristic impedance of the equivalent circuit corresponding to the unit layer, and calculating the propagation constant and Generating an equivalent circuit corresponding to the multilayer ceramic capacitor using the characteristic impedance, and calculating each parameter of the equivalent circuit corresponding to the multilayer ceramic capacitor using frequency characteristics of the multilayer ceramic capacitor. .

Description

Modeling method for multilayer ceramic capacitors

The present invention relates to a technique for modeling an equivalent circuit having a frequency response characteristic most similar to that of a multilayer ceramic capacitor.

Today, multi-layer ceramic capacitors (MLCCs) are widely used throughout the electronics industry because of their small size and small equivalent series resistance (ESR). In particular, high-capacity MLCCs are important because they provide low impedance in the power distribution network (PDN) to provide sufficient current to the MPU or ASIC.

As such, high-capacity MLCCs are widely used in the electronics industry, and require a reliable and accurate equivalent circuit model. When the equivalent circuit model of MLCC is applied to the simulation of the time domain and the frequency domain, there is an advantage that the entire system can be easily analyzed and designed through the response of the equivalent circuit.

In particular, high-capacity MLCCs exhibit resonance characteristics at the first self-resonance frequency (SRF). Secondary resonances appear as the frequency increases, so a modeling circuit capable of accurately representing the frequency response characteristics is required.

For equivalent circuit modeling of MLCCs, a series RLC model, which is generally the simplest form, can be used. This model is a series of resistors, inductors, and capacitors in series, and it is easy to extract each parameter and satisfies the MLCC's frequency response characteristics up to the first resonant frequency. However, since each of the RLC parameters is frequency independent, the impedance is similar to the actual measurement, but there is a problem that the phase or ESR value does not match the actual measurement.

Other methods of modeling MLCCs include distributed models or models using transmission lines. The variance model may represent frequency-dependent inductance, resistance, and capacitance through a ladder-structured RLC model. However, because the number of devices in a distributed model is determined by the number of layers in the MLCC, model complexity becomes very high when modeling a high-capacity MLCC with hundreds of layers. On the other hand, the MLCC model using transmission line theory assumes two inner plates as lossy transmission lines, defines impedances for two substrates using wave equation, and satisfies the first resonant frequency. Extract the model. However, such a transmission line model has a limitation in displaying the characteristics of a high capacity MLCC composed of hundreds of layers because it is assumed that the potential of the external terminal of the MLCC is the same.

The present invention is to provide an accurate modeling circuit exhibiting a frequency response characteristic similar to an actual multilayer ceramic capacitor by modeling a multilayer ceramic capacitor using a transmission line concept.

Modeling method of a multilayer ceramic capacitor according to an embodiment of the present invention for solving the above problems, a modeling method of a multilayer ceramic capacitor comprising a layer region formed by stacking a plurality of substrates and an end region formed at the bottom of the layer region Comprising: forming an equivalent circuit corresponding to a unit layer of a predetermined length in the layer region, and calculating the propagation constant and characteristic impedance of the equivalent circuit corresponding to the unit layer; Generating an equivalent circuit corresponding to the multilayer ceramic capacitor using the calculated propagation constant and the characteristic impedance; And calculating each parameter of an equivalent circuit corresponding to the multilayer ceramic capacitor using the frequency characteristic of the multilayer ceramic capacitor.

At this time, the equivalent circuit corresponding to the unit layer. A first resistor and a first inductor connected in series between one end and the other end of the unit layer; A second resistor connected in parallel between one end and the other end of the unit layer; A second inductor connected in series with the second resistor; A first capacitor connected in series with the second inductor; And a third resistor connected in parallel with the first capacitor.

Values of the first resistor and the first inductor are equivalent resistances and equivalent inductances of the external electrodes connected to the unit layers of the multilayer ceramic capacitor, and values of the second resistor and the second inductor are inside the multilayer ceramic capacitor. Equivalent resistance and equivalent inductance of the included substrate, the value of the first capacitor is the equivalent capacitance between each substrate in the multilayer ceramic capacitor, the value of the third resistance is the dielectric loss (Dielectric loss) of the multilayer ceramic capacitor It is preferable.

In addition, the propagation constant is

The characteristic impedance may be determined as follows.

It can be determined as follows.

Meanwhile, the step of generating an equivalent circuit corresponding to the multilayer ceramic capacitor may include calculating an equivalent impedance of the multilayer ceramic capacitor by assuming that the layer area is a transmission line to which an infinite load is connected; Calculating second and fourth order approximations of the calculated hyperbolic tangent values of the equivalent impedance using continuous partial approximation; And applying the second approximation value and the fourth approximation value to the calculated equivalent impedance of the multilayer ceramic capacitor, respectively, to generate a secondary approximation furnace and a fourth approximation furnace furnace of the multilayer ceramic capacitor.

At this time, the equivalent impedance of the secondary equivalent circuit is the following equation

는 상기 단위 레이어에 대응되는 등가회로의 전파상수, l은 상기 레이어 영역의 길이, R_p는 상기 기판의 레지스턴스, L_p는 상기 기판의 인덕턴스, R_T는 상기 말단 영역의 레지스턴스, L_T는 상기 말단 영역의 인덕턴스, R_s는 상기 레이어 영역과 접속된 외부 전극의 레지스턴스, L_s는 상기 레이어 영역과 접속된 외부 전극의 인덕턴스, C는 상기 적층형 세라믹 캐패시터 내부의 각 기판 간의 캐패시턴스, R_d는 유전손실)(Wherein, Z _{2nd -} 2 _model is equivalent to the impedance of the equivalent circuit of the car, Z ₀ is the characteristic of the equivalent circuit corresponding to the impedance of the layer unit,

Is a propagation constant of an equivalent circuit corresponding to the unit layer, l is the length of the layer region, R _p is the resistance of the substrate, L _p is the inductance of the substrate, R _T is the resistance of the terminal region, and L _T is the Inductance of the terminal region, R _s is the resistance of the external electrode connected to the layer region, L _s is the inductance of the external electrode connected to the layer region, C is the capacitance between each substrate in the multilayer ceramic capacitor, R _d is the dielectric Loss)

The equivalent impedance of the fourth equivalent circuit may be determined as follows.

는 상기 단위 레이어에 대응되는 등가회로의 전파상수, l은 상기 레이어 영역의 길이, R_p는 상기 기판의 레지스턴스, L_p는 상기 기판의 인덕턴스, R_T는 상기 말단 영역의 레지스턴스, L_T는 상기 말단 영역의 인덕턴스, R_s는 상기 레이어 영역과 접속된 외부 전극의 레지스턴스, L_s는 상기 레이어 영역과 접속된 외부 전극의 인덕턴스, C는 상기 적층형 세라믹 캐패시터 내부의 각 기판 간의 캐패시턴스, R_d는 유전손실)(Wherein, Z _{4th - model} 2 is an equivalent impedance of the secondary equivalent circuit, Z ₀ is the characteristic of the equivalent circuit corresponding to the impedance of the layer unit,

Is a propagation constant of an equivalent circuit corresponding to the unit layer, l is the length of the layer region, R _p is the resistance of the substrate, L _p is the inductance of the substrate, R _T is the resistance of the terminal region, and L _T is the Inductance of the terminal region, R _s is the resistance of the external electrode connected to the layer region, L _s is the inductance of the external electrode connected to the layer region, C is the capacitance between each substrate in the multilayer ceramic capacitor, R _d is the dielectric Loss)

It can be determined as follows.

Meanwhile, calculating each parameter of an equivalent circuit corresponding to the multilayer ceramic capacitor may include calculating a parameter from the impedance measurement at the first resonance frequency of the multilayer ceramic capacitor to the secondary near-field; And calculating a parameter to the fourth near field from the calculated parameter to the secondary near field and the impedance measurement value at the secondary resonance frequency of the multilayer ceramic capacitor.

The present invention has the effect of providing an accurate modeling circuit that exhibits the frequency response characteristic of a high-capacity multilayer ceramic capacitor by modeling a multilayer ceramic capacitor using a transmission line concept.

In addition, the parameter of the modeling circuit extracted according to the present invention includes a unit length parameter including internal structure information of the actual multilayer ceramic capacitor, and when used, the parameter may be used to manufacture and change characteristics of the actual high capacity multilayer ceramic capacitor. .

1 is a cross-sectional view of a multilayer ceramic capacitor (MLCC) according to an embodiment of the present invention.
FIG. 2 is an equivalent block diagram of the impedance of the multilayer ceramic capacitor disclosed in FIG. 1.
3 is a flowchart illustrating a modeling method 300 of a multilayer ceramic capacitor according to an embodiment of the present invention.
4 is an exemplary view for explaining that a current flowing through each layer of the multilayer ceramic capacitor forms a loop according to an embodiment of the present invention.
5 is an equivalent circuit diagram illustrating a multilayer ceramic capacitor using capacitors and inductors according to an embodiment of the present invention.
FIG. 6A is a diagram for describing a model of a lossless transmission line theory, and FIG. 6B is a diagram illustrating a dispersion model in which the transmission line theory model is applied to the multilayer ceramic capacitor 100.
FIG. 7 is a diagram illustrating an equivalent circuit corresponding to a unit layer having a minimum length Δz of a layer region of the multilayer ceramic capacitor 100 based on the transmission line theory from the dispersion model illustrated in FIG. 6B. .
FIG. 8 illustrates a state in which the layer region of the multilayer ceramic capacitor 100 is assumed to be a transmission line having a length _L with a load Z _L.
FIG. 9 is a circuit diagram illustrating a secondary model in which Equation 12 is represented using a lumped element.
FIG. 10 is a circuit diagram showing a fourth-order model in which Equation 13 is represented using a lumped element.
11 and 12 show the equivalent impedance of the multilayer ceramic capacitor 100 obtained by substituting the approximation of the hyperbolic tangent of Equation 10 according to each order into Equation 11 and the actual impedance of the multilayer ceramic capacitor 100. It is a graph showing impedance and phase.
FIG. 13 is a diagram illustrating a secondary model of the multilayer ceramic capacitor 100.
FIG. 14 is a table illustrating parameter values of a secondary model extracted for three models of a high capacity multilayer ceramic capacitor having a size of 2012 according to an embodiment of the present invention.
FIG. 15 is a view illustrating a fourth order model of a high capacity multilayer ceramic capacitor.
16 is a graph of measuring and recording impedance real values of high capacity multilayer ceramic capacitors.
FIG. 17 illustrates a length ratio of Z _layer and Z _T in the multilayer ceramic capacitor 100.
18 is an internal cross-sectional view of a 10 μF multilayer ceramic capacitor of 2012 size.
FIG. 19 is a table showing parameters of unit lengths extracted for three models of a high capacity multilayer ceramic capacitor having a size of 2012.
FIG. 20 is a table showing parameters of a fourth-order equivalent model extracted by substituting the parameter of the unit length described in FIG. 20 into Equation 20. FIG.

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. However, this is only an exemplary embodiment and the present invention is not limited thereto.

In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intention or custom of the user, the operator, and the like. Therefore, the definition should be based on the contents throughout this specification.

As a result, the technical spirit of the present invention is determined by the claims, and the following examples are one means for efficiently explaining the technical spirit of the present invention to those skilled in the art to which the present invention pertains. It is only.

1 is a cross-sectional view of a multilayer ceramic capacitor (MLCC) according to an embodiment of the present invention.

As shown, the multilayer ceramic capacitor 100 according to an embodiment of the present invention includes a substrate 102 stacked in parallel with each other, a dielectric 104 and an external electrode provided between the substrates 102. (106, termination). At this time, as shown, the substrate 102 of each layer is alternately connected to the external electrode 106 and the adjacent substrate is connected through the dielectric 104. The impedance of the multilayer ceramic capacitor 100 is the impedance Z _layer of the portion where the substrate 102 and the external electrode 106 are bonded (hereinafter referred to as a "layer area"), the dielectric 104 and the external electrode ( It can be configured with the impedance Z _T of the portion (hereinafter referred to as the 'end region') that exists 106, as shown in Figure 2 equivalent block diagram.

The impedance Zcap of the multilayer ceramic capacitor 100 is shown from the equivalent block diagram of FIG. 2 as follows.

In Equation 1, since Z _T represents the impedance of the external electrode 106, Equation 1 may be expressed as Equation 2 below.

In the above equation, R _T represents the loss of the external electrode 106 and L _T represents the inductance of the external electrode 106.

3 is a flowchart illustrating a modeling method 300 of a multilayer ceramic capacitor according to an embodiment of the present invention.

As illustrated, the modeling method 300 of the multilayer ceramic capacitor according to the exemplary embodiment of the present invention constitutes an equivalent circuit corresponding to a unit layer of a predetermined length in a layer area of the multilayer ceramic capacitor 100, and the unit Calculating a propagation constant and characteristic impedance of the equivalent circuit corresponding to the layer (302), generating an equivalent circuit corresponding to the multilayer ceramic capacitor using the calculated propagation constant and the characteristic impedance (304), and Calculating each parameter of an equivalent circuit corresponding to the multilayer ceramic capacitor using the frequency characteristic of the multilayer ceramic capacitor.

Hereinafter, each step of the modeling method 300 of the multilayer ceramic capacitor as described above will be described in detail.

Stacked  ceramic Capacitor  unit Layer modelling (302)

First, a process for extracting the impedance of the layer region where the substrate 102 and the external electrode 106 are bonded is as follows.

Inductance can generally be defined when constructing a closed loop. Therefore, in consideration of the impedance of the closed circuit including the multilayer ceramic capacitor 100, as shown in FIG. 4, a current flow is formed in each layer. As can be seen in FIG. 4, the current flowing through the top layer of the multilayer ceramic capacitor 100 has a high inductance and the current flowing through the bottom layer has a low inductance.

Referring to FIG. 4, a model of the multilayer ceramic capacitor 100 using a capacitor and an inductor element, ignoring the loss of the substrate 102 and the external electrode 106, may be represented as a structure of FIG. 5A. have. If this is unfolded again, the structure is the same as the model of FIG. Finally, this may be expressed as a Lumped model as shown in FIG.

In the case of high-capacity multilayer ceramic capacitors, hundreds of substrates are stacked in the layer region, and if each layer is modeled separately, the model complexity becomes very high. However, since the equivalent circuit model shown in (c) of FIG. 5 is shaped like a lumped model of a lossless transmission line, the impedance for hundreds of layers is simplified by using continuous approximation such as the transmission line theory. It is possible to express.

FIG. 6A is a diagram illustrating a model of a lossless transmission line theory, and FIG. 6B is a diagram illustrating a dispersion model in which the transmission line theory model is applied to the multilayer ceramic capacitor 100. Where R _S is the resistance of the external electrode 106, L _S is the inductance of the external electrode 106, R _P is the resistance of the substrate 102, L _P is the inductance of the substrate 102, and R _d is the dielectric loss. (Dielectric loss), and C is the capacitance between the substrates.

FIG. 7 is a diagram illustrating an equivalent circuit corresponding to a unit layer having a minimum length Δz of a layer region of the multilayer ceramic capacitor 100 based on the transmission line theory from the dispersion model illustrated in FIG. 6B. .

Applying Kirchhoff's voltage law and current law to the circuit shown in FIG.

Each can be obtained. Dividing Equation 3 by Δz and making a condition by Δz → 0 can be represented by the following differential equation.

Two equations of Equation 4 are combined and solved as equations for V (z) and I (z) as follows.

를 구하면 Propagation Constant in Equation 5

If you find

And a characteristic impedance is derived from Equation 5 below.

Stacked  ceramic On the capacitor  Corresponding Equivalent circuit  Create (304)

FIG. 8 illustrates a state in which the layer region of the multilayer ceramic capacitor 100 is assumed to be a transmission line having a length _L with a load Z _L. When the current at Z = -l is I _in and the voltage is V _in , the input impedance Z _in facing the load at a distance l away from the load can be expressed as follows from the equation for the input impedance of the transmission line: have.

In Equation 8, since Z _L has a very small capacitance value compared to the capacitance between substrates, Z _L Assuming that = ∞, Equation 8 can be expressed as follows.

은 연속부분근사(continued fraction approximation)을 이용하면 다음과 같이 근사화할 수 있다.
In Equation 9,

Using continuous fraction approximation can be approximated as

From the above Equations 1 and 10, the impedance Z _cap of the multilayer ceramic capacitor 100 is

The following equation (12) can be obtained by approximating the above equation (11) using up to the second term of equation (10). This is defined as the quadratic approximation or the impedance of the quadratic model (Z _{2nd - model} ).

In the same way, by approximating Equation 11 using up to the fourth order term of Equation 10 (fourth order approximation), Equation 13 can be obtained as follows. _{4th - model} ).

In this case, l represents the length of the layer region.

Equation 12 and equation 13 are shown using a lumped element to obtain an equivalent circuit model as shown in FIGS. 9 and 10. The model shown in FIG. 9 will be defined as a quadratic approximation or a quadratic model, and the model shown in FIG. 10 will be defined as a quadratic approximation or a fourth order model. The fourth-order model shown in FIG. 10 is a final equivalent model of the multilayer ceramic capacitor 100 according to the present invention, and the second-order model is a model used to obtain parameters of the fourth-order model.

을 각 차수에 따라 근사화한 값을 수학식 11에 대입하여 얻은 적층형 세라믹 캐패시터(100)의 등가 임피던스와 실제 적층형 세라믹 캐패시터(100)에서 측정한 임피던스, 페이즈를 나타낸 그래프이다. 도시된 바와 같이, 2차 이상의 모델은 1차 공진주파수의 특성을 만족시키고 4차 이상의 모델은 1차 공진주파수와 2차 공진주파수 모두에서의 임피던스와 페이즈 특성을 만족시키는 것을 알 수 있다.
11 and 12 illustrate equation 10.

Is a graph showing the equivalent impedance of the multilayer ceramic capacitor 100 obtained by substituting the value approximated according to each order into Equation 11 and the impedance and phase measured by the actual multilayer ceramic capacitor 100. As shown, it can be seen that the second-order or higher model satisfies the characteristics of the primary resonant frequency and the fourth-order or higher model satisfies the impedance and phase characteristics at both the first and second resonant frequencies.

Stacked  ceramic On the capacitor  Corresponding Equivalent circuit  Parameter calculation (306)

Hereinafter, a process of calculating each parameter of the equivalent circuit derived by the above-described method will be described.

In the model parameter extraction process, parameters of the secondary model are extracted from the primary resonant frequency using the characteristics shown in FIGS. The unit length parameter is extracted using a part of, and finally, all parameters of the 4th model are extracted.

FIG. 13 is a diagram illustrating a secondary model of the multilayer ceramic capacitor 100 described above. In FIG. 13, each parameter R2nd, L2nd, G2nd, and C2nd can be expressed as follows from Equation 12.

A method for extracting parameter values of the secondary model described in Equation 14 is as follows. First, the impedance Z _{2nd - model} (ω) of the secondary model from the secondary equivalent model circuit of FIG. 13 is represented by real and imaginary numbers as follows.

In Equation 15, the capacitor value C _2nd is applied by giving an error of ± 20% to the actual capacitance value of the multilayer ceramic capacitor 100 indicated by the manufacturer as shown in Equation 16 below.

G _2nd is a value representing dielectric loss. In general, G _2nd can be expressed as follows using loss tangent and capacitance values.

In addition, using the characteristic that the imaginary component of impedance Z _{2nd - model} (ω) of the secondary model becomes 0 at the first resonant frequency, L _2nd can be extracted as follows.

In Equation 18, ω _SRF represents a first resonant frequency. Similarly, in the case of R _2nd , the imaginary component of impedance Z _{2nd - model} (ω) is removed at the first resonant frequency (ω _SRF ) and (ωC _2nd ) ² >> G _2nd ^{- 1} from the real component. .

The parameter values of the secondary model extracted for the three models of the 2012 high-capacity multilayer ceramic capacitor through the above process are shown in FIG. 14.

FIG. 15 is a view illustrating a fourth equivalent model which is a final equivalent model of a high capacity multilayer ceramic capacitor. Each of the parameters C _circuit1 , G _circuit1 , L _circuit1 , R _circuit1 , C _circuit2 , G _circuit2 , L _circuit2 , R _circuit2 , L _circuit3 , and R _circuit3 in the _drawings may be defined as follows from Equation 13 described above.

In Equation 19, C _circuit1 , G _circuit1 , C _circuit2 , and G _circuit2 may be extracted using Equation 16 and Equation 17 described above.

In the fourth equivalent model shown in FIG. 15, circuit 2 causes series resonance and circuit 2 and circuit 3 cause parallel resonance. The parameter extraction from the parallel resonance is complicated by the formula induction process because the resistor parameter and the inductor parameter are together. Therefore, in the present invention, the parameter is extracted from the frequency when the series resonance of circuit2 occurs. The frequency at which the series resonance occurs is defined as a secondary resonance frequency (ω _{2 nd} ), and the unit length parameter (L _P / l) is derived from the parameters extracted from the secondary resonance frequency and the parameters of the secondary model. , L _S l, R _P / l, R _S l) can be extracted.

First, a process of extracting the inductance parameters L _P / l, L _S l and L _{T from the} parameters will be described first.

16 is a graph measuring and recording an impedance real value of a high capacity multilayer ceramic capacitor. As can be seen from the figure, the impedance of the high capacity multilayer ceramic capacitor model has a maximum value when circuit2 and circuit3 of FIG. 15 cause parallel resonance and a minimum value when circuit2 causes series resonance. However, it is difficult to distinguish between the maxima and minima in the impedance or phase information of the measured data. Therefore, the second resonance frequency is extracted from the measured impedance real value of the high capacity multilayer ceramic capacitor at the point where the impedance real value becomes the minimum after the parallel resonance of circuit2 and circuit3.

Using the characteristic that the impedance imaginary value of circuit2 becomes zero at the second resonant frequency, L _circuit2 becomes

It is determined as

Can be obtained. Here, L _s / l and L _T denote the inductance of the external electrode 106, so that the ratio of the values is expressed using the length ratio k between Z _layer and Z _T shown in FIG.

Can be defined as Here, L _s represents the inductance for the 2Z _layer , so the ratio of 2L _T and Ls / l is determined by k as shown in Equation 23.

When the equations 21 and 22 are combined and solved, the values of Lp / l and Ls / l can be expressed using the parameters of the secondary model as follows.

The inductance parameters L _circuit1 , L _circuit2 , and L _circuit3 of the fourth-order model may be represented by substituting Equation 24 into Equation 20 and may be defined as follows.

Hereinafter, the extraction process of the register parameters (R _p / l, R _s 1, R _T ) of the 4th model will be described.

As the frequency increases, the resistance of the conductor increases according to the surface depth when the skin depth becomes thinner than the thickness of the conductor due to the skin effect that the current flows concentrated on the surface rather than inside the metal. As a result, in the case of R _P representing the resistance of the substrate, the value increases as the frequency increases.

In general, the surface depth in a conductor can be defined as:

Where μ is the permeability and σ is the conductivity.

18 is an internal cross-sectional view of a 10 μF multilayer ceramic capacitor of 2012 size.

에 반비례하여 감소하기 때문에 기판의 레지스턴스 R_p/l은 f₀ 이후에

에 비례하여 증가하게 되고 다음의 수학식과 같이 정의될 수 있다.
Assuming that the substrate of the multilayer ceramic capacitor is nickel, the surface depth at 50 MHz has a thickness of 1 μm. In the case of the multilayer ceramic capacitor of FIG. 18, since the average thickness is 1.25 μm, the surface effect is affected from several tens of MHz units of 50 MHz or less. In addition, as can be seen in Figure 18, since the thickness of the actual substrate is uneven, the surface effect is affected from a lower frequency than the actual, thereby increasing the resistance value of the substrate. If we assume that the effect of the surface starts from a certain frequency f ₀ , the surface depth

Since the decrease in inverse proportion to the resistance R _p / l of the substrate after the f ₀

It is increased in proportion to and can be defined as in the following equation.

Here, l 'represents the thickness of the layer of one substrate and R _dC is the resistance value of the substrate when there is no influence of the surface effect, and is represented by using the cross-sectional area A, the length L, and the conductivity σ of the substrate. Each parameter l ', L, A was extracted by measuring the actual value from the internal cross-sectional view of the multilayer ceramic capacitor. Since the real value of the multilayer ceramic capacitor increases from the frequency f ₀ when the surface effect starts to affect, the value of f ₀ is extracted from the frequency where the real value of the measurement data becomes the minimum.

From Equations 14 and 19,

Here, the ratio of the R _S 1 and the R _T value may be determined by k as in Equation 31 similarly to the relationship between the L _S 1 and the L _T value of Equation 23.

The value of R _S 1 can be obtained by substituting this value into Equation 30 from the value of R _P / l obtained in Equation 29, and the value of R _T can be obtained through Equation 31.

FIG. 19 illustrates parameters of unit lengths extracted for three models of a high-capacity multilayer ceramic capacitor having a size of 2012 according to the above process, and FIG. 20 substitutes the parameter of unit lengths described in FIG. 19 into Equation 20. This is a table showing the parameters of the fourth-order equivalent model extracted.

The modeling method 300 of the multilayer ceramic capacitor according to the exemplary embodiment of the present invention described above may be implemented in the form of software and performed on a computer. Such software may be implemented to be driven online or offline, and the computer device for performing this may also include a desktop computer, a server computer or a mobile device. Meanwhile, an embodiment of the present invention may include a computer readable recording medium including a program for performing the methods described herein on a computer. The computer-readable recording medium may include a program command, a local data file, a local data structure, or the like, alone or in combination. The media may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well-known and available to those skilled in the computer software arts. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape, optical recording media such as CD-ROMs and DVDs, magneto-optical media such as floppy disks, and magnetic media such as ROMs, And hardware devices specifically configured to store and execute program instructions. Examples of program instructions may include machine language code such as those generated by a compiler, as well as high-level language code that may be executed by a computer using an interpreter or the like.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the present invention. I will understand.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims below and equivalents thereof.

100: laminated ceramic capacitor 102: substrate
104: dielectric 106: external electrode

Claims (10)

In the computer modeling method of a multilayer ceramic capacitor comprising a layer region formed by stacking a plurality of substrates and an end region formed at the bottom of the layer region,
Forming an equivalent circuit corresponding to a unit layer having a predetermined length in the layer region, and calculating propagation constants and characteristic impedances of the equivalent circuit corresponding to the unit layer;
Generating an equivalent circuit corresponding to the multilayer ceramic capacitor using the calculated propagation constant and the characteristic impedance; And
Calculating each parameter of an equivalent circuit corresponding to the multilayer ceramic capacitor using the frequency characteristic of the multilayer ceramic capacitor;
Including,
The equivalent circuit corresponding to the unit layer
A first resistor and a first inductor connected in series between one end and the other end of the unit layer;
A second resistor connected in parallel between one end and the other end of the unit layer;
A second inductor connected in series with the second resistor;
A first capacitor connected in series with the second inductor; And
A third resistor connected in parallel with the first capacitor;
Modeling method of a multilayer ceramic capacitor comprising a.
delete The method of claim 1,
Values of the first resistor and the first inductor are equivalent resistance and equivalent inductance of an external electrode connected to the unit layer of the multilayer ceramic capacitor,
Values of the second resistor and the second inductor are equivalent resistance and equivalent inductance of the substrate included in the multilayer ceramic capacitor,
The value of the first capacitor is an equivalent capacitance between each substrate in the multilayer ceramic capacitor,
The value of the third resistor is a dielectric loss of the multilayer ceramic capacitor.
The method of claim 3,
The propagation constant is represented by the following equation

A modeling method of a multilayer ceramic capacitor, determined as follows. Where R _S is the resistance of the external electrode, L _S is the inductance of the external electrode, R _P is the resistance of the substrate, L _P is the inductance of the substrate, R _d is the dielectric loss, and C is the distance between the substrates. Capacitance)
The method of claim 3,
The characteristic impedance is represented by the following equation

A modeling method of a multilayer ceramic capacitor, determined as follows. Where R _S is the resistance of the external electrode, L _S is the inductance of the external electrode, R _P is the resistance of the substrate, L _P is the inductance of the substrate, R _d is the dielectric loss, and C is the distance between the substrates. Capacitance)
In the computer modeling method of a multilayer ceramic capacitor comprising a layer region formed by stacking a plurality of substrates and an end region formed at the bottom of the layer region,
Forming an equivalent circuit corresponding to a unit layer having a predetermined length in the layer region, and calculating propagation constants and characteristic impedances of the equivalent circuit corresponding to the unit layer;
Generating an equivalent circuit corresponding to the multilayer ceramic capacitor using the calculated propagation constant and the characteristic impedance; And
Calculating each parameter of an equivalent circuit corresponding to the multilayer ceramic capacitor using the frequency characteristic of the multilayer ceramic capacitor;
Including,
Generating an equivalent circuit corresponding to the multilayer ceramic capacitor may include
Calculating an equivalent impedance of the multilayer ceramic capacitor by assuming the layer area as a transmission line to which infinite loads are connected;
Calculating second and fourth order approximations of the calculated hyperbolic tangent values of the equivalent impedance using continuous partial approximation; And
Generating second and fourth approximation furnaces of the multilayer ceramic capacitor by applying the second and fourth approximation values to the calculated equivalent impedances of the multilayer ceramic capacitors, respectively;
Modeling method of a multilayer ceramic capacitor comprising a.
The method of claim 6,
The equivalent impedance of the secondary equivalent circuit is expressed by the following equation

(Wherein, Z _{2nd -} 2 _model is equivalent to the impedance of the equivalent circuit of the car, Z ₀ is the characteristic of the equivalent circuit corresponding to the impedance of the layer unit,

Is a propagation constant of an equivalent circuit corresponding to the unit layer, l is the length of the layer region, R _p is the resistance of the substrate, L _p is the inductance of the substrate, R _T is the resistance of the terminal region, and L _T is the Inductance of the terminal region, R _s is the resistance of the external electrode connected to the layer region, L _s is the inductance of the external electrode connected to the layer region, C is the capacitance between each substrate in the multilayer ceramic capacitor, R _d is the dielectric Loss)
The modeling method of a multilayer ceramic capacitor determined as follows.
The method of claim 6,
The equivalent impedance of the fourth equivalent circuit is expressed by the following equation

(Wherein, Z _{4th - model} 2 is an equivalent impedance of the secondary equivalent circuit, Z ₀ is the characteristic of the equivalent circuit corresponding to the impedance of the layer unit,

Is a propagation constant of an equivalent circuit corresponding to the unit layer, l is the length of the layer region, R _p is the resistance of the substrate, L _p is the inductance of the substrate, R _T is the resistance of the terminal region, and L _T is the Inductance of the terminal region, R _s is the resistance of the external electrode connected to the layer region, L _s is the inductance of the external electrode connected to the layer region, C is the capacitance between each substrate in the multilayer ceramic capacitor, R _d is the dielectric Loss)
The modeling method of a multilayer ceramic capacitor determined as follows.
The method of claim 6,
Computing each parameter of the equivalent circuit corresponding to the multilayer ceramic capacitor,
Calculating a parameter into the secondary near-field from an impedance measurement at the primary resonant frequency of the multilayer ceramic capacitor; And
Calculating a parameter into the quaternary near field from the calculated parameter into the secondary near field and impedance measurement at the secondary resonant frequency of the multilayer ceramic capacitor;
Modeling method of a multilayer ceramic capacitor comprising a.
A computer-readable recording medium containing a program for executing the method according to claim 1, 3 to 9 on a computer.

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