JP5246785B2 - Circuit model creation device, circuit model creation method, simulation device, and simulation method - Google Patents

Description

  The present invention relates to a circuit model creation apparatus and method for creating equivalent circuit model information of a passive element mounted on a surface-mount circuit board, and a simulation for simulating circuit characteristics of a circuit board using the equivalent circuit model information The present invention relates to an apparatus and a method.

  High-precision analysis of a printed circuit board (PCB) power supply network is indispensable for reducing unnecessary radiation and realizing stable operation of an integrated circuit.

  In recent years, the power consumption of LSIs has been increasing, and noise current has also increased with such trends. For this reason, reducing the input impedance of the power supply network is one of the most important items in the design. Various analysis methods have been proposed so far in order to enable the optimum design of the input impedance of the PCB power supply network (Patent Document 1). In these analyses, passive components such as multilayer ceramic chip capacitors, packages, LSIs, etc. are individually modeled as components and then combined to analyze the entire power supply network.

  Here, the electrical model of the surface-mount type multilayer ceramic chip capacitor is, firstly, the internal structure can be concealed, secondly, it can be used in common among users, and the time for model creation can be shortened. In addition, when an analysis is performed by inputting a detailed structure, it is generally necessary to use an S parameter model or an equivalent circuit model provided by a component manufacturer because it takes too much time. There is a need for a passive component model with high accuracy for various layouts while maintaining these advantages.

JP 2007-004418 A

  In a general high-frequency circuit power supply network, a surface mount type passive component model such as a chip capacitor is represented by an equivalent circuit model composed of passive elements R, L, and C as shown in FIG. . Here, the circuit constants R, L, and C of the surface mount type passive component model are created by measurement under certain conditions. For example, as shown in FIG. 22, in the analysis of the input impedance of the PCB power supply network including the capacitor, it is usual that the frequency and impedance of resonance and antiresonance do not coincide with the actual measurement. This is because the parasitic inductance in the capacitor model is different from the actual value.

  In addition, since a capacitor alone does not form a loop circuit, its parasitic inductance cannot be defined. In order to represent the parasitic inductance of the capacitor, the area of the loop formed by the capacitor and the feedback current flowing through the conductor pattern of the PCB is required. Since the L value is a constant, the conventional model always uses a parasitic inductance obtained by measurement under a certain condition. For this reason, the parasitic inductance value of the provided model is rarely adapted to the PCB layout that the user designs and analyzes.

  Originally, the parasitic inductance of the passive element is determined only after being mounted on the PCB, but it is impossible to know the mounting state at the time of creating the passive element model. This is the reason why it is difficult for the passive component manufacturer to prepare and provide a highly accurate model to the user.

  The present invention has been proposed in view of such circumstances, and a circuit model creation apparatus and method capable of improving the simulation accuracy of a power supply circuit with a relatively simple equivalent circuit model, and conventional experience. An object of the present invention is to provide a simulation apparatus and method capable of replacing a typical circuit design and contributing to improvement of design accuracy and reduction of design man-hours.

  As a means for solving the above-described problem, the present invention provides a circuit model creation device that creates equivalent circuit model information of a passive element that is surface-mounted on a circuit board, and a distance from a mounting surface to a ground layer through which a feedback current flows. Acquisition means for acquiring a change in parasitic inductance with a distance from the mounting surface to the ground layer as a variable for a basic equivalent circuit model corresponding to a passive element surface-mounted on a circuit board having a predetermined value; and the acquisition And a means for creating equivalent circuit model information having an arbitrary distance from the mounting surface to the ground layer by reflecting the change in the parasitic inductance obtained by the means in the basic equivalent circuit model.

Further, the present invention by executing a program for modeling by a computer, a circuit model creation method for creating an equivalent circuit model information of the passive element to be surface mounted on a circuit board, the feedback current from the mounting surface For a basic equivalent circuit model corresponding to a passive element surface-mounted on a circuit board where the distance to the flowing ground layer is a predetermined value, a change in parasitic inductance using the distance from the mounting surface to the ground layer as a variable is acquired. The equivalent circuit model information having an arbitrary distance from the mounting surface to the ground layer is created by reflecting the acquisition step process and the parasitic inductance change acquired by the acquisition step process in the basic equivalent circuit model. a process of creating step is performed in the computer, etc. of the passive element to be surface mounted to the circuit board To create a circuit model information.

  Further, the present invention provides a simulation apparatus for simulating circuit characteristics of a circuit board on which a passive element is surface-mounted, and the characteristics of the passive element and a ground in which a feedback current flows from a mounting surface of the circuit board on which the passive element is surface-mounted. A setting means for setting a distance to the layer, and a basic equivalent circuit model corresponding to a passive element surface-mounted on a circuit board having a predetermined distance from the mounting surface to the ground layer. Storage means for storing arbitrary equivalent circuit model information reflecting a change in parasitic inductance acquired as a variable, and an equivalent circuit corresponding to the distance from the mounting surface to the ground layer set by the setting means from the storage means Analysis means for reading model information and analyzing circuit characteristics using the read equivalent circuit model information.

The present invention, by executing the simulation program by the computer, a simulation method for simulating circuit characteristic of the circuit board surface mount passive components, and characteristics of the passive elements, the passive element surface The process of the setting step in which the distance from the mounting surface on the circuit board to be mounted to the ground layer where the feedback current flows is set, and the surface mounting on the circuit board where the distance from the mounting surface to the ground layer is a predetermined value The basic equivalent circuit model corresponding to the passive element is set by the process of the above setting step from the storage means for storing any equivalent circuit model information reflecting the change of the parasitic inductance acquired using the distance as a variable. Reads equivalent circuit model information corresponding to the distance from the mounting surface to the ground layer. A process of analyzing, the circuit characteristics by using the equivalent circuit model information is executed in the computer, the passive element to simulate circuit characteristics of the circuit board surface mounted.

  The present invention acquires a change in parasitic inductance in the basic equivalent circuit model using the distance from the mounting surface to the ground layer as a variable, reflects the acquired change in parasitic inductance in the basic equivalent circuit model, and changes the ground from the mounting surface to the ground. By creating equivalent circuit model information with an arbitrary distance to the layer, circuit characteristics according to the mounting state of the passive elements can be accurately expressed, so comparison of equivalent circuit models that can increase the simulation accuracy of power supply circuits Can be provided to users with simple and simple expressions.

  In addition, the present invention analyzes the circuit characteristics using the equivalent circuit model information corresponding to the distance from the mounting surface set by the setting means to the ground layer, thereby accurately adjusting the circuit characteristics according to the mounting state of the passive element. Since the simulation can be performed with good representation, it is possible to replace the conventional empirical circuit design and contribute to the improvement of design accuracy and the reduction of design man-hours.

It is a figure which shows the printed circuit board which is a power supply network of a general high frequency circuit. It is a figure which shows arrangement | positioning of the port in a surface mount type passive component model. It is a figure which shows the equivalent circuit model of a surface mount type passive component model. It is a figure which shows the frequency characteristic of the parasitic inductance of a capacitor | condenser. It is a figure which shows the structure which concerns on a circuit model creation apparatus. It is a figure which shows the image information output by an output part. It is a figure which shows the structure which concerns on a simulation apparatus. It is a flowchart with which it uses for description of the process performed by a simulation apparatus. It is a figure which shows the structure of a multilayer ceramic chip capacitor. It is sectional drawing of a multilayer ceramic chip capacitor. It is a figure which shows the frequency characteristic of the multilayer ceramic chip capacitor and bulk conductor of the same dimension. It is a figure which shows the electric current distribution obtained by the moment method. It is a figure which shows the circuit model which considered the multilayer ceramic chip capacitor as a stub transmission line. It is a figure which shows the frequency characteristic of the low resistance capacitor of (sigma) = 5.6 * 107 [S / m]. It is a figure showing the current distribution of 200 MHz which is a resonance point of the 7th resonance. It is a figure which shows the characteristic of the multilayer ceramic chip capacitor mounted in the printed circuit board. It is a figure which shows the impedance characteristic of the multilayer ceramic chip capacitor mounted in the printed circuit board. It is a figure which shows the structure of the equivalent circuit model of a multilayer ceramic chip capacitor It is a figure which shows the frequency characteristic of an actual measurement result, and the frequency characteristic of an equivalent circuit model. It is a figure which shows the comparison with an equivalent circuit model and a measurement result about the frequency characteristic of an inductance. It is a figure which shows the prior art example of surface mount type passive component models, such as a chip capacitor. It is a figure which shows the comparison with an equivalent circuit model and a measurement result about the frequency characteristic of an inductance.

  A circuit model creation apparatus to which the present invention is applied is an apparatus for creating an equivalent circuit model of a surface-mount circuit board on which passive elements such as a multilayer ceramic chip capacitor are mounted. A simulation apparatus to which the present invention is applied is an apparatus that simulates circuit characteristics of a circuit board using the equivalent circuit model created by the circuit model creation apparatus.

  In the present embodiment, circuit characteristics of an equivalent circuit model proposed in the present embodiment will be described prior to description of specific configurations of these circuit model creation apparatuses and simulation apparatuses.

  FIG. 1 is a diagram illustrating a printed circuit board 1 which is a power supply network of a general high-frequency circuit. The printed circuit board 1 is a power supply network that receives power supply from a DC voltage source 11 and is mounted with a high-frequency circuit 12 such as an LSI. That is, on the printed circuit board 1, the power supply pin 12a and the GND pin 12b of the high-frequency circuit 12 are connected to the power supply voltage line V and the ground line GND through the via holes 1a and 1b, respectively. Further, a capacitor 13 is surface-mounted on the printed circuit board 1 on the power supply voltage line V side on the path through which the feedback current of the high frequency circuit 12 flows for the purpose of absorbing the high frequency current component of the high frequency circuit 12.

  In order to analyze the characteristics of the power supply network of the printed circuit board 1 having such a configuration with high accuracy, it is indispensable for reducing unnecessary radiation and realizing stable operation of the integrated circuit. A noise voltage that disturbs the voltage of the DC voltage source 11 due to the operation of the high-frequency circuit 12 in the power supply network can be simply expressed as V = ZI according to Ohm's law.

  Here, Z is an input impedance of the power supply network, and I is a current caused by a noise source inside the high-frequency circuit 12. That is, the noise source inside the high-frequency circuit 12 can be approximated by a current source. The input impedance Z of the power supply network of the printed circuit board 1 is an impedance that allows the printed circuit board 1 side to be seen from the power supply pins 12 a and the GND pins 12 b of the high-frequency circuit 12.

  In this way, the parasitic inductance of the capacitor 13 which is a passive element is defined according to the mounting state of the printed circuit board 1. Therefore, since the capacitor 13 alone does not form a loop circuit, its parasitic inductance cannot be defined. In order to represent the parasitic inductance of the capacitor, it is necessary to consider the characteristics of the capacitor itself and the area of the loop formed by the feedback current flowing through the conductor pattern of the printed circuit board.

  In this way, in order to consider the area of the loop formed by the feedback current, the arrangement of the ports in the surface-mounted passive component model 2 proposed in this embodiment is shown in FIG. Here, an arrow A in FIG. 2 indicates an excitation port. In this surface-mounted passive component model 2, the distance h between the capacitor 21 and the ground 22 through which the feedback current flows is clearly shown. Since most of the magnetic flux generated by the capacitor 21 passes between the capacitor 21 and the ground 22, the parasitic inductance is defined by representing the total amount of magnetic flux generated by the current in the capacitor 21 approximately. As a result, the surface-mount passive component model 2 can reflect different parasitic inductances depending on the thickness of the printed wiring board and the layout pattern.

  An equivalent circuit model of the surface mount type passive component model 2 is shown in FIG. Whether or not the ground is explicitly defined is the most important difference from the conventional part model. Strictly speaking, it is determined depending on the measurement environment even in the conventional part model, but it is not specified under which ground layout these measurements are made. Therefore, when the conventional component model is used, it cannot be determined whether or not the parasitic inductance is suitable for the PCB layout shape to be designed.

  On the other hand, in the surface mount type passive component model 2, the problem of the conventional model described above can be solved by clearly indicating the distance between the component and the ground.

  Here, as the surface mount type passive component model 2, a plurality of models must be prepared individually according to the distance between the ground and the capacitor. As shown in FIG. 4, the frequency characteristic ΔL / Δf of the parasitic inductance of the capacitor is The distance h between the ground and the component does not change. Further, since the current concentrates on the bottom surface mainly due to the skin effect, the inductance of the high frequency capacitor can be easily corrected at every high frequency h between the ground and the component. For this reason, an equivalent circuit model is provided in which a correction inductance expressed as a function with a distance h between different grounds and a component as a variable is provided based on an equivalent circuit model at a distance h between any ground and the component. By doing so, the capacitor can be expressed by one equivalent circuit model.

  The surface-mounted passive component model 2 proposed as described above is created by a circuit model creation device 100 as shown in FIG.

  That is, the circuit model creation device 100 is a computer including an input unit 110 such as a keyboard, a CPU 120, a ROM 130, a RAM 140, a mass storage device 150 such as a hard disk or a flash memory, and a display unit 160 such as an LCD.

  The input unit 110 receives input information related to a passive element that is a model creation target. That is, the input unit 110 associates, as input information, the element characteristics of the passive element determined without depending on the mounting state and the distance from the mounting surface on which the passive element is surface-mounted to the ground layer where the feedback current flows. Entered information is input. The input unit 110 notifies the CPU 120 of input information.

  The CPU 120 reads out a model creation program stored in the large-capacity storage device 150, develops it in the RAM 140, and executes it, thereby realizing the following processing unit. That is, the CPU 120 is created by a basic equivalent circuit model creation unit 121 that creates a basic equivalent circuit model in which passive elements are surface-mounted based on input information notified from the input unit 110, and a basic equivalent circuit model creation unit 121. The parasitic inductance information acquisition unit 122 for acquiring a change in parasitic inductance when the mounting state of the basic equivalent circuit model is changed, and the equivalent circuit model information based on the information acquired by the parasitic inductance information acquisition unit 122 It comprises an equivalent circuit model information creation unit 123 that creates and outputs it.

  The basic equivalent circuit model creation unit 121 creates a basic equivalent circuit model in which passive elements are surface-mounted based on input information notified from the input unit 110. Specifically, the basic equivalent circuit model creation unit 121 passively applies a circuit board in which the distance from the mounting surface on which the passive element is surface-mounted to the ground layer through which the feedback current flows is a predetermined value input by the input unit 110. Create a basic equivalent circuit model with elements mounted on the surface.

  For example, in order to accurately express the mounting state when the passive element is mounted on the circuit board, the basic equivalent circuit model creation unit 121 uses the feedback path through which the feedback current flows in the first circuit model representing the characteristics of the passive element. A basic equivalent circuit model is created in which a second circuit model representing parasitic inductance is connected in series.

  The parasitic inductance information acquisition unit 122 performs the following processing to acquire the change in parasitic inductance when the mounting state is changed with respect to the basic equivalent circuit model created by the basic equivalent circuit model creation unit 121. Do. That is, the parasitic inductance information acquisition unit 122 acquires a change in parasitic inductance with the distance from the mounting surface to the ground layer as a variable for the basic equivalent circuit model. The change in the parasitic inductance may be obtained by performing an interpolation process such as a least square method on an actual measurement value measured using a circuit board having a different distance from the mounting surface to the ground layer, You may make it acquire by the analysis process which changes the parameter contained in a basic equivalent circuit model which is mentioned later.

  The equivalent circuit model information creation unit 123 reflects the change in the parasitic inductance acquired by the parasitic inductance information acquisition unit 122 in the basic equivalent circuit model, so that the equivalent circuit model information having an arbitrary distance from the mounting surface to the ground layer is obtained. create.

  As a first specific example, the equivalent circuit model information creation unit 123 represents the basic equivalent circuit model and the change in parasitic inductance acquired by the parasitic inductance information acquisition unit 122 with the distance from the mounting surface to the ground layer as a variable. Information corresponding to the function is created as arbitrary equivalent circuit model information.

  As a second specific example, as shown in FIG. 6, the equivalent circuit model information creation unit 123 is acquired by a basic equivalent circuit model and a parasitic inductance information acquisition unit 122 corresponding to each distance from the mounting surface to the ground layer. Information corresponding to the parasitic inductance is created as arbitrary equivalent circuit model information. That is, the equivalent circuit model information creation unit 123 arbitrarily sets the basic equivalent circuit model 171 created by setting the distance h from the mounting surface to the ground layer to 60 [μm], and the distance from the mounting surface to the ground layer. Image information in association with the parasitic inductance table 172 when changed is displayed on the display unit 160. The parasitic inductance is not limited to the case of displaying discrete values as in the parasitic inductance table 172, and a function that represents the distance from the mounting surface to the ground layer as a variable as in the first specific example described above. It may be displayed.

  Further, the equivalent circuit model information creation unit 123 is not limited to displaying the above-described model information on the display unit 160. For example, the same information is printed by a printing apparatus, and this information is attached as actual surface-mounted component information. You may make it provide to the user who uses surface mount components.

  The circuit model creation device 100 configured as described above acquires the change in parasitic inductance in the basic equivalent circuit model using the distance from the mounting surface to the ground layer as a variable, and uses the obtained change in parasitic inductance as the basic equivalent circuit. By reflecting the model and creating equivalent circuit model information with an arbitrary distance from the mounting surface to the ground layer, it is possible to accurately express the circuit characteristics according to the mounting state of the passive elements. An equivalent circuit model that can be increased can be provided to the user with a relatively simple expression. For example, the passive component manufacturer can provide a user who is a customer with highly accurate equivalent circuit parameters created by the circuit model creation device 100.

  In this way, a highly accurate circuit model can be provided because the inductance of a capacitor at high frequency concentrates the current on the bottom surface. Therefore, at high frequency, the function using the distance h from the mounting surface to the ground as a variable can be used. It is because it can correct | amend easily. In addition, equivalent circuit model information for adding a parasitic inductance determined by a distance h ′ different from the equivalent circuit model at a distance h from any mounting surface to the ground layer is as follows. This is because it can be expressed by a model.

  Next, a simulation apparatus 200 that simulates the circuit characteristics of the circuit board using the surface-mounted passive component model 2 created by the circuit model creation apparatus 100 having the above configuration will be described.

  As shown in FIG. 7, the simulation apparatus 200 is a computer including an input unit 210 such as a keyboard, a CPU 220, a ROM 230, a RAM 240, a mass storage device 250 such as a hard disk or a flash memory, and a display unit 260 such as an LCD. .

  The input unit 210 receives setting information in which the characteristics of the passive element and the distance from the mounting surface on which the passive element is surface-mounted to the ground layer on which the feedback current flows are set on the circuit board on which the passive element is surface-mounted. Is done. The input unit 110 notifies the CPU 120 of setting information.

  The mass storage device 250 stores information relating to the equivalent circuit model created by the circuit model creation device 100 described above.

  That is, the mass storage device 250 is obtained using this distance as a variable for a basic equivalent circuit model corresponding to a passive element surface-mounted on a circuit board having a predetermined distance from the mounting surface to the ground layer. Arbitrary equivalent circuit model information reflecting changes in parasitic inductance is stored. That is, the mass storage device 250 includes basic equivalent circuit model information 251 indicating basic equivalent circuit model in which a passive element is surface-mounted on a circuit board having a predetermined value from a mounting surface to a ground layer through which a feedback current flows. The basic circuit board model is stored in association with parasitic inductance information 252 indicating a change in parasitic inductance with the distance from the mounting surface to the ground layer as a variable. Here, the parasitic inductance information 252 is a look-up table that represents a change in parasitic inductance using a distance from the mounting surface to the ground layer as a variable as a function represented by a continuous value or a discrete value.

  The mass storage device 250 stores a program for simulating circuit characteristics of the circuit board.

  The CPU 220 reads out a simulation program stored in the large-capacity storage device 250, develops it in the RAM 240, and executes it, thereby realizing the following analysis unit 221.

  The analysis unit 221 reads the basic equivalent circuit model information 251 and the parasitic inductance information 252 from the mass storage device 250 according to the setting information input to the input unit 210, and analyzes circuit characteristics based on the read information. I do. Specifically, the analysis unit 221 reads from the large-capacity storage device 250 the basic equivalent circuit model and the change in parasitic inductance with the distance from the mounting surface of the basic circuit board model to the ground layer as a variable. The analysis unit 221 analyzes circuit characteristics using an equivalent circuit model in which parasitic inductance is corrected corresponding to the distance from the mounting surface to the ground layer indicated by the setting information. The analysis unit 221 displays the analysis result obtained by analyzing the circuit characteristics on the display unit 260.

  The simulation apparatus 200 having such a configuration performs a simulation on the circuit characteristics of the printed circuit board according to the flowchart shown in FIG.

  In step S1, a circuit model of the printed circuit board PCB designed by the user is input to the input unit 210. That is, the input unit 210 includes a characteristic of a passive element mounted on the printed circuit board PCB and a ground layer in which a feedback current flows from a mounting surface on which the passive element is surface-mounted in the printed circuit board PCB on which the passive element is surface-mounted. Setting information in which the distance to is set is input.

  In step S2, the analysis unit 221 selects an optimal parasitic inductance value by referring to the parasitic inductance information 252 of the mass storage device 250 based on the distance information from the mounting surface indicated by the setting information to the ground layer. To do. Thereby, the analysis unit 221 can select an equivalent circuit model most suitable for the cross-sectional structure of the printed circuit board to be designed.

  In step S3, the analysis unit 221 connects the equivalent circuit model of the passive element defined by the parasitic inductance selected in step S2 to the circuit board model.

  In step S4, the analysis unit 221 analyzes the power supply network input impedance for the circuit board model to which the equivalent circuit model of the passive element is connected in step S3.

  As described above, the simulation apparatus 200 analyzes the circuit characteristics using the equivalent circuit model in which the parasitic inductance is corrected in accordance with the distance from the mounting surface to the ground layer indicated by the setting information input by the input unit 210. By doing so, it is possible to perform simulation by accurately expressing circuit characteristics according to the mounting state of passive elements, so that it replaces the conventional empirical circuit design, contributing to improvement of design accuracy and reduction of design man-hours. be able to.

  By the way, when the surface mount type passive component model created by the circuit model creation device 100 is a multilayer ceramic chip capacitor configured by mutually laminating a plurality of opposing internal electrodes and dielectric layers. From the viewpoint of improving accuracy, it is desirable to create an equivalent circuit model by the following method.

  That is, from the viewpoint of improving accuracy, in the circuit model creation device 100, the parasitic inductance information acquisition unit 122 determines the distance from the mounting surface to the ground layer with respect to the equivalent circuit model created by the basic equivalent circuit model creation unit 121. When the change is changed, the change of the parasitic inductance in the higher frequency region than the basic self-resonance frequency of the multilayer ceramic chip capacitor is analyzed, and the analysis result is notified to the equivalent circuit model information creating unit 123 as the parasitic inductance information.

  In addition, the basic equivalent circuit model creating unit 121 is a circuit that shows parasitic inductance in a higher frequency region than the basic self-resonant frequency of the multilayer ceramic chip capacitor at both ends of the circuit model showing the circuit characteristics including the capacitance of the multilayer ceramic chip capacitor. An equivalent circuit model is created by connecting the models in series.

  Further, the basic equivalent circuit model creation unit 121 corresponds to each self-resonant frequency from the basic self-resonant frequency of the multilayer ceramic chip capacitor to the high frequency region as a circuit model indicating circuit characteristics including the capacitance of the multilayer ceramic chip capacitor. A model in which a plurality of resonant circuit models are connected in parallel is created.

  In the following, a specific method for deriving a basic equivalent circuit model of a multilayer ceramic chip capacitor with high accuracy will be described based on verification results using measured values.

As shown in FIGS. 9A and 9B, the multilayer ceramic chip capacitor 301 mounted on the surface of the printed circuit board 300 composed of the ground layer 300a and the dielectric layer 300b is shown in FIG. As shown in FIG. 2, a large number of laminated conductor plates are used to achieve a high capacitance. For example, even a small 1005 size (1.0 × 0.5 mm ² ) capacitor typically contains 100 or more plates. Here, since the mesh required for decomposing the thin plate structure of the three-dimensional full-wave electromagnetic simulation is very thin, an analysis method using such a mesh is unrealistic. In consideration of the fact that the multilayer ceramic chip capacitor 301 is composed of a large number of conductors, the plate and the insulator in the multilayer ceramic chip capacitor 301 are each one as long as the internal thin plate spacing is smaller than the spatial wave mode in the y direction. By treating it as an effective medium, frequency characteristics can be analyzed efficiently.

  Therefore, by treating the multilayer ceramic chip capacitor as one effective medium and using the two-dimensional moment method as shown below, the characteristics of the multilayer ceramic chip capacitor can be analyzed with high accuracy.

  FIG. 10 is a cross-sectional view of the multilayer ceramic chip capacitor on the xy plane. The xy plane is the same everywhere along the z-axis. A magnetic field perpendicular to the z-axis direction, that is, a TM field in the xy plane, can be treated as having only a z-direction current and electric field in the conductor. Each field has a static characteristic with respect to the angular frequency ω.

  This is because only the current in the z direction exists, and the vector potential at r shown in the following equation (1) has only elements in the z direction.

Here, μ ₀ is the magnetic permeability, v is the voltage of the cell through which the current flows, and J _z is the current density of the cell. The integral around the z coordinate is derived from the two-dimensional magnetic vector potential of the following equation (2).

  Here, S shows the cross-sectional area of all the metal thin plates. The electric field is represented by Az, and the scalar potential φ is represented by the following equation (3).

  In order to analyze bulk conductors, in many moment methods, Ohm's law Jz = Ez is used to represent the relationship between current density and electric field. In order to consider the unified distributed capacitance in the xy plane, the above relationship is changed to the following equation (4).

  Here, c and σ represent capacitance and conductivity for each unit volume, respectively. That is, Equation (4) is a z-direction capacitance based on a two-dimensional assumption.

  Substituting Equations (3) and (2) into Equation (4) yields an integral equation of current density Jz as shown in Equation (5) below.

  In the equation (5), the second term on the left side corresponds to the inductance jωL. This equation (5) can be regarded as an LCR series circuit model of each cell.

  Here, the integral equation of Equation (5) can be efficiently solved by the following moment method.

  First, the cross section of each conductor is divided into a plurality of rectangular cells. Considering the ground structure of the multilayer ceramic chip capacitor as shown in FIG. 10, the model has two conductor groups (p = 1, 2). Both the multilayer ceramic chip capacitor and the ground layer are divided into np cells. A basis function is defined for each conductor. Here, a set of pulse functions fpi (r) in which current flows uniformly in each cell, as shown in the following equation (6), is used.

When a basis function is used in the equation (6), the current density _Jz is expressed by the following equation (7).

Here, J _pi is the current distribution and constant to be obtained. Substituting equation (7) into equation (5), the following equation (8) is derived.

Here, S _qi is the cross-sectional area of each cell. When the centroids of all the rectangles are made coincident and a closed loop current loop equation of the following equation (9) is added, equation (8) becomes a linear equation of J _pi and δφ / δz.

Here, I is the total current amount of the conductor, and is an arbitrary boundary condition.

  Next, the electrical resistance of the multilayer ceramic chip capacitor is calculated by the following equation (10) based on the relationship between the scalar potential gradient δφ / δz obtained from the equation (8) and the total current I.

  Here, Z is an electrical resistance for each unit length.

  The equivalent parasitic resistance is expressed by the following equation (11).

  Further, from the equation (4), the capacitance is inversely proportional to the resistance R (ω) represented by the equation (11). Therefore, the equivalent capacitance C (ω) is expressed by the following equation (12).

Here, R _dc and C _dc are DC resistance and capacitance, respectively, as shown by the following equation (13).

  Once the equivalent capacitance is measured, the equivalent inductance is computed to subtract the capacitance element from the imaginary part of the electrical resistance and divided by jω.

  By the moment method as described above, for example, a multilayer ceramic chip capacitor having a size of 1005 and a capacitance of 0.1 μF can be analyzed. Bulk conductors having a geometric size equivalent to this multilayer ceramic chip capacitor can be analyzed and compared to obtain detailed frequency characteristics of the multilayer ceramic chip capacitor.

  As shown in FIG. 10, the embedded plate of the multilayer ceramic chip capacitor 301 has an interval h ′ in the outline of the capacitor and has an altitude h ″ from the surface of the printed circuit board 300 depending on the thickness of the pad electrode and the solder.

  Here, as a specific example, h ′ = 70 [μm], h ″ = 100 [μm], and ω = l = 400 [μm]. Also, the thickness of the dielectric as the distance from the mounting surface to the ground layer h is 100 [μm] When the conductivity of the plate is σ = 3.15 × 104 [S / m], it is measured so as to be compatible with the measurement resistance of 20 [mΩ]. It is divided into square cells and decreases exponentially as a whole, in order to obtain the proximity effect accurately, the ground layer is considered in the image method.

  FIG. 11A, FIG. 11B, and FIG. 11C are graphs showing the frequency characteristics of the calculated impedance, resistance, and inductance of the same dimension multilayer ceramic chip capacitor and bulk conductor, respectively. As is clear from these figures, the multilayer ceramic chip capacitor and the bulk conductor have different frequency characteristics exceeding the LC series resonance frequency of 30 [MHz]. The resistance and inductance of the multilayer ceramic chip capacitor are twisted at 60 MHz. When the frequency exceeds 100 [MHz], the characteristics of the two elements of the multilayer ceramic chip capacitor and the bulk conductor are suitable.

  These phenomena suggest that current is redistributed from the bottom edge of the conductor at frequencies where the inductive reactance exceeds the resistance.

  As is clear from these frequency characteristics, the mounting state of the printed circuit board was accurately represented by modeling in consideration of the parasitic inductance in the high frequency region than the basic self-resonant frequency of the multilayer ceramic chip capacitor. An equivalent circuit model can be derived.

  FIG. 12 is a graph showing the current distribution obtained by the moment method described above. Specifically, FIG. 12A, FIG. 12B, and FIG. 12C show contour diagrams of current distribution at frequencies of 10 MHz, 63 MHz, and 1 GHz, respectively. In the current distribution at 10 MHz, the current is distributed almost uniformly. At 1 GHz, the current is concentrated at the bottom, similar to the bulk conductor current distribution. As shown in FIG. 12B, at the second resonance frequency of 63 MHz, the current is concentrated around the center where the inductance is larger than in the case of the unified current distribution.

  Due to these phenomena, the multilayer ceramic chip capacitor can be regarded as a stub transmission line. A circuit model 400 in which the multilayer ceramic chip capacitor 301 is regarded as the stub transmission line 401 in this way is shown in FIG. In general, a line length of 0.4 [mm] is too short for resonance at 60 MHz. However, it resonates due to strong wavelength reduction due to the large dielectric constant of the insulating medium. For example, the inductance increase as shown in FIG. 11C can be regarded as λ / 2 resonance of the stub transmission line, and is reflected in the calculated current distribution of FIG.

  Here, the reason why the other stub transmission line resonance does not appear at a higher frequency is that the resistance component of the multilayer ceramic chip capacitor at the target frequency affects.

For example, as shown in FIGS. 11C and 12C, the current is concentrated again at the bottom corner due to a large resistance exceeding the λ / 2 resonance frequency. In order to confirm this experimentally, FIG. 14 shows an analysis of a low-resistance capacitor with σ = 5.6 × 10 ⁷ [S / m]. From the results shown in FIG. 14, it is clear that the impedance has many resonance points that essentially exceed the series LC resonance frequency. FIG. 15 shows a current distribution at 200 MHz, which is the resonance point of the seventh resonance, as a specific example. As shown in FIG. 15, the current distribution shows a unique pattern that is a strong resonance in the x and y directions. As is apparent from these results, the multilayer ceramic chip capacitor can be modeled as a stub transmission line.

  Another main factor for accurate capacitor modeling is the external inductance, which is a characteristic damaged by the mounting state in which the multilayer ceramic chip capacitor is mounted. In order to analyze the relationship between the frequency characteristics and the distance from the mounting surface to the ground layer, the distance from the three different mounting surfaces to the ground layer is set to h = 60, 100, and 200 μm on the printed circuit board. The characteristics of the mounted multilayer ceramic chip capacitor were analyzed, and the analysis results are shown in FIG.

  FIGS. 16A, 16B, and 16C are graphs showing the frequency characteristics of impedance, the frequency characteristics of resistance, and the frequency characteristics of inductance, respectively. 16A and 16C show that the impedance and the inductance increase in proportion to the distance h from the mounting surface to the ground layer. On the other hand, as shown in FIG. 16B, it is shown that the resistance decreases in proportion to the distance h from the mounting surface to the ground layer due to the proximity effect in both directions.

  Changing the frequency characteristics of the capacitor according to the user layout requires a different model depending on the distance h from the mounting surface to the ground layer. Therefore, a model creation method when the distance h is changed for one model corresponding to the distance h from a specific mounting surface to the ground layer is shown below. This is a method based on the following actual measurement results.

  First, the resistance of the resistance does not change greatly due to a change in the distance h from the mounting surface to the ground layer, compared to the inductance. Second, since the capacitance mainly affects the impedance change in the frequency domain, the inductance at a frequency lower than the LC resonance can be ignored. Third, because of the skin effect, almost all of the current is concentrated on the bottom plate, so that the inductance at a lower frequency than the resonance of λ / 2 can be approximated by changing the external inductance, ie the inductance of the bottom plate.

  Based on the above first to third analysis results, if the distance h from the mounting surface to the ground layer is different, the frequency characteristics of the multilayer ceramic chip capacitor are as shown in the following equation (15). It can be compensated by changing the external inductance of the model.

Here, L _ex is an external inductance.

As a specific example, assuming that the current having a frequency of 5 [GHz] is concentrated at the edge of the bottom plate and assuming that the frequency is sufficiently high, replacing L _ex in the equation (15) with L (5 GHz), The following equations (16) and (17) are obtained.

FIG. 17 is a graph showing an impedance curve when the distance h from the mounting surface to the ground layer is changed from h = 100 [μm] to h = 60 [μm] or 200 [μm].
Here, when the distance h from the mounting surface to the ground layer is h = 100 [μm], the corresponding parasitic inductance is 43 [pH]. When the distance h from the mounting surface to the ground layer is h = 60 [μm], the corresponding parasitic inductance is 20 [pH]. As can be seen from FIG. 17, the equivalent circuit model change curve compensated by using the above equation (17) with respect to the equivalent circuit model under the condition where the distance h is 100 [μm] is measured with high accuracy. And fits.

  FIG. 18 shows the structure of an equivalent circuit model 500 of a multilayer ceramic chip capacitor created on the basis of the analysis results described above.

  The equivalent circuit model 500 is composed of two main parts as shown in FIG. That is, the equivalent circuit model 500 includes an LR parallel circuit block 501 that models a transmission line inside a capacitor, and two external impedance model blocks 502 a and 502 b that are symmetrically separated from the LR parallel circuit block 501. Is done. Here, the external impedance model blocks 502a and 502b are models representing an external inductance and a skin effect measured by geometric information indicating a capacitor and a distance from a mounting surface on which the capacitor is mounted to a ground layer.

  The LR parallel circuit block 501 is an LCR ladder circuit arranged at the center of the equivalent circuit model 500, and transmits a self-resonant frequency above the LC series resonance that is the basic self-resonant frequency of the multilayer ceramic chip capacitor. It is a model representing line characteristics. Further, the number of stages of the LCR ladder circuit is determined by the specific resistance of the multilayer ceramic chip capacitor.

  In the case of a low resistance capacitor, an LCR ladder circuit having a larger number of stages is required. In the LR parallel circuit block 501, since each resonance phenomenon appears in a different frequency range, each block can express a behavior independent of other parts.

All parameters other than _Lex are equal and independent of the distance from the mounting surface to the ground layer. Once the parameters are determined by measurement or electromagnetic simulation, the parameters that change when changing the distance from the mounting surface to the ground layer, using the above equation (17), to compensate for the external inductance L _ex Can be obtained. That is, the user can change the capacitor model so that L _ex most closely matches the PCB configuration.

Each parameter of the equivalent circuit model 500 can be determined from one measurement. First, the external inductance L _ex, which changes according to the distance from the mounting surface to the ground layer is calculated using equation (17). Here, the external inductance L _ex changes with h _total = h + h ′ + h ″ as shown in FIG. 10. Here, h ′ and h ″ are usually difficult to measure with high accuracy.

Therefore, h ′ + h ″ can be determined by comparing L _ex calculated by the moment method with the measured inductance. In this way, the distance from the mounting surface to the ground layer is determined by the moment method. The corresponding L _ex can be calculated.

In order to verify the accuracy of the above-described equivalent circuit model, the frequency characteristic of the created equivalent circuit model is compared with the actual measurement result. The actually measured multilayer ceramic chip capacitor has the same parameters as in the simulation state, the size is 1.0 mm × 0.5 mm ² , 0.1 μF, and the distance from the mounting surface to the ground layer is 0.06 to 0.2 mm. Use the ones changed to The frequency characteristics of the multilayer ceramic chip capacitor are measured by a 2-port parallel measurement method.

First, a model parameter of h = 100 [μm] is obtained based on the actual measurement result. Subsequently, L _ex that changes in accordance with the distance from the mounting surface to the ground layer is calculated using the above-described equation (15). In this actual measurement result, for example, h ′ + h ″ is estimated as approximately 170 μm. Further, in the LR parallel circuit block 501, the necessary ladder circuit number N is, for example, a frequency band of 5 [GHz]. It is assumed that N = 6 that accurately represents the measurement result.

  FIG. 19 is a comparison result comparing the frequency characteristics of the actual measurement results and the frequency characteristics of the equivalent circuit model in which the distance from the mounting surface to the ground layer is h = 100 μm. FIGS. 19A, 19B, and 19C are graphs showing the frequency characteristics of impedance, the frequency characteristics of resistance, and the frequency characteristics of inductance, respectively. Note that an equivalent circuit model in which the number of stages of the ladder circuit is N = 1 is shown in FIG. 19 as a comparative example.

  Table 1 below shows parameters generated as a result of each equivalent circuit model shown in FIG.

  From the comparison results shown in FIG. 19, it is clear that the equivalent circuit model designed with N = 6 matches the actual measurement result with higher accuracy than the equivalent circuit model designed with N = 1.

  FIG. 20 is a graph showing a comparison between an equivalent circuit model designed with N = 6 and an actual measurement result with respect to the frequency characteristic of the inductance. In FIG. 20, “h = 60 μm” and “h = 200 μm” indicate the frequency characteristics of the equivalent circuit model in which the distance from the mounting surface to the ground layer is changed to h = 60 μm and h = 200 μm, respectively. That is, these two equivalent circuit models are obtained by changing the characteristics of the models by the compensation method using the equation (15) as described above with reference to the equivalent circuit model of “h = 100 μm”. As shown in FIG. 20, in these equivalent circuit models, it is possible to accurately predict the change in the frequency characteristic of the inductance due to the distance from the mounting surface to the ground layer.

  As a comparative example, when the external inductance is not changed in accordance with the change in the distance from the mounting surface to the ground layer, the equivalent circuit model of “h = 60” and “h = 200 μm” is used as the error with respect to the actually measured value in the 1 GHz inductance. Each is about 15%. On the other hand, in the equivalent circuit model in which the external inductance is changed according to the change in the distance from the mounting surface to the ground layer, the errors with respect to the actual measurement values are 6% and 3%, respectively, compared with the above comparative example. Model accurately.

  As described above, the circuit model creation apparatus 100 can derive a precise physical system model using the two-dimensional moment method for analyzing the current distribution of the multilayer ceramic chip capacitor. Specifically, the circuit model creation apparatus 100 can derive an equivalent circuit model with less modeling error by approximating a multilayer conductor plate, which is a physical model of a multilayer ceramic chip capacitor, to a uniform distributed capacitance. Further, the circuit model creation apparatus 100 can clearly represent the kink of the frequency response measured using the moment method by the calculated current distribution. In addition, the circuit model creation device 100 can derive an equivalent circuit model with high accuracy so that the multilayer ceramic chip capacitor is similar to the resonance of the transmission line higher than the resonance frequency of the series LC circuit. The circuit model creation device 100 can express the characteristics of an actual multilayer ceramic chip capacitor only for low-dimensional resonance because of the balance between conductivity and dielectric constant.

  Based on the above analysis results, the circuit model creation device 100 can create an equivalent circuit model including a circuit as a transmission line, a skin effect, and an external inductance. In addition, the circuit model creation device 100 can create an equivalent circuit model that accurately matches the measured impedance result by deriving an equivalent circuit model in consideration of the distance from the mounting surface to the ground layer. The model created by the circuit model creation device 100 in this way can improve the accuracy of the distribution network simulation, for example.

  In addition, this invention is not limited only to the above embodiment, Of course, a various change is possible in the range which does not deviate from the summary of this invention.

DESCRIPTION OF SYMBOLS 1 Printed circuit board, 1a, 1b Via hole, 2 Surface mount type passive component model, 11 DC voltage source, 12 High frequency circuit, 12a Power supply pin, 12b GND pin, 13 Capacitor, 21 Capacitor, 22 Ground, 100 Circuit model creation apparatus, 110, 210 Input unit, 120, 220 CPU, 121 Basic equivalent circuit model creation unit, 122 Parasitic inductance information acquisition unit, 123 Equivalent circuit model information creation unit, 130, 230 ROM, 140, 240 RAM, 150, 250 Mass storage Device, 160, 260 Display unit, 171 Equivalent circuit model, 172 Parasitic inductance table, 200 Simulation device, 210 Input unit, 221 Analysis unit, 250 Mass storage device, 251 Basic equivalent circuit model information, 252 Parasitic inductor Wardrobe information, 300 a printed circuit board, 300a ground layer, 300b a dielectric layer, 301 multilayer ceramic chip capacitor, 400 the circuit model, 401 stub transmission line, 500 equivalent circuit model, 501 parallel circuit block, 502a external impedance model block

Claims (10)

In a circuit model creation device for creating equivalent circuit model information of passive elements surface-mounted on a circuit board,
For the basic equivalent circuit model corresponding to the passive element surface-mounted on the circuit board where the distance from the mounting surface to the ground layer where the feedback current flows is a predetermined value, the parasitic distance with the distance from the mounting surface to the ground layer as a variable Obtaining means for obtaining a change in inductance;
A circuit model creation comprising creation means for creating equivalent circuit model information in which the distance from the mounting surface to the ground layer is reflected by reflecting the change in the parasitic inductance obtained by the obtaining means in the basic equivalent circuit model apparatus.   The acquisition means changes a parasitic inductance with respect to the basic equivalent circuit model in which a first circuit model representing the characteristics of the passive element and a second circuit model representing a parasitic inductance caused by a feedback path through which the feedback current flows are connected in series. The circuit model creation device according to claim 1, wherein: The passive element is a multilayer ceramic chip capacitor,
The acquisition means analyzes the change in the parasitic inductance in the higher frequency region than the basic self-resonance frequency of the multilayer ceramic chip capacitor when the distance from the mounting surface to the ground layer is changed. The circuit model creation apparatus according to claim 1, wherein a change in parasitic inductance with respect to the circuit model is acquired.   The basic equivalent circuit model shows parasitic inductance in a higher frequency region than the basic self-resonant frequency of the multilayer ceramic chip capacitor at both ends of the first circuit model showing circuit characteristics including capacitance of the multilayer ceramic chip capacitor. 4. The circuit model creation device according to claim 3, wherein the circuit model creation device is an equivalent circuit model in which the second circuit models are respectively connected in series.   The first circuit model is a model in which a plurality of resonant circuit models corresponding to each self-resonant frequency ranging from a basic self-resonant frequency to a high frequency region of the multilayer ceramic chip capacitor are connected in parallel. The circuit model creation device according to claim 4.   The creation means includes information associating the basic equivalent circuit model with a function in which a change in the parasitic inductance obtained by the obtaining means is represented by a variable representing a distance from the mounting surface to the ground layer as a variable. The circuit model creation device according to claim 1, wherein the circuit model creation device is created as equivalent circuit model information.   The creating means uses the information associating the basic equivalent circuit model and the parasitic inductance acquired by the acquiring means corresponding to each distance from the mounting surface to the ground layer as the arbitrary equivalent circuit model information. The circuit model creation apparatus according to claim 1, wherein the circuit model creation apparatus creates the circuit model. A circuit model creation method for creating equivalent circuit model information of passive elements surface-mounted on a circuit board by executing a program for model creation by a computer ,
For the basic equivalent circuit model corresponding to the passive element surface-mounted on the circuit board where the distance from the mounting surface to the ground layer where the feedback current flows is a predetermined value, the parasitic distance with the distance from the mounting surface to the ground layer as a variable Processing of an acquisition step of acquiring a change in inductance; and
By reflecting the change of the parasitic inductance acquired by the process of the acquisition step in the basic equivalent circuit model, the process of the creation step of creating the equivalent circuit model information having an arbitrary distance from the mounting surface to the ground layer is performed.
A circuit model creation method for causing the computer to create equivalent circuit model information of a passive element that is surface-mounted on a circuit board . In a simulation device that simulates the circuit characteristics of a circuit board with surface mounted passive elements,
Setting means for setting the characteristics of the passive element and the distance from the mounting surface of the circuit board on which the passive element is surface-mounted to the ground layer through which the feedback current flows,
The basic equivalent circuit model corresponding to the passive element surface-mounted on the circuit board having a predetermined distance from the mounting surface to the ground layer reflects any change in parasitic inductance obtained using the distance as a variable. Storage means for storing the equivalent circuit model information of
A simulation comprising: reading from the storage means equivalent circuit model information corresponding to the distance from the mounting surface to the ground layer set by the setting means; and analyzing means for analyzing circuit characteristics using the read equivalent circuit model information apparatus. A simulation method for simulating circuit characteristics of a circuit board on which a passive element is surface-mounted by executing a simulation program by a computer ,
A process of a setting step in which the characteristics of the passive element and the distance from the mounting surface of the circuit board on which the passive element is surface-mounted to the ground layer through which the feedback current flows;
The basic equivalent circuit model corresponding to the passive element surface-mounted on the circuit board having a predetermined distance from the mounting surface to the ground layer reflects any change in parasitic inductance obtained using the distance as a variable. The equivalent circuit model information corresponding to the distance from the mounting surface to the ground layer set by the processing of the setting step is read from the storage means for storing the equivalent circuit model information of the circuit, and the circuit characteristics are read using the read equivalent circuit model information. Analysis step processing to analyze
Is a simulation method for simulating the circuit characteristics of a circuit board on which a passive element is surface-mounted .

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