KR101155886B1 - Direct up-conversion digital-to-rf transmitter using scrambler - Google Patents

Abstract

PURPOSE: An up-converting digital-RF transmitter using scrambler is provided to increase the whole linearity index of a transmitter system. CONSTITUTION: Decoding units(33,34) convert a digital signal into a signal of unit-weighted-code in a binary-code type. Scrambling units(35,36) scramble an order of converted output signals. A plurality of digital RF(Radio Frequency) converting cells is connected to the multiple-bit output signals of the scrambling unit. A differential RF signal is generated by mixing a differential carrier signal and a control signal. A local oscillator or a frequency synthesizer(61) generate the differential carrier signal.

Description

DIRECT UP-CONVERSION DIGITAL-TO-RF TRANSMITTER USING SCRAMBLER}

The present invention relates to an RF transmitter, and more particularly, to an RF transmitter of a direct upconversion method for transmitting data in a wireless communication system.

In a conventional wireless communication system, a transmitter is implemented using a superheterodyne scheme. The superheterodyne method converts a signal of a low frequency band containing actual information into a signal of an intermediate frequency (IF) and then transmits it on a high frequency carrier, which is complicated in hardware and consumes a lot of power. There was a downside.

In order to overcome the disadvantages of the conventional superheterodyne scheme, a direct up-conversion scheme is employed in which the baseband signal is directly frequency-converted into a carrier signal without using an intermediate frequency. It is becoming.

1 is a block diagram illustrating an example of a conventional direct upconversion RF transmitter, and FIG. 2 is a block diagram illustrating another example of a conventional direct upconversion RF transmitter.

Referring to FIG. 1, the conventional direct upconversion RF transmitter 10 includes a first and a second digital-to-analog converter (D / A) 11, 12, and a first and a second. 2 includes a mixer 15, 16, an adder 17, a drive amplifier 19, a power amplifier 20, a duplexer 21 and an antenna 22.

In a modem (MODEM, modulator and demodulator, not shown), a digital baseband in-phase signal I _BB and quadrature signal Q _BB are provided.

The first digital-to-analog converter 11 receives the in-phase signal I _BB and converts it into a first analog signal, and the first mixer 15 converts the first analog signal and the first carrier signal sin ω _LO t. ) Is mixed to generate a first mixed signal up-modulated to the frequency of the RF band.

The second digital-to-analog converter 12 receives the quadrature signal Q _BB and converts it into a second analog signal, and the second mixer 16 converts the second analog signal and the second carrier signal cos ω _LO t. ) Is mixed to generate a second mixed signal up-modulated to the frequency of the RF band.

An adder 17 combines the first and second mixed signals. In a real circuit implementation, the signal is loaded in the magnitude of the current, so it is only necessary to short it.

The driving amplifier 19 and the power amplifier 20 amplify the output signal of the adder 17 and provide a final transmission signal to the antenna 22. For example, when the baseband signal is modulated by an amplitude modulation scheme, the amplifiers 19 and 20 are implemented in the form of a linear amplifier.

The duplexer 21 performs duplexing between the amplifiers 19 and 20 and the antenna 22 to distinguish the transmission signal from the reception signal, thereby preventing crosstalk between the signals.

Referring to FIG. 2, the conventional direct up-conversion RF transmitter 10a includes first and second low pass filters disposed at the rear ends of the first and second digital-to-analog converters 11 and 12, respectively. 13, 14 and the bandpass filter 18 disposed at the rear end of the adder 17 has the same configuration as the RF transmitter 10 of FIG.

Low pass filters 13, 14 remove harmonics of the first and second analog signals output from digital-to-analog converters 11, 12, and band pass filters 18 add the adder 17. Remove harmonics of the output signal.

1 and 2, the conventional RF transmitters 10 and 10a of the direct upconversion method include the mixers 15 and 16, the adder 17, the amplifiers 19 and 20, and perform direct upconversion. Including a plurality of analog elements such as the filters 13, 14, 18 increases the complexity of the circuit, the area occupied on the semiconductor integrated circuit increases. In addition, these analog circuits can also be sensitively changed in performance due to changes in external conditions such as error in semiconductor manufacturing process, instability of supply voltage and temperature.

Shakeshaft (US 6937848) solves the above problem by connecting a plurality of Gilbert-cell mixer cells in parallel and controlling each of them as a digital signal, thereby converting the function of the digital-to-analog converter and frequency up-conversion. A digital-to-RF converter that integrates the mixer's functions was constructed and applied to the transmitter circuit system as shown in FIG.

The present invention minimizes the disadvantages caused by the analog circuit by reducing the weight of the analog circuit and increasing the weight of the digital circuit as compared to the conventional analog-based direct up-conversion RF transmitter. As such, it is common to refer to an RF transmitter as a digital-RF transmitter, in which an analog circuit plays a role of a digital circuit. In the above invention, each cell is divided into a most significant bit (MSB) cell and a least significant bit (LSB) cell, and each MSB cell or each LSB cell is designed as an element of the same size, and each cell is a thermometer-code decoder. It is connected to and controlled by a thermometer-code decoder.

As such, if each cell is designed to be unit-weighted, the number of cells increases, which increases the design area of the semiconductor layout and increases the design area, but increases the linearity of the transmission system as a whole. . However, due to practical semiconductor process limitations, it is difficult to make each cell perfectly the same size, and this semiconductor process error causes the linearity of the transmission system to be poor. This error is particularly evident when observing the transmitter's output spectrum and causes adjacent channel interference within the signal band range on the wireless communication system. In other words, it creates a signal distortion to cause unnecessary frequency components to be detected around the channel to send a signal.

The present invention has been made in view of the above problems, and controls each digital-RF conversion cells of the same size as a digital signal, even if a size difference error between each device or cells inevitably occurs in the process It is an object of the present invention to provide an RF transmitter that includes a scrambler that makes the distortion components due to the signals scatter properly in the outer band than the signal band channel.

In other words, digital-to-RF conversion cell is realized due to the limitation of semiconductor process by implementing RF transmitter by connecting a plurality of digital-to-RF conversion cells that directly convert a multi-bit digital control signal from the baseband to an RF signal in parallel. The purpose of the present invention is to improve the performance of a transmitter by dispersing the signal arrangement using a scrambler in order to prevent a decrease in transmitter linearity or an increase in adjacent channel interference caused by a slight difference in size.

The present invention for achieving the technical problem relates to a direct up-conversion digital-RF transmitter using a scrambler, unit-weighted multi-bit digital signal in the form of binary-code (binary-code) a decoder unit for converting the signal into a code; A scrambler unit for mixing an arrangement order between a plurality of output signals converted from the decoder unit into equal-weighted-codes; A double-balanced signal connected to one of the multi-bit output signals of the scrambler unit and generating a differential RF signal by mixing a control signal having a 1-bit width and a differential carrier signal for up-modulating the control signal A plurality of digital-RF conversion cells having a structure; A local oscillator or frequency synthesizer for generating the differential carrier signal; Characterized in that it comprises a.

In addition, the decoder unit, characterized in that it comprises a thermometer-code decoder (thermometer-code decoder).

In addition, the decoder unit is characterized in that it comprises a binary decoder (binary decoder).

The scrambler unit may include a plurality of swapper cells, each having two input units and an output unit and determining whether two signals of the input unit are directly connected to the output unit or inverted by the selection signal. It features.

The swapper cell may further include: a butterfly multiplexer unit having two input units and an output unit, respectively, and determining whether two signals of the input unit are connected to the output unit as they are or are inverted by the selection signal; A memory unit which stores a state of the selection signal; And a logic unit generating a next selection signal by referring to two input unit signals included in the swapper cell and a state of a selection signal stored in a current memory unit. Characterized in that it comprises a.

The digital-RF conversion cell also converts the 1-bit wide control signal into a differential signal to produce a differential data input signal and is synchronized by a sequential logic circuit element comprising a latch or flip-flop, the differential carrier A first switch pair unit for mixing the differential data input signal and the differential carrier signal based on a voltage level of the signal; And a second switch pair unit connected to the first switch pair unit and performing mixing of the differential data input signal and the differential carrier signal based on the voltage level of the differential data input signal. Characterized in that it comprises a.

The differential carrier signal may include a first carrier signal and a second carrier signal complementary to each other, and the first switch pair may include a source connected to a ground voltage, a gate and a drain to which the first carrier signal is applied. A first transistor comprising a; And a second transistor including a source connected to the ground voltage, a gate and a drain to which the second carrier signal is applied. Characterized in that it comprises a.

In addition, the second switch pair unit is connected to the drain of the first transistor, the first differential data switch pair to electrically connect one of the first path or the second path selectively according to the voltage level of the differential data input signal. ; And a second differential data switch pair connected to the drain of the second transistor and electrically connecting one of the third path and the fourth path according to the voltage level of the differential data input signal. Characterized in that it comprises a.

The differential data input signal may include a first input signal and a second input signal complementary to each other, and the first differential data switch pair may include a source connected to a drain of the first transistor, and the second input signal. A third transistor including a gate to which an input signal is applied and a drain connected to the first node; And a fourth transistor including a source connected to the drain of the first transistor, a gate to which the first input signal is applied, and a drain connected to a second node. The second differential data switch pair includes: a fifth transistor including a source connected to the drain of the second transistor, a gate to which the first input signal is applied, and a drain connected to the first node; And a sixth transistor including a source connected to the drain of the second transistor, a gate to which the second input signal is applied, and a drain connected to the second node. Characterized in that it comprises a.

In addition, a plurality of output matching circuit is connected to each of the differential output of the digital-RF conversion cell connected in parallel and matching the output impedance; And further comprising:

In addition, a balun for converting the differential high-frequency output signal from the differential output of the plurality of digital-RF conversion cells connected in parallel to a single-output signal; Further comprising:

A bandpass filter connected to the output of said balun having a single-output signal line; And further comprising:

In addition, the memory unit, a latch or flip-flop; The logic unit may include an XOR gate; Characterized in that it comprises a.

The multi-bit digital signal is also a sigma-delta modulated oversampling and noise shaped signal.

The digital-RF conversion cell converts the 1-bit control signal into a differential signal to form a differential data input signal, and based on the voltage level of the differential carrier signal, for the differential data input signal and the differential carrier signal. A first switch pair for performing mixing; A second switch pair unit connected to the first switch pair unit and configured to mix the differential data input signal and the differential carrier signal based on a voltage level of the differential data input signal; And a constant bias voltage connected to the first switch pair part to apply a current source to control the amount of current flowing through the first switch pair part and the second switch pair part or a gate node corresponding thereto, and the source node is grounded. Seventh transistor; Characterized in that it comprises a.

According to the present invention as described above, the digital-RF transmitter provides an effect of increasing the linearity indicator of the overall transmission system compared to the prior art. For example, it can reduce the adjacent channel leakage ratio around the signal band channel on the transmitter's output spectrum and increase the signal to noise and distortion ratio.

In addition, even if the degree of mismatch or distribution between digital-RF conversion cells is not known in detail, the resulting effect can be shaped out-of-band so that it can be in-band. The distortion of the band) can be made to have no significant effect.

Since the object of the present invention is to implement a transmitter system integrated around a digital circuit, from the viewpoint of compensating the analog high frequency signal of the final output stage by using a scrambler which is a digital circuit, the original digital-RF transmitter is also implemented.

On the other hand, although the circuit on the semiconductor chip is slightly added, it can be composed only of digital circuits composed of devices having a relatively small scale, which contributes little to the total transmitter area and power consumption.

In particular, the transmitter including the binary decoder instead of the thermometer-code decoder can reduce the complexity of the circuit configuration and the power consumption as shown in FIGS. 16 and 17.

1 is a diagram illustrating an example of a conventional general analog-based direct up-conversion transmitter.
2 is a diagram illustrating another example of a conventional analog-based direct up-conversion transmitter.
3 is a diagram illustrating a detailed configuration for each element included in a digital-RF conversion cell.
4 shows an example of a single-differential output conversion unit included in a digital-RF conversion cell.
FIG. 5 illustrates an example of a cell of a double balanced or Gilbert-cell mixer structure included in a digital-RF conversion cell. FIG.
FIG. 6 illustrates another example of a cell of a double-balanced or Gilbert-cell mixer structure included in a digital-RF conversion cell according to the present invention. FIG.
7 is a functional illustration of a digital-RF transmitter according to the prior art.
8 illustrates a configuration of a digital-RF transmitter according to an embodiment of the present invention.
9 illustrates a configuration of a digital-RF transmitter according to an embodiment of the present invention.
10 illustrates a configuration of a digital-RF transmitter according to an embodiment of the present invention.
11 illustrates a configuration of a digital-RF transmitter according to an embodiment of the present invention.
12 illustrates a configuration of a digital-RF transmitter according to an embodiment of the present invention.
FIG. 13 is a diagram illustrating an embodiment of a scrambler included in the present invention. FIG.
14 is a view showing an embodiment of a swapper cell included in the scrambler included in the present invention.
FIG. 15 illustrates another embodiment of a swapper cell included in a scrambler included in the present invention. FIG.
16 illustrates one embodiment of a thermometer-code decoder included in the present invention.
17 illustrates an embodiment of a binary decoder included in the present invention.

Specific features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings. It is to be noted that the detailed description of known functions and constructions related to the present invention is omitted when it is determined that the gist of the present invention may be unnecessarily blurred.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings.

A direct up-conversion digital-RF transmitter using a scrambler according to an embodiment of the present invention will be described with reference to FIGS. 3 to 17 as follows.

3 is a diagram illustrating a digital-RF conversion cell 40 included in an RF transmitter according to an embodiment of the present invention.

Referring to FIG. 3, the digital-RF conversion cell includes a single-differential output conversion unit 47, a latch or flip-flop 48 synchronized by the sampling clock signal CLK _BB , and a Gilbert cell having a dual-balance structure ( 50).

The digital-RF conversion cell converts the control signal DATA1 having a 1-bit width from the scrambler section to be described later by the single-differential output conversion unit 47 into the differential data signals D1 + and D1- and then latches or Sampling is done with sequential logic circuits such as flip-flops.

The differential input signals BB1 + and BB1- generated as a result of the sampling include the first phase input signal BB1 + and the second phase input signal BB1- in phase, and the differential carrier signals LO1 + and LO1- are generated. A differential RF signal comprising a first phase carrier signal LO1 + on phase and a second phase carrier signal LO1- on a portion, the output signal resulting from the mixing of the differential carrier signal and the differential input signal is the first phase RF signal on phase; (RF1 +) and the second RF signal (RF1-) on the site.

The first switch pair unit 42 may mix the differential input signals BB1 + and BB1- and the differential carrier signals LO1 + and LO1- based on the voltage levels of the differential carrier signals LO1 + and LO1-. And a first NMOS transistor Q1 and a second NMOS transistor Q2.

The first NMOS transistor Q1 includes a source connected to a ground voltage, a gate and a drain to which the first carrier signal LO1 + is applied.

The second NMOS transistor Q12 includes a source connected to the ground voltage, a gate and a drain to which the second carrier signal LO1 is applied.

The second switch pair part 43 is connected to the first switch pair part 42 and based on the voltage levels of the differential input signals BB1 + and BB1-, the differential input signals BB1 + and BB1- and the differential carrier signal ( Mixing for LO1 + and LO1- may be performed and may include a first differential data switch pair 44 and a second differential data switch pair 45.

The first differential data switch pair 44 is connected to the drain of the first NMOS transistor Q1 and selectively selects one of the first path and the second path according to the voltage level of the differential input signals BB1 + and BB1-. Connect

The second differential data switch pair 45 is connected to the drain of the second NMOS transistor Q2 and selectively selects one of the third path and the fourth path according to the voltage level of the differential input signals BB1 + and BB1-. Connect

Here, the first path is a path for electrically connecting the drain of the first NMOS transistor Q1 and the first node N1, and the second path is a drain and the second path of the first NMOS transistor Q1. The path electrically connects the node N2. The third path is a path electrically connecting the drain of the second NMOS transistor Q2 and the first node N1. The fourth path is the second path. The path electrically connects the drain of the NMOS transistor Q2 and the second node N2.

That is, the first differential data switch pair 44 may have one of the first NMOS transistor Q1, the first node N1, and the second node N2 according to the voltage levels of the differential input signals BB1 + and BB1-. , And the second differential data switch pair 45 is connected to the second NMOS transistor Q2 and the first node N1 and the second node N2 according to the voltage levels of the differential input signals BB1 + and BB1-. ) Can optionally be linked.

The first differential data switch pair 44 may include a third NMOS transistor Q3 and a fourth NMOS transistor Q4.

The third NMOS transistor Q3 includes a source connected to the drain of the first NMOS transistor Q1, a gate to which the second input signal BB1-1 is applied, and a drain connected to the first node N1.

The fourth NMOS transistor Q4 includes a source connected to the drain of the first NMOS transistor Q1, a gate to which the first input signal BB1 + is applied, and a drain connected to the second node N2.

In addition, the first differential data switch pair 44 turns on one of the third and fourth NMOS transistors Q3 and Q4 and turns off the other according to the voltage levels of the differential input signals BB1 + and BB1-. As a result, one of the first path and the second path may be selectively connected.

The second differential data switch pair 45 may include a fifth NMOS transistor Q5 and a sixth NMOS transistor Q6.

The fifth NMOS transistor Q5 includes a source connected to the drain of the second NMOS transistor Q2, a gate to which the first input signal BB1 + is applied, and a drain connected to the first node N1.

The sixth NMOS transistor Q6 includes a source connected to the drain of the second NMOS transistor Q2, a gate to which the second input signal BB1-1 is applied, and a drain connected to the second node N2.

The second differential data switch pair 45 turns on one of the fifth and sixth NMOS transistors Q5 and Q6 and turns off the other according to the voltage levels of the first differential input signals BB1 + and BB1-. As a result, one of the third path and the fourth path may be selectively connected.

4 is a diagram illustrating an embodiment 47 of single-differential output conversion, which is a component of the digital-RF conversion cell 40 included in the RF transmitter according to an embodiment of the present invention.

One path is connected to the differential data signal D1 + after passing through two inverters 71 and 72, and the other is connected to the differential data signal D1- after passing through one inverter 73.

FIG. 5 is a diagram illustrating another embodiment 50a of the Gilbert cell which is a component of the digital-RF conversion cell 40 included in the RF transmitter according to the embodiment of the present invention.

Referring to FIG. 5, rather than grounding the sources of the first NMOS transistor Q1 and the second NMOS transistor Q2 like the Gilbert cell 50 of FIG. 3, each node is connected to one node and is connected between the ground and the node. Inserting a current source 46 in the control to flow a constant current. This has the advantage of reducing the effect of the input common-mode voltage level of the differential carrier signal on the differential RF signal.

FIG. 6 is a diagram illustrating another embodiment 50b of the Gilbert cell, which is a component of the digital-RF conversion cell 40 included in the RF transmitter according to the embodiment of the present invention.

Referring to FIG. 6, when the seventh NMOS transistor which replaces the role of the current source 46 of FIG. 5 is inserted, and the gate node is fixed to a constant bias voltage VBIAS, the input common mode voltage level mentioned above becomes Similarly, the effect on the differential RF signal can be reduced.

7 is a diagram functionally showing a digital-RF transmitter 30 according to the prior art. Referring to FIG. 7, a conventional digital-RF transmitter includes a plurality of digital-RF conversion cells 31 and 32 and a frequency synthesizer or a local oscillator 61 connected in parallel.

The in-phase path of the direct upconverting RF transmitter is connected by connecting a plurality of (n) digital-RF conversion cells in parallel (all input / output terminals except the control signal stage having a 1-bit width) in parallel. 1-bit wide control of each digital-RF converter for n-bit wide digital in-phase / quadrature signals (I, Q) located in the phase path and quadrature path and coming from the digital baseband. Each signal is divided and applied, and a clock signal CLK _BB is applied to all digital-RF conversion cells to be synchronized, that is, to be sampled at the same time. The differential carrier signal input of each digital-RF conversion cell is labeled as a single signal in the figure but is actually a differential signal.

The frequency synthesizer or local oscillator 61 provides a high frequency differential carrier signal to each digital-RF conversion cell. For example, a signal corresponding to sin ω _LO t may be applied to a digital-RF conversion cell in an in-phase path, and a signal corresponding to cos ω _LO t may be applied to a digital-RF conversion cell in a quadrature path.

8 is a diagram illustrating an embodiment 30a of a digital-RF transmitter according to the present invention. According to FIG. 8, in one embodiment of the digital-RF transmitter according to the present invention, the thermometer-code decoders 33 and 34, the scramblers 35 and 36, and the plurality of digital-RF conversion cells 31 and 32 connected in parallel are provided. And a frequency synthesizer or local oscillator (61).

The multi-bit (m-bit in the figure) digital signals delivered in the digital baseband are in binary code form. In order to improve the linearity of the transmission system, each digital-RF conversion cell should be designed to have the same size, and the same-weighted-code in the binary code to control these same size cells based on the binary code signal coming from the baseband. The decoders 33 and 34 converting the data into two are required.

Controlling n digital-RF conversion cells with n signal lines having the same-weight-code by the decoder, as mentioned above, results in a small size difference of each device caused by the error in the semiconductor process. This adversely affects the linearity of the entire transmission system. Therefore, the insertion of a scrambler to be described later in FIGS. 13, 14 and 15 between the decoder and the same-weight-code controlled digital-RF conversion cells has less influence on the linearity of the transmitter system. Distortion components near the channel band in the spectrum are reduced.

The frequency synthesizer or local oscillator 61, like the conventional digital-RF transmitter of FIG. 7, provides a high frequency differential carrier signal to each digital-RF conversion cell. For example, a signal corresponding to sin ω _LO t may be applied to a digital-RF conversion cell in an in-phase path, and a signal corresponding to cos ω _LO t may be applied to a digital-RF conversion cell in a quadrature path. Alternatively, two differential carrier signals corresponding to two paths may be inverted and applied. However, only phase differences corresponding to 90 degrees need to exist. Alternatively, as mentioned above, a signal in the form of a square wave may be applied instead of a signal in the form of a sine wave.

9 shows another embodiment 30b of a digital-RF transmitter according to the present invention. 9, the sigma-delta modulators 37 and 38 are inserted in front of the decoder in the transmitter structure of FIG. 8, which is an embodiment of the digital-RF transmitter according to the present invention.

The sigma-delta modulators 37 and 38 modulate the l-bit signal coming from the baseband according to the sigma-delta modulation scheme, and output an oversampled and noise shaped m-bit signal. At this time, the sigma-delta modulators 37 and 38 have a higher frequency than that of the baseband signal coming from the modem because the sigma-delta modulators 37 and 38 are synchronized to the clock CLK _BB even though the signal input thereto has a wider data bit width than the signal to be output. Oversampled to ensure that the output signal has improved resolution. This results in a signal with a higher signal-to-noise ratio due to oversampling and noise shaping, even though the number of digital-to-RF converter cells to be connected in the back is rather small.

10 shows another embodiment 30c of a digital-RF transmitter according to the present invention. Referring to FIG. 10, when an output matching circuit 51 is added to the final output stage in the structure of FIG. 8, the output stage impedance is matched to a specific impedance, so that a signal is better transmitted to a circuit or a block to be connected to the rear stage than without an output matching circuit. It is possible to make it possible.

FIG. 11 is a view showing another embodiment 30d of the digital-RF transmitter according to the present invention, in which the balun 52 is added to the final output terminal in the structure of FIG. 8, and FIG. 12 is a digital according to the present invention. FIG. 11 shows another embodiment 30e of the RF transmitter, in which a band pass filter 18 is added in the structure of FIG.

FIG. 13 is a diagram illustrating an embodiment of a scrambler 35 or 36 included in the present invention. According to FIG. 13, each of the scramblers included in the digital-RF transmitter according to the present invention has two input units and an output unit, and it is determined whether the two signals of the input unit are directly connected to the output unit or inverted by the selection signal. It may include a plurality of swapper cells (100, swapper cells).

In particular, FIG. 13 shows that the 4-bit binary code is converted into 16 equally-weighted-codes by the decoder (I0-I15) and then scrambled while passing through a plurality of swapper cells, thereby dispersing the arrangement order. In this case, a total of 32 swapper cells are required.

At this time, the equal-weighted-code signals I0 to I15 before passing through the scrambler and the equal-weighted-code signals O0-O15 after passing are equivalent to each other, that is, the number of signal lines that are on (1). The number of signal lines and off (0) are the same, but the arrangement is different. For example, the same-weighted-code signal 0000,0000,1111,1111 before passing through the scrambler may be converted to 0101,0101,0101,0101, etc. after passing through the scrambler, such that the number of zeros and one The numbers are the same but the order is different.

The arrangement of the swapper cell 100 is similar to the butterfly architecture used to implement the Fast Fourider Transform (FFT) algorithm.

FIG. 14 is a diagram illustrating an embodiment of a swapper cell 100 included in a scrambler included in the present invention. According to FIG. 14, each of the swapper cells 100 that may be included in the scrambler included in the digital-RF transmitter according to the present invention has two input units and an output unit, and two signals of the input unit are directly outputted by the selection signal. A butterfly multiplexer unit 101 determining whether to be connected or inverted to each other, a memory unit 102 storing a state of the selection signal, and two included in the swapper cell The logic unit 103 may generate a next selection signal by referring to the input unit signal and the state of the selection signal currently stored in the memory unit 102.

FIG. 15 is a diagram illustrating another embodiment of a swapper cell 100c included in a scrambler included in the present invention. Referring to FIG. 15, a latch or flip-flop may be included in the memory unit 102 of the swapper cell 100c which may be included in the scrambler included in the digital-RF transmitter according to the present invention. Logic unit 103 may include XOR gates 105 and 106.

FIG. 16 is a diagram showing an embodiment of the thermometer-code decoder 33a included in the present invention, and FIG. 17 is a diagram showing an embodiment of the binary decoder 33b included in the present invention.

While the present invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. It will be appreciated by those skilled in the art that numerous changes and modifications may be made without departing from the invention. Accordingly, all such appropriate modifications and changes, and equivalents thereof, should be regarded as within the scope of the present invention.

33,34: decoder 35,36: scrambler
31,32: digital-to-RF conversion cell 61: frequency synthesizer or local oscillator
37, 38: sigma-delta modulator 51: output matching circuit
52: balun 18: bandpass filter
100: swapper cell 101: butterfly multiplexer
102: memory section 103: logic section
105,106: XOR gate

Claims (15)

In the direct upconversion digital-RF transmitter using a scrambler,
A decoder unit for converting a multi-bit digital signal from a binary-code form to a unit-weighted-code form;
A scrambler unit for mixing an arrangement order between a plurality of output signals converted from the decoder unit into equal-weighted-codes;
A double-balanced signal connected to one of the multi-bit output signals of the scrambler unit and generating a differential RF signal by mixing a control signal having a 1-bit width and a differential carrier signal for up-modulating the control signal A plurality of digital-RF conversion cells having a structure; And
A local oscillator or frequency synthesizer for generating the differential carrier signal; Direct up-conversion digital-RF transmitter using a scrambler, characterized in that it comprises a.
The method of claim 1,
The decoder unit,
A direct upconverting digital-RF transmitter using a scrambler, comprising a thermometer-code decoder.
The method of claim 1,
The decoder unit,
Direct up-converting digital-RF transmitter using a scrambler, characterized in that it comprises a binary decoder.
The method of claim 1,
The scrambler unit,
A scrambler comprising a plurality of swapper cells each having two input parts and an output part and determining whether the two signals of the input part are directly connected to the output part or inverted by the selection signal; Direct up-conversion digital-RF transmitter.
The method of claim 4, wherein
The swapper cell,
A butterfly multiplexer portion each having two input portions and an output portion and determining whether the two signals of the input portion are directly connected to the output portion or inverted by the selection signal;
A memory unit which stores a state of the selection signal; And
A logic unit configured to generate a next selection signal by referring to two input unit signals included in the swapper cell and a state of a selection signal stored in a current memory unit; Direct up-conversion digital-RF transmitter using a scrambler, characterized in that it comprises a.
The method of claim 1,
The digital-RF conversion cell,
Converting the 1-bit wide control signal into a differential signal to produce a differential data input signal, synchronized by a sequential logic circuit element including a latch or flip-flop, the differential based on the voltage level of the differential carrier signal A first switch pair for mixing the data input signal and the differential carrier signal; And
A second switch pair unit connected to the first switch pair unit and configured to mix the differential data input signal and the differential carrier signal based on a voltage level of the differential data input signal; Direct up-conversion digital-RF transmitter using a scrambler, characterized in that it comprises a.
The method according to claim 6,
The differential carrier signal includes a first carrier signal and a second carrier signal complementary to each other,
The first switch pair portion,
A first transistor including a source connected to a ground voltage, a gate to which a first carrier signal is applied, and a drain; And
A second transistor including a source connected to the ground voltage, a gate and a drain to which the second carrier signal is applied; Direct up-conversion digital-RF transmitter using a scrambler, characterized in that it comprises a.
The method according to claim 6,
The second switch pair portion,
A first differential data switch pair connected to the drain of the first transistor and electrically connecting one of the first path and the second path according to the voltage level of the differential data input signal; And
A second differential data switch pair connected to the drain of the second transistor and electrically connecting one of a third path and a fourth path according to a voltage level of the differential data input signal; Direct up-conversion digital-RF transmitter using a scrambler, characterized in that it comprises a.
The method of claim 8,
The differential data input signal includes a first input signal and a second input signal complementary to each other,
The first differential data switch pair is
A third transistor including a source connected to the drain of the first transistor, a gate to which the second input signal is applied, and a drain connected to the first node; And
A fourth transistor including a source connected to the drain of the first transistor, a gate to which the first input signal is applied, and a drain connected to a second node; Including;
The second differential data switch pair is
A fifth transistor including a source connected to the drain of the second transistor, a gate to which the first input signal is applied, and a drain connected to the first node; And
A sixth transistor including a source connected to the drain of the second transistor, a gate to which the second input signal is applied, and a drain connected to the second node; Direct up-conversion digital-RF transmitter using a scrambler, characterized in that it comprises a.
The method of claim 1,
An output matching circuit each connected to a differential output unit of a plurality of digital-RF conversion cells connected in parallel and matching output impedances; Direct up-converting digital-RF transmitter using a scrambler, characterized in that it further comprises.
The method of claim 1,
A balun for converting a differential high frequency output signal from a differential output portion of a plurality of digital-RF conversion cells connected in parallel to a single output signal; Direct up-conversion digital-RF transmitter using a scrambler, characterized in that it further comprises.
The method of claim 11,
A bandpass filter connected to the output of the balun having a single-output signal line; Direct up-converting digital-RF transmitter using a scrambler, characterized in that it further comprises.
The method of claim 5, wherein
The memory unit may include a latch or flip flop; Including,
The logic unit may include an exclusive OR gate; Direct up-conversion digital-RF transmitter using a scrambler, characterized in that it comprises a.
The method of claim 1,
The multi-bit digital signal,
A direct upconverting digital-RF transmitter using a scrambler, characterized in that it is a sigma-delta modulated oversampling and noise shaped signal.
The method of claim 1,
The digital-RF conversion cell,
A first switch pair unit converting the 1-bit control signal into a differential signal to form a differential data input signal and performing mixing of the differential data input signal and the differential carrier signal based on a voltage level of the differential carrier signal ;
A second switch pair unit connected to the first switch pair unit and configured to mix the differential data input signal and the differential carrier signal based on a voltage level of the differential data input signal; And
A bias voltage is applied to the gate node so as to be connected to the first switch pair, and to control the amount of current flowing through the first switch pair and the second switch pair. A seventh transistor; Direct up-conversion digital-RF transmitter using a scrambler, characterized in that it comprises a.

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