KR101154389B1 - Pixel Cell, Image Sensor Adopting The Pixel Cell, and Image Processing System Including The Image Sensor - Google Patents

Abstract

Pixels of the image sensor are provided. The pixel may include a photoelectric conversion element formed on a second semiconductor pattern, at least one transistor operatively coupled to the photoelectric conversion element and separated from the second semiconductor pattern, and a signal charge generated in the photoelectric conversion element. And a transfer gate formed in the second semiconductor pattern to transfer to at least one transistor. The photoelectric conversion device includes a first conductive region formed in the second semiconductor pattern and a region of the second conductive type formed in the second semiconductor pattern to surround the region of the first conductive type.

Image sensor, pixel, photoelectric conversion element, fill factor

Description

Pixel, Image Sensor Adopting The Pixel Cell, and Image Processing System Including The Image Sensor

1 is a plan view showing a pixel array portion of a conventional image sensor;

FIG. 2 is a cross-sectional view of a unit pixel when cut along the line II ′ of FIG. 1;

3 is a perspective view schematically showing an image sensor according to an embodiment of the present invention;

4 is a plan view showing a portion of a pixel array of an image sensor according to an embodiment of the present invention;

5 is a cross-sectional view of a unit pixel when cut along the line II-II ′ of FIG. 4;

6 is a schematic block diagram of an image sensor including a pixel array according to an embodiment of the present invention;

7 is a block diagram schematically illustrating a system including the image sensor of FIG. 6 according to an embodiment of the present invention.

The present invention relates to an image sensor, and more particularly to a pixel of an image sensor.

Recently, the digital revolution is progressing rapidly, and one of the representative products is the digital camera. Key factors that determine the quality of digital cameras are optical lenses and image sensors. The light from the lens is converted into an electrical signal by the image sensor for good image quality.

A typical image sensor is composed of a pixel array, that is, a plurality of pixels arranged in a two-dimensional matrix, each pixel is generated in the photodiode and the photodiode to generate a signal charge by the incident light (photon) And an element for transferring and outputting signal charges. According to the transfer and output method of the signal charge, the image sensor is classified into a charge coupled device (CCD) type image sensor (hereinafter referred to as 'CD image sensor') and a complementary metal oxide semiconductor (CMOS) type image sensor (hereinafter referred to as 'CMOS'). The image sensor). The CD image sensor uses a plurality of MOS capacitors to transfer and output charges. The signal charge of each pixel is sequentially transferred to adjacent MOS capacitors by applying an appropriate voltage to the gate of the MOS capacitor over time. The CMOS image sensor uses a plurality of transistors for each pixel, and the signal charge generated in the photodiode is output after being converted into a voltage in each pixel.

While the CD image sensor has less noise and better image quality than the CMOS image sensor, the CMOS image sensor has the advantages of low production cost and low power consumption. That is, CMOS image sensors have the advantages of low power capability, single voltage current, low power consumption, compatibility with integrated CMOS circuits, random access of image data, and reduced cost of using standard CMOS technology. Accordingly, application fields of CMOS image sensor are widely extended to digital cameras, smart phones, personal digital assistants (PDAs), notebooks, security cameras, barcode detectors, high definition TVs (HDTVs), high resolution cameras, and toy supplies.

1 shows a portion of a pixel array of a conventional CMOS image sensor. Referring to FIG. 1, a typical pixel is formed in each of the active regions 13 of a semiconductor substrate electrically isolated by an isolation region 15 and includes a photodiode and a plurality of transistors. Each of the active regions 13 may be divided into a first active region 13A in which a photodiode is formed and a second active region 13B in which a plurality of transistors are formed, which are connected to each other and are located on the same semiconductor substrate. . The transfer gate 21, the reset gate 23, the source follower gate 25, and the selection gate 27 are positioned on the second active region 13B. The transfer gate 21 is positioned adjacent to the first active region 13A, and the impurity diffusion region formed in the second active region between the transfer gate 21 and the reset gate 23 is the floating diffusion region 29. A source follower gate 25 is electrically connected to the floating diffusion region 29. The impurity diffusion region formed in the second active region between the reset gate 23 and the source follower gate 25 is the reset diffusion region 31. An impurity diffusion region 33 is formed in the second active region between the source follower gate 25 and the selection gate 27, and an impurity diffusion region 35 is formed in the second active region outside the selection gate 27. Each gate and its impurity active regions constitute a transistor.

Referring to Figure 2 will be described in more detail the vertical cross-sectional structure of a conventional pixel. FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1, showing a vertical structure of a conventional pixel. Referring to FIG. 2, the photodiode includes an n-type region 17 and a p-type region 19 formed in the first active region 13A. The floating diffusion region 29 is electrically connected to the source follower gate 25 through the local wiring 37.

In such a conventional image sensor, photodiodes and gates are formed on the same active region 13 and a portion 13B of the active region 13 must be allocated for the transistors. In other words, only a portion 13A of the active region 13 is used for the photodiode. Therefore, in the conventional image sensor, there is a limit in increasing the fill factor indicating the ratio of the photodiode to the pixel. In addition, light incident on the target pixel may be reflected by the wiring or gate of the target pixel, in particular obliquely incident light, to reach an adjacent pixel to cause signal cross-talk.

Accordingly, the present invention provides a pixel having a new structure, an image sensor using the same, and an image processing system including the image sensor.

An image sensor according to an exemplary embodiment for achieving the object of the present invention comprises: a first semiconductor pattern and a second semiconductor pattern facing each other with an interlayer insulating layer therebetween; A photoelectric conversion element formed on the second semiconductor pattern; And at least one transistor formed in the first semiconductor pattern and operatively coupled to the photoelectric conversion element in order to sense signal charge generated in the photoelectric conversion element.

In this embodiment, the photoelectric conversion element may be a photodiode including an n-type region formed inside the second semiconductor pattern and a p-type region formed on the surface of the second semiconductor pattern to surround the n-type region. .

In this embodiment, the image sensor further comprises first and second charge collection regions formed in the first semiconductor pattern and the second semiconductor pattern and electrically connected to each other to collect signal charges generated in the photoelectric conversion element. The at least one transistor may be operatively coupled to the first and second charge collection regions.

The image sensor may include: first and second charge collection regions formed in the first semiconductor pattern and the second semiconductor pattern and electrically connected to each other to collect signal charges generated by the photoelectric conversion element; The at least one transistor may include a first transistor for sensing signal charges of the first and second charge collection regions and a second transistor for resetting. At this time, the drain of the first transistor and the second transistor are connected to each other to form a common drain, the gate of the first transistor is electrically connected to the first and second charge collection regions, the first charge collection The region may serve as a source region of the second transistor.

The image sensor may include: first and second charge collection regions formed in the first semiconductor pattern and the second semiconductor pattern and electrically connected to each other to collect signal charges generated by the photoelectric conversion element; The at least one transistor includes a first transistor for sensing signal charges of the first and second charge collection regions and a second transistor for resetting; The semiconductor device may further include a transfer gate formed between the interlayer insulating layer and the second semiconductor pattern to transfer signal charges generated by the photoelectric conversion element to the second charge collection region.

In this embodiment, the image sensor further comprises a transfer gate formed between the interlayer insulating layer and the second semiconductor pattern to transfer the signal charge generated in the photoelectric conversion element to the first and second charge collection regions. It may include.

In this embodiment, the image sensor further comprises a transfer gate formed between the interlayer insulating layer and the second semiconductor pattern to transfer the signal charge generated in the photoelectric conversion element to the first and second charge collection regions. And the photoelectric conversion element is a diode including an n-type region formed inside the second semiconductor pattern and a p-type region formed on a surface of the second semiconductor pattern to surround the n-type region, wherein the second charge collection The region may be formed in the p-type region outside the transfer gate to be separated from the n-type region.

In this embodiment, the image sensor may further include a color filter formed on the second semiconductor pattern. The image sensor may contact the second semiconductor pattern. Alternatively, a buffer layer may be further interposed between the image sensor and the color filter.

An image sensor according to an exemplary embodiment for achieving the object of the present invention comprises: a first semiconductor pattern and a second semiconductor pattern facing each other with an interlayer insulating layer therebetween; A photoelectric conversion element formed on the second semiconductor pattern; A transfer gate positioned below the photoelectric conversion element and configured to transfer signal charges generated by the photoelectric conversion element to a second charge collection region of the second semiconductor pattern; A first charge collection region formed in the first semiconductor pattern and electrically connected to the second charge collection region; A source follower gate electrically connected to the first and second charge collection regions and formed on the first semiconductor pattern; First and second drain regions formed on first semiconductor patterns on both sides of the source follower gate; And a reset gate formed on the first semiconductor pattern between the first drain region and the first charge collection region.

In the present embodiment, the photoelectric conversion element is a diode including an n-type region formed inside the second semiconductor pattern and a p-type region formed on a surface of the second semiconductor pattern to surround the n-type region. The first charge collection region may be formed in the second semiconductor pattern outside the transfer gate to be spaced apart from the n-type region.

In this embodiment, the interlayer dielectric layer includes a first interlayer dielectric layer and a second interlayer dielectric layer, and electrical connection between the first charge collection region and the second charge collection region is: the first interlayer insulation layer; A first contact plug penetrating a layer and connected to the second charge collection region; A local conductive pattern formed on the first interlayer insulating layer and electrically connected to the first contact plug; The second contact plug penetrates the second interlayer insulating layer to connect the first charge collection region to the local conductive pattern.

In this embodiment, the interlayer dielectric layer includes a first interlayer dielectric layer and a second interlayer dielectric layer, and electrical connection between the first charge collection region and the second charge collection region is: the first interlayer insulation layer; A first contact plug penetrating a layer and connected to the second charge collection region; A local conductive pattern formed on the first interlayer insulating layer and electrically connected to the first contact plug; And a second contact plug that penetrates the second interlayer insulating layer and connects the first charge collection region and the local conductive pattern, wherein the local conductive pattern penetrates the first interlayer insulating layer. The third contact plug may be electrically connected to a source follower gate.

In this embodiment, the image sensor may further include metal wires for applying an appropriate bias voltage to the transfer gate and the reset gate inside the interlayer insulating layer.

The image sensor may include: a second drain region formed in the first semiconductor pattern; The semiconductor device may further include a selection gate formed on the first semiconductor pattern between the second drain region and the first source region.

The image sensor may include: a second drain region formed in the first semiconductor pattern; And a selection gate formed on the first semiconductor pattern between the second drain region and the first source region, wherein a metal wiring for applying an appropriate bias voltage to the selection gate is formed inside the interlayer insulating layer. Can be located.

According to an exemplary embodiment of the present invention, a pixel includes: a photoelectric conversion element formed on a second semiconductor pattern; And at least one transistor operatively coupled to the photoelectric conversion element and formed in the first semiconductor pattern away from the second semiconductor pattern.

An image processing system according to an exemplary embodiment for achieving the object of the present invention comprises: a processor; And an image sensor coupled to the processor, wherein the image sensor includes a plurality of pixels, each pixel being operatively coupled to the photoelectric conversion element and the photoelectric conversion element formed on a second semiconductor pattern. At least one transistor formed in the first semiconductor pattern away from the semiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more readily apparent from the following description of preferred embodiments with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the present specification, when it is mentioned that a layer is on another layer or substrate, it means that it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween. In the drawings, the thicknesses and sizes of regions, patterns, and layers are exaggerated for clarity. In addition, in various embodiments of the present specification, terms such as first, second, and third are used to describe various regions, patterns, layers, and the like, but these regions, patterns, and layers are defined by the terms. It should not be. Also, the term is only used to distinguish one particular region, pattern or layer from another region, pattern or layer. Thus, the film quality referred to as the first layer (pattern or region) of one embodiment may be referred to as the second layer (pattern or region) in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment.

As used herein, for example, "a first element is operatively coupled to a second element" means that a particular terminal of the first element is directly connected to a specific terminal of the second element or indirectly through another conductive medium. do. The first element and / or the second element is not particularly limited thereto and may be, for example, a transistor, an impurity doped region, or various conductive wirings.

For example, "a transistor is operatively coupled to a photodiode" indicates that the impurity region of the photodiode is used as a source region (or drain region) of the transistor, or the impurity region of the photodiode and the source region of the transistor ( Or the drain region) may be connected to each other, or the impurity region of the photodiode may be electrically connected to the gate of the transistor.

For example, "the first transistor and the second transistor are operatively coupled" means that the voltage applied to the gate of the first transistor is directly or indirectly through a conductive medium such as a third transistor or a metal wire. It may mean that it is delivered to a specific terminal of, for example, a gate, a source region or a drain region. Alternatively, this may mean that a specific terminal of the first transistor and a specific terminal of the second transistor are electrically connected to each other.

As used herein, "semiconductor substrate" or "semiconductor layer" or "semiconductor pattern" or "substrate" refers to a structure based on any semiconductor. The semiconductor-based structure includes silicon, silicon-on-insulator (SOI) in which silicon is located on an insulating layer, silicon-on-sapphire (SOS) in which silicon is located on sapphire, silicon-germanium, Doped or undoped silicon, epitaxial layers formed by epitaxy growth techniques, and other semiconductor structures.

Although the present invention can be applied to all kinds of image sensors, the CMOS image sensor will be described in terms of only an example for a clearer understanding of the present invention. In addition, the unit pixel of the CMOS image sensor includes a photoelectric conversion element and at least one or more transistors. Among the CMOS image sensors having various types of unit pixels, in an exemplary aspect, the unit pixel adopts a photodiode as the photoelectric conversion element. Next, a CMOS image sensor employing a transfer transistor, a reset transistor, a source follower transistor, and a selection transistor to detect signal charges generated in the photoelectric conversion device will be described.

3 is a diagram schematically illustrating a unit pixel of an image sensor according to an exemplary embodiment. Referring to FIG. 3, the pixel 101 according to the present embodiment includes a photodiode 115 and a transfer transistor, a reset transistor, a source follower transistor, and a selection transistor operatively coupled thereto. According to an embodiment of the present invention, the constituent elements of the pixel are appropriately divided and disposed on the first and second semiconductor patterns 111 and 113 facing each other apart. For example, the photodiode 115 and the transfer transistor are formed in the second semiconductor pattern 113, and the reset transistor, the source follower transistor, and the selection transistor are formed in the first semiconductor pattern 111. The transfer gate 217 of the transfer transistor is disposed under the photodiode 115. Thus, the transfer transistor, reset transistor, source follower transistor, and select transistor do not affect the fill factor.

According to the present exemplary embodiment, the entire area of the second semiconductor pattern 113 may be used as a photodiode, thereby realizing a fill factor of 100%.

According to the present exemplary embodiment, since the first semiconductor pattern 111 on which the transistors are formed is independent of the fill factor, the first semiconductor pattern 111 may be formed to have substantially the same size as the second semiconductor pattern 113, thereby providing 1 / f noise characteristics. It can improve and an operation speed etc. can be improved. In addition, the size of the charge collecting regions 411_1 and 411_2 can be increased, thereby increasing the dynamic range.

The photodiode 115 may include a first conductive region (for example, an n-type region) 113n and a second conductive region 113n surrounding the first conductive region 113n formed in the second semiconductor pattern 113. For example, p-type region) 113p is included. According to the present exemplary embodiment, electron-hole pairs are formed as signal charges by photon incident on the second semiconductor pattern 113, and electrons are formed in the n-type region of the photodiode 115. Accumulates at 113n). The n-type region 113n is completely packed into the p-type region 113p to minimize the leakage of electrons.

The transfer gate 217 is disposed below the n-type region 113n with the gate insulating layer 317 interposed therebetween. When an appropriate bias voltage is applied to the transfer gate 217, charges (for example, electrons) accumulated in the n-type region 113n are transferred to the second charge collection region 411_2 serving as a floating diffusion region. The second charge collection region 411_2 is formed in the second semiconductor pattern 113 outside the transfer gate 217, for example, by being doped with n-type impurities. The transfer gate 217, the second charge collection region 411_1 and the n-type region 113n on both sides thereof may be regarded as constituting the transfer transistor.

The reset gate 211, the source follower gate 213, and the selection gate 215 are disposed on the first semiconductor pattern 111 with corresponding gate insulating layers 311, 313, and 315 interposed therebetween. Impurity diffusion regions serving as source / drain regions are positioned in the first semiconductor pattern on both sides of these gates. Each gate and its impurity diffusion regions constitute a transistor. For example, the reset gate 211 and its impurity diffusion regions 411_1 and 413 constitute a reset transistor, and the source follower gate 213 and its impurity diffusion regions 413 and 415 are sourced. The follower transistor is configured, and the select gate 215 and the impurity diffusion regions 415 and 417 on both sides constitute the select transistor. The impurity diffusion region 413 between the reset gate 211 and the source follower gate 213 is applied with a VDD voltage from a power supply.

The impurity diffusion region 411_1 of the reset transistor is electrically connected to the second charge collection region 411_2, and thus the impurity diffusion region 411_1 serves as a floating diffusion region like the second charge collection region 411_2. That is, similarly to the second charge collection region, charges transferred from the photodiode 115 also accumulate in the impurity diffusion region 411_1 of the reset transistor, and hereinafter, signal transfer is collected in the impurity diffusion region 411_1 of the reset transistor. In consideration of this, the impurity diffusion region 411_1 of the reset transistor is referred to as a first charge collection region. By applying an appropriate bias voltage to the reset gate 211, a channel is formed in the first semiconductor pattern under the reset gate 211, and the signal charges remaining in the first and second charge collection regions 411_1 and 411_2. Flows to the power source connected to the impurity diffusion region 413 of the reset transistor to initialize the pixel.

The source follower gate 213 of the source follower transistor is electrically connected to the first and second charge collection regions 411_1 and 411_2. The first charge collection region 411_1, the second charge collection region 411_2, and the source follower gate 213 are electrically connected to each other by the local conductive pattern 611 and the contact plugs 511, 513, and 711. Form a node. Accordingly, a signal voltage corresponding to the amount of signal charge collected in the first and second charge collection regions 411_1 and 411_2 appears in the impurity diffusion region 415 of the source follower transistor. By applying an appropriate bias voltage to the select gate 215 of the select transistor, the signal voltage is output to the output terminal of the select transistor, that is, the impurity diffusion region 417. The signal output to the output terminal 417 of the selection transistor is further processed in the peripheral circuit portion (not shown). Signal processing in the peripheral circuit portion will be described in more detail with reference to FIG. 6.

The first semiconductor pattern 111 on which the reset transistor, the source follower transistor, and the select transistor are formed may be, for example, a p-type silicon semiconductor substrate available in a conventional manner. Transistors formed on the first semiconductor pattern 111 may be formed by, for example, depositing a gate insulating layer and a conductive layer, and then performing a patterning process and an ion implantation process to form impurity diffusion regions. . As the conductive layer for the gate, but not limited thereto, polysilicon or multilayers of polysilicon and silicide may be used, for example. When the first semiconductor pattern 111 is p-type, n-type impurity ions are implanted to form a source / drain region of the transistor.

An interlayer insulating layer (not shown) is positioned between the first semiconductor pattern 111 and the second semiconductor pattern 113, which will be described in detail with reference to FIG. 5.

The transfer gate 217 may be formed by depositing a conductive layer on the interlayer insulating layer and then performing a patterning process. The patterning process may use a photolithography process. The gate insulating layer 317 surrounding the transfer gate 217 may be formed by, for example, using thin film deposition technology. The second semiconductor pattern 113 disposed on the second interlayer insulating layer so as to cover the transfer gate 217 and the gate insulating layer 317 is not limited thereto. For example, chemical vapor deposition, plasma chemical vapor deposition, or the like may be used. It can be formed by using a thin film deposition technique, or an epitaxy technique.

The photodiode 115 may be formed by performing an ion implantation process on the second semiconductor pattern 113. For example, after the second semiconductor pattern 113 doped with p-type is formed, an impurity ion implantation process for forming the n-type region 113n is performed and impurity ions for forming the p-type region 113p. The photodiode 113 may be formed by performing the injection process. According to the present embodiment, the vertical structure of the photodiode 113 exhibits a PNP so that no image lag occurs.

The second charge collection region 411_2 serving as the floating diffusion region may be formed by performing an ion implantation process on the second semiconductor pattern 113 using the transfer gate 217 as an ion implantation mask.

The order of the ion implantation process for the photodiode and the ion implantation process for the second charge collection region 411_2 may be changed as appropriate.

The contact plugs 511, 513, and 711 may be formed by patterning an interlayer insulating layer to form a contact hole and then forming a conductive material therein. The local conductive pattern 611 may be formed by depositing and patterning a conductive layer. In the manufacturing process, the contact plug 511 connected to the first charge collection region 411_1 and the contact plug 513 connected to the source follower gate 213 may be formed at the same time.

Although not shown, wirings for applying an appropriate bias voltage to the reset gate 211, the selection gate 215, and the transfer gate 217 are positioned between the first semiconductor pattern 111 and the second semiconductor pattern 113. do. When the local conductive pattern 611 is formed, these wirings can be formed at the same time.

When the contact plugs 511 and 513 connected to the first charge collection region 411_1 and the source follower gate 213 are formed, contact plugs (not shown) connected to the selection gate 215 may be simultaneously formed. Can be. In addition, when forming a contact plug 711 electrically connecting the local conductive pattern 611 and the second charge collection region 411_2, the wiring and the transfer gate 217 for applying a bias to the transfer gate 217. Contact plugs (not shown) for connecting the same may be formed at the same time.

The order of forming these contact plugs, wirings, and local conductive patterns can be variously changed. According to the present exemplary embodiment, wirings for applying bias to various gates may be formed under the photodiode, thereby ensuring sufficient margin for the arrangement of the wirings and varying the arrangement of the wirings.

According to this embodiment, a color filter can be arranged directly above the photodiode, thereby minimizing optical cross-talk and electrical cross-talk. In addition, since the photodiode and the color filter are disposed in close proximity or in contact with each other, a microlens for collecting light may not be used.

According to the present exemplary embodiment, the light shielding pattern may be formed under the photodiode without degrading the fill factor, thereby more effectively minimizing electrical interference.

According to this embodiment, the photodiode is formed in a state where most of the metal wirings are all formed. Therefore, no metal contact is formed on the photodiode, thereby minimizing dark levels.

4 is a plan view showing a portion of a pixel array according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view showing pixels when cut along the line II-II 'of FIG. 4.

Referring to FIG. 4, the first semiconductor pattern 111 in which the reset gate 211, the source follower gate 213, and the selection gate 215 are formed is positioned under the second semiconductor pattern 113 in which the photodiode is formed. The first semiconductor pattern 111 is completely covered by the second semiconductor pattern 113. Therefore, the size of the second semiconductor pattern 113 on which the photodiode is formed determines the size of the pixel, and the entire second semiconductor pattern 113 is used as the photodiode. In the drawing, the gate width (or the width of the active region) is correspondingly increased by increasing the first semiconductor pattern 111 in the y-axis direction, thereby improving the performance of the transistor. The first semiconductor pattern 111 may have the same size as the second semiconductor pattern 113 by increasing the width of the first semiconductor pattern 111. In addition, since the first semiconductor pattern 111 is positioned below the second semiconductor pattern 113 on which the photodiode is formed, the shape of the first semiconductor pattern 111 may be variously modified without reducing the fill factor. Do. For example, by variously modifying the shape of the first semiconductor pattern 111, it is possible to design the shape of the channel accordingly so that individual transistors have optimal performance.

In addition, since the transfer gate 127 is located under the photodiode, the gate length of the transfer gate can be variously designed, and the transfer gate can be appropriately designed so that the optimum transfer efficiency is shown.

The vertical cross-sectional structure of a pixel according to an embodiment of the present invention can be understood from FIG. 5. In FIG. 5, reference numerals 811 and 813 denote first and second interlayer insulating layers, reference numeral 911 denotes these first and second interlayer insulating layers, and reference numeral 1111 denotes a color filter. The interlayer insulating layers 811 and 813 are, for example, silicate glass (BPSG) doped with boron and phosphorus, silicate glass (BSG) doped with boron, silicate glass (PSG) doped with phosphorus, silicate not doped with impurities It may be formed of glass (USG), vapor deposition silicon oxide and the like. The color filter may be formed according to a conventional method.

Referring to FIG. 5, color filter 1111 is formed in close proximity or in contact with photodiode 115. In a typical image sensor as shown in Figs. 1 and 2, various wirings are formed on the photodiode, so that the color filter and the photodiode are far apart. In the conventional image sensor, a micro lens is used to increase the light collecting efficiency. In addition, in such a conventional image sensor, the distance between the color filter and the photodiode is large, and optical interference often occurs in which light passing through the color filter reaches adjacent pixels other than the intended pixel. However, according to the present invention, since the color filter and the photodiode are formed in close proximity or in contact with each other, substantially all of the light passing through the color filter is incident on the photodiode. In addition, according to the present invention, a photodiode is located directly under the color filter, so that a microlens may not be formed.

6 is a schematic block diagram of an image sensor 2080 including a pixel array in accordance with the present invention. Referring to FIG. 6, the pixel array 2000 includes a plurality of pixels arranged in a matrix in a predetermined manner. The pixel array 2000 includes a plurality of rows and columns. A specific row of the pixel array is selected by the row driver 2100 in response to the row decoder 2200, and a specific column of the pixel array is selected by the column driver 2600 in response to the column decoder 2700. The CMOS image sensor is controlled by the controller 2500, which controls the row decoder 2200, the row driver 2100, the column reader 2700, and the column driver 2600.

The output signal of the pixel includes a pixel reset signal Vrst and a pixel image signal Vsig. The pixel reset signal Vrst is a signal corresponding to the potential of the charge collection region when the pixel is reset, and the pixel image signal Vsig is the charge collection region in the state where the signal transfer generated by the image is transferred to the charge collection region. This signal corresponds to the potential of. The pixel reset signal Vrst and the pixel image signal Vsig are read by the sample / hold circuit 2610. The amplifier circuit 2620 generates a difference signal Vrst-Vsig between the reset signal Vrst and the image signal Vsig. This difference signal is converted into a digital signal by the analog-to-digital converter 2750. The image processor 2800 processes the digitized difference signal to generate a digital image. The image sensor 2080 may be included on a semiconductor chip (for example, the wafer 3000).

FIG. 7 is a block diagram schematically illustrating an exemplary processor based system 4000 including the image sensor of FIG. 6. Digital circuitry, which may include, for example, image sensor 4080, is a good example of a processor-based system. Processor-based systems include, but are not limited to, computer systems, camera systems, scanners, video phones, surveillance systems, machine vision systems, vehicle navigation systems, autofocus systems, star tracking System, motion detection system, image stabilization system, data compression system, and any system that can use the present invention.

System 4000 includes image sensor 4080 of FIG. 6. System 4000 includes a processor 4020 having a central processing unit (CPU) that communicates with various devices over a bus 4040. Some of the devices connected to the bus 4040 are for example input / output devices 4060, and image sensors 4080 provide input / output communication to / from the system 4000. Some of the devices connected to the bus 4040 include one or more peripheral memory devices such as, for example, RAM 4100, hard drive 4120, floppy disk drive 4140, compact disk drive 4160. Image sensor 4080 receives control signals or data from processor 4020 or other device in system 4000. The image sensor 3080 may provide the processor 402 with a signal that defines an image based on the received control signal or data, and the processor 402 processes the signal received from the image sensor 4080.

So far I looked at the embodiment (s) with respect to the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

According to the present invention, the entire area of the second semiconductor pattern 113 may be used as a photodiode, thereby realizing a fill factor of 100%.

According to the present invention, since the first semiconductor pattern 111 on which the transistors are formed is independent of the fill factor, the first semiconductor pattern 111 may be formed to have substantially the same size as the second semiconductor pattern 113, thereby improving 1 / f noise characteristics. It is possible to improve the operating speed and the like. In addition, the size of the charge collecting regions 411_1 and 411_2 can be increased, thereby increasing the dynamic range.

According to the present invention, the vertical structure of the photodiode 113 exhibits a PNP so that no image lag occurs.

According to the present invention, since the first semiconductor pattern 111 is positioned below the second semiconductor pattern 113 on which the photodiode is formed, the shape of the first semiconductor pattern 111 may be variously modified without reducing the fill factor. It is possible to let. For example, by variously modifying the shape of the first semiconductor pattern 111, it is possible to design the shape of the channel accordingly so that individual transistors have optimal performance.

According to the present invention, since the color filter and the photodiode are formed in close proximity or in contact with each other, substantially all of the light passing through the color filter is incident on the photodiode.

According to the present invention, the photodiode may be positioned directly under the color filter, thereby not forming a microlens.

According to the present invention, a light shielding pattern can be formed under the photodiode without lowering the fill factor, thereby more effectively minimizing electrical interference.

According to the present invention, a photodiode is formed in a state where most of the metal wirings are all made. Therefore, no metal contact is formed on the photodiode, thereby minimizing dark levels.

Claims (20)

A first semiconductor pattern and a second semiconductor pattern facing each other with an interlayer insulating layer therebetween; A photoelectric conversion element formed on the second semiconductor pattern; At least one transistor formed in the first semiconductor pattern and operatively coupled to the photoelectric conversion element to sense signal charge generated in the photoelectric conversion element; And A transfer gate formed in the second semiconductor pattern to transfer signal charges generated in the photoelectric conversion element to the at least one transistor, The photoelectric conversion element includes a first conductive region formed in the second semiconductor pattern and a region of the second conductive type formed in the second semiconductor pattern to surround the region of the first conductive pattern, And the first conductive region covers an upper region of the transfer gate. The image sensor of claim 1, wherein the region of the first conductivity type is an n-type region, the region of the second conductivity type is a p-type region, and the photoelectric conversion element is a photodiode. The method according to claim 1, And collecting first and second charge collection regions formed in the first semiconductor pattern and the second semiconductor pattern and electrically connected to each other to collect signal charges generated in the photoelectric conversion element. And the at least one transistor is operatively coupled to the first and second charge collection regions. The method of claim 3, The at least one transistor includes a first transistor for sensing signal charges of the first and second charge collection regions and a second transistor for resetting, Drains of the first and second transistors are connected to each other to form a common drain, A gate of the first transistor is electrically connected to the first and second charge collection regions, And the first charge collection region serves as a source region of the second transistor. The method of claim 4, The transfer gate transfers the signal charges generated by the photoelectric conversion element to the second charge collection region. The method of claim 3, The transfer gate transfers the signal charge generated in the photoelectric conversion element to the first and second charge collection regions. The method of claim 6, The photoelectric conversion element is a diode including an n-type region formed in the second semiconductor pattern and a p-type region formed on a surface of the second semiconductor pattern to surround the n-type region. And the second charge collection region is formed in the p-type region outside the transfer gate to be spaced apart from the n-type region. The method of claim 7, The at least one transistor includes a first transistor for operatively coupled to the first and second charge collection regions to sense signal charge and a second transistor for resetting, Drains of the first and second transistors are connected to each other to form a common drain, A gate of the first transistor is electrically connected to the second charge collection region, And the first charge collection region serves as a source region of the second transistor. The method according to any one of claims 1 to 8, And a color filter formed on the second semiconductor pattern. A first semiconductor pattern and a second semiconductor pattern facing each other with an interlayer insulating layer interposed therebetween; A photoelectric conversion element formed on the second semiconductor pattern; A transfer gate formed on the second semiconductor pattern and transferring signal charges generated in the photoelectric conversion element to a second charge collection region of the second semiconductor pattern; A first charge collection region formed in the first semiconductor pattern and electrically connected to the second charge collection region; A source follower gate electrically connected to the first and second charge collection regions and formed on the first semiconductor pattern; First and second drain regions formed on first semiconductor patterns on both sides of the source follower gate; And A reset gate formed on the first semiconductor pattern between the first drain region and the first charge collection region, The photoelectric conversion element includes a first conductive region formed in the second semiconductor pattern and a region of the second conductive type formed in the second semiconductor pattern to surround the region of the first conductive pattern, And the first conductive region covers an upper region of the transfer gate. The method of claim 10, The region of the first conductivity type is an n-type region, the region of the second conductivity type is a p-type region, and the photoelectric conversion element is a photodiode, And the second charge collection region is formed in the second semiconductor pattern outside the transfer gate away from the n-type region. The method according to claim 10 or 11, The interlayer insulating layer includes a first interlayer insulating layer and a second interlayer insulating layer, The electrical connection between the first charge collection region and the second charge collection region is: A first contact plug penetrating the first interlayer insulating layer and connected to the first charge collection region; A local conductive pattern formed on the first interlayer insulating layer and electrically connected to the first contact plug; And, And a second contact plug penetrating the second interlayer insulating layer to connect the second charge collection region and the local conductive pattern. The method according to claim 12, And the local conductive pattern is electrically connected to a third contact plug electrically connected to the source follower gate through the first interlayer insulating layer. The method of claim 10, And metal wires for applying a bias voltage to the transfer gate and the reset gate in the interlayer insulating layer. The method of claim 10, A second drain region formed in the first semiconductor pattern; And, And a selection gate formed on the first semiconductor pattern between the second drain region and the first source region. 16. The method of claim 15, And an metal wire for applying a bias voltage to the selection gate is located inside the interlayer insulating layer. The method of claim 10, And a color filter formed on the second semiconductor pattern. A photoelectric conversion element formed on the second semiconductor pattern; At least one transistor operatively coupled to the photoelectric conversion element and formed in the first semiconductor pattern away from the second semiconductor pattern; And A transfer gate formed in the second semiconductor pattern to transfer signal charges generated in the photoelectric conversion element to the at least one transistor, The photoelectric conversion element includes a first conductive region formed in the second semiconductor pattern and a region of the second conductive type formed in the second semiconductor pattern to surround the region of the first conductive pattern, And the first conductive region covers an upper region of the transfer gate. A processor; And, Including an image sensor coupled to the processor, The image sensor includes a plurality of pixels, Each of the pixels may include a photoelectric conversion element formed in a second semiconductor pattern, at least one transistor formed in a first semiconductor pattern operatively coupled to the photoelectric conversion element, and separated from the second semiconductor pattern, and signal charges generated in the photoelectric conversion element. A transfer gate formed in the second semiconductor pattern to transfer to the at least one transistor, The photoelectric conversion element includes a first conductive region formed in the second semiconductor pattern and a region of the second conductive type formed in the second semiconductor pattern to surround the region of the first conductive pattern, And the first conductive region covers an upper region of the transfer gate. The method of claim 19, The region of the first conductivity type is an n-type region, the region of the second conductivity type is a p-type region, and the photoelectric conversion element is a photodiode.

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