KR101147097B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of improving image quality by preventing horizontal streaks generated in a region corresponding to a liquid crystal injection hole.

A liquid crystal display device according to the present invention comprises a liquid crystal panel comprising a transistor and a color filter substrate bonded by an encapsulant to have an image display portion for displaying an image, and formed between one side of the image display portion and the encapsulant. A first gate driver circuit for supplying a gate pulse to the display unit, a second gate driver circuit formed between the other side of the image display unit and the sealant so as to be spaced apart from the sealant at a predetermined interval, and supplying a gate pulse to the image display unit; And a data driver for supplying an image signal to the image display unit.

By such a configuration, the present invention can prevent the horizontal streaks occurring in the liquid crystal injection hole region by reducing the width of the gate driving circuit formed adjacent to the liquid crystal injection hole so as not to overlap with the sealant. Accordingly, the present invention can prevent the horizontal stripe phenomenon, it is possible to improve the yield of the liquid crystal display device.

Sealant, Sealing Pattern, Gate Drive Circuit, Overlapping, Horizontal Stripes

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

1 is a schematic view of a liquid crystal display according to the related art.

FIG. 2 is a diagram illustrating the first and second gate driving circuits shown in FIG. 1. FIG.

3 is an enlarged view of a portion A shown in FIG. 1;

4 is a view showing horizontal stripes generated in a liquid crystal display according to the related art.

5 is a schematic view of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 6 is a view of the first and second gate driving circuits shown in FIG. 5; FIG.

FIG. 7 shows the first and second gate driving circuits and the sealant shown in FIG. 5; FIG.

8 is an enlarged view of a portion B shown in FIG. 7;

FIG. 9 is a waveform diagram illustrating an output signal of the second gate driving circuit illustrated in FIG. 5.

<Explanation of Signs of Major Parts of Drawings>

2, 102: color filter array substrate 4, 104: transistor array substrate

10, 110: liquid crystal panel 12, 112: image display unit

50, 150: first gate driver circuit 60, 160: second gate driver circuit

70, 170: sealing agent 80, 180: liquid crystal injection hole

82,182: sealing pattern 90: horizontal stripes

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving image quality by preventing horizontal streaks generated in a region corresponding to a liquid crystal injection hole.

Recently, various flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have emerged. Examples of such flat panel display devices include a liquid crystal display, a field emission display, a plasma display panel, and a light emitting display.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor (hereinafter, referred to as TFT) as a switching element. The gate terminal of the TFT is connected to any one of the gate lines.

The TFT used in such a liquid crystal display uses amorphous silicon or polysilicon as the semiconductor layer. The amorphous type liquid crystal display device has an advantage that the amorphous silicon layer has relatively uniformity and stable characteristics, but has a disadvantage in that it is difficult to improve the pixel density due to the low charge mobility. However, in recent years, through circuit complementary, it is possible to embed a driving circuit using amorphous silicon on an array substrate.

1 is a view schematically showing a liquid crystal display according to a related art.

Referring to FIG. 1, a liquid crystal display according to the related art includes a color filter array substrate 2 and a transistor array substrate bonded by a sealant 70 to have an image display unit 12 displaying an image. A liquid crystal panel 10 including 4) and a sealant 70 formed between the sealant 70 and one edge of the liquid crystal panel 10 so as to partially overlap the sealant 70 to supply a gate pulse to the image display unit 12. A second gate driving circuit 50 formed between the sealant 70 and the other edge of the liquid crystal panel 10 to partially overlap the sealant 70 and supplying a gate pulse to the image display unit 12. A gate driving circuit 60 and a plurality of data integrated circuits 40 for supplying an analog image signal to the image display unit 12 are provided.

In addition, the liquid crystal display according to the related art is a printed circuit in which a driving circuit including a timing controller 22 controlling the first and second gate driving circuits 50 and 60 and a plurality of data integrated circuits 40 is mounted. A plurality of Tape Carrier Packages (hereinafter referred to as TCP), in which a printed circuit board 20 and a data integrated circuit 40 are mounted and connected between the printed circuit board 20 and the liquid crystal panel 10. 34).

The liquid crystal panel 10 uniformly maintains a cell gap between the color filter array substrate 2 and the transistor array substrate 4 bonded to each other by the sealant 70 and the two array substrates 2 and 4 opposed to each other. And a liquid crystal filled in the liquid crystal space provided by the spacer.

A color filter, a common electrode, a black matrix, and the like, which are not shown, are formed in the display area of the color filter array substrate 2, that is, the image display unit 12. In this case, the common electrode may be formed on the transistor array substrate 4 or / and the color filter array substrate 2 according to the liquid crystal mode.

Signal lines such as a plurality of data lines DL and a plurality of gate lines GL are formed in the display area of the transistor array substrate 4, that is, the image display unit 12, and the data lines DL and the gate lines GL. A thin film transistor formed in the liquid crystal cell region defined by the intersection of the?) And a pixel electrode connected to each thin film transistor TFT.

Each liquid crystal cell may be equivalently represented by a liquid crystal capacitor Clc and includes a storage capacitor Cst for maintaining a data signal charged in the liquid crystal capacitor Clc until the next data signal is charged. The thin film transistor switches an image signal to be transmitted from the data line DL to the liquid crystal cell in response to a scan signal (gate pulse) from the gate line GL to the pixel electrode.

On the other hand, a data pad region connected to the data line DL is formed in the upper non-display area of the transistor array substrate 4. Further, first and second gate driving circuits 50 and 60 connected to the gate line GL are formed in the left and right non-display regions of the transistor array substrate 4.

The sealant 70 is formed along the edge of the color filter array substrate 2 or / and the transistor array substrate 4 except for the liquid crystal injection hole 80 to bond the two array substrates 2 and 4 through a bonding process. . In this case, the sealant 70 is formed to partially overlap the first and second gate driving circuits 50 and 60 formed on the left and right sides of the transistor array substrate 4.

The liquid crystal injection hole 80 is formed at one side of the two array substrates 2 and 4 bonded together so that the liquid crystal is injected during the liquid crystal injection process after the bonding process of the two array substrates 2 and 4. At this time, the liquid crystal injection hole 80 is formed with a plurality of sealing patterns 82 formed at regular intervals to serve as a dam (Dam) during the liquid crystal injection. The liquid crystal injection hole 80 including the plurality of sealing patterns 82 is sealed by an encapsulant during the encapsulation process after the liquid crystal injection process.

Each TCP 34 is electrically connected between the printed circuit board 20 and the liquid crystal panel 10 by a tape automated bonding (TAB) method. At this time, the input pads of each TCP 34 are electrically connected to the printed circuit board 20, and the output pads are electrically connected to the liquid crystal panel 10.

Each data integrated circuit 40 receives a control signal and a data signal from the timing controller mounted on the printed circuit board 20 through an input pad of the TCP 34, and converts the data signal into an analog signal using the input control signal. The image signal is converted into an image signal and supplied to the data line DL of the liquid crystal panel 10 through an output pad of the TCP 34.

The timing controller 22 arranges the source data supplied from the driving system according to the driving of the liquid crystal panel 10 according to the vertical, horizontal synchronizing signal and the data enable signal supplied from the external driving system so as to correspond to the driving of the liquid crystal panel 10. 40).

In addition, the timing controller 22 generates a data control signal for controlling the driving timing of each data integrated circuit 40 by using the vertical and horizontal synchronization signals and the data enable signal supplied from the driving system. It supplies to 40. In addition, the timing controller 22 uses the vertical and horizontal synchronizing signals and the data enable signal supplied from the driving system to control the driving timing of each of the first and second gate driving circuits 50 and 60. Is generated and supplied to each of the first and second gate driving circuits 50 and 60.

The first gate driving circuit 50 is directly formed between one end of the transistor array substrate 4 and the sealant 70 to sequentially supply gate pulses to the gate line GL.

To this end, the first gate driving circuit 50 includes a plurality of first stages 521 to 52n having an output terminal connected to one side of the gate lines GL as shown in FIG. 2.

Each of the plurality of first stages 521 to 52n is connected to the start pulse GSP input line and connected to the at least one clock signal CLK input line, respectively. At least one clock signal CLK is supplied in the form of a phase delay sequentially by one clock. In this case, when the number of clock signals CLK supplied to the clock signal CLK input line is two, the first gate driving circuit 50 is referred to as a two-phase shift register.

Accordingly, each of the plurality of first stages 521 to 52n shifts and outputs the start pulse GSP by one clock according to the two clock signals CLK1 and CLK3. At this time, the signals output from each of the first stages 521 to 52n of the first gate driving circuit 50 are supplied to the gate pulses GP and to the next stages 522 to 52n.

Meanwhile, each of the plurality of first stages 521 to 52n includes a plurality of transistors having the same channel width in order to shift the start pulse GSP by one clock according to the two clock signals CLK1 and CLK3. . Accordingly, the first gate driving circuit 50 is formed to have a predetermined width W and partially overlap with the sealant 70 due to the area of each of the plurality of transistors.

The second gate driving circuit 60 is directly formed between the other end of the transistor array substrate 4 and the sealant 70 to sequentially supply gate pulses to the gate line GL.

To this end, the second gate driving circuit 60 includes a plurality of second stages 621 to 62n having an output terminal connected to each other side of the gate lines GL as shown in FIG. 2.

Each of the plurality of second stages 621 to 62n is connected to a start pulse GSP input line and connected to at least one clock signal CLK input line. At least one clock signal CLK is supplied in the form of a phase delay sequentially by one clock. At this time, when the number of clock signals CLK supplied to the clock signal CLK input line is two, the second gate driving circuit 60 is referred to as a two-phase shift register.

Accordingly, each of the plurality of second stages 621 to 62n shifts and outputs the start pulse GSP by one clock according to the two clock signals CLK2 and CLK4. At this time, the signals output from the second stages 621 to 62n of the second gate driving circuit 60 are supplied to the gate pulses GP and to the next stages 622 to 62n.

Meanwhile, each of the plurality of second stages 621 to 62n has a plurality of transistors having the same channel width W in order to shift the start pulse GSP by one clock according to the two clock signals CLK1 and CLK3. It consists of. Accordingly, the second gate driving circuit 60 has a predetermined width W due to the area of each of the plurality of transistors, partially overlaps the sealant 70, and overlaps the liquid crystal injection hole 80.

In the liquid crystal display according to the related art, the gate pulses GP are sequentially applied to the gate lines GL using the first and second gate driving circuits 50 and 60 embedded in the liquid crystal panel 10. By supplying analog image signals from the plurality of data integrated circuits 40 to the data lines DL so as to be synchronized with the supply box, a desired image is displayed on the image display unit 12.

However, in the liquid crystal display according to the related art, the second gate driving circuit 60 is partially formed with the plurality of U-shaped sealing patterns 82 formed in the sealant 70 and the liquid crystal injection hole 80 as shown in FIG. 3. Overlaps. That is, some of the plurality of second stages 621 to 62n constituting the second gate driving circuit 60 partially overlap each U-shaped sealing pattern 82.

Accordingly, the liquid crystal display according to the related art corresponds to the liquid crystal injection hole 80 by an interaction between materials of the second stage transistors and the material of the sealing pattern 82 partially overlapping each of the U-shaped sealing patterns 82. As shown in FIG. 4, horizontal stripes 90 are generated on the liquid crystal panel 10 due to the difference in luminance between the region and the region that is not. Further, in the liquid crystal display according to the related art, horizontal streaks on the liquid crystal panel 10 may occur due to the difference in luminance between the overlapping area between the second gate driving circuit 60 and the sealing pattern 82 and the area 84 that is not. 90) occurs.

Specifically, in the liquid crystal display according to the related art, the uncured component of the encapsulant encapsulating the liquid crystal injection hole 80 is introduced toward the image display unit 12 as the driving time of the second gate driving circuit 60 passes. As the voltage drop between the electrodes is generated due to the residual of the DC component DC due to the impurity, the luminance difference between the region corresponding to the liquid crystal injection hole 80 and the region not being generated is generated.

In addition, in the liquid crystal display according to the related art, the dielectric constant is changed due to the overlap between the transistor of each stage of the second gate driving circuit 60 and the sealant 70, and thus, the second stage overlaps with the sealant 70. When the output voltage difference between the second stages is not generated, the luminance difference between the region corresponding to the liquid crystal injection hole 80 and the other region is not generated.

Accordingly, in order to solve the above problems, the present invention provides a liquid crystal display device which can improve image quality by preventing horizontal streaks generated in a region corresponding to the liquid crystal injection hole.

A liquid crystal display according to an embodiment of the present invention for achieving the above object is a liquid crystal panel including a transistor and a color filter substrate bonded by a sealant to have an image display unit for displaying an image, and the image display unit A first gate driving circuit formed between one side and the sealant to supply a gate pulse to the image display unit, and formed between the other side of the image display unit and the sealant so as to be spaced apart from the sealant by a predetermined distance, And a second gate driving circuit for supplying a gate pulse, and a data driver for supplying an image signal to the image display portion.

The width of the first gate driving circuit is different from that of the second gate driving circuit.

The width of the first gate driving circuit is wider than that of the second gate driving circuit.

The first gate driving circuit includes a plurality of first stages having a plurality of transistors for sequentially supplying a gate pulse to the image display unit according to at least two clock signals, and the second gate driving circuit includes at least two And a plurality of second stages having a plurality of transistors for sequentially supplying a gate pulse to the image display unit in accordance with the two clock signals.

The channel width of each transistor constituting the second stage is smaller than that of each transistor constituting the first stage.

One side of the first gate driving circuit is partially overlapped with the sealant.

The liquid crystal display may further include a liquid crystal injection hole for injecting liquid crystal into a space between the bonded transistor and the color filter substrate.

The second gate driving circuit is formed between the image display unit adjacent to the liquid crystal injection hole and the sealant.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

5 is a schematic view of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 6, a liquid crystal display according to an exemplary embodiment of the present invention includes a color filter array substrate 102 and a transistor bonded by a sealant 170 to have an image display unit 112 for displaying an image. A liquid crystal panel 110 including an array substrate 104, a first gate driving circuit 150 formed between the sealant 170 and the image display unit 112 to supply a gate pulse to the image display unit 112; The second gate driving circuit 160 is formed between the sealant 170 and the image display unit 112 so as to be spaced apart from the sealant 170 at a predetermined gap, and supplies a gate pulse to the image display unit 112. And a plurality of data integrated circuits 140 for supplying an analog image signal to the image display unit 112.

In addition, the liquid crystal display according to the exemplary embodiment of the present invention includes a driving circuit including a first and second gate driving circuits 150 and 160 and a timing controller 122 controlling the plurality of data integrated circuits 140. A plurality of tape carrier packages (Tape Carrier Package) mounted between the printed circuit board 120 and the data integrated circuit 140 and connected between the printed circuit board 120 and the liquid crystal panel 110. TCP 134).

The liquid crystal panel 110 uniformly maintains a cell gap between the color filter array substrate 102 and the transistor array substrate 104 bonded to each other by the sealant 170 and the two array substrates 102 and 104 opposed to each other. And a liquid crystal filled in the liquid crystal space provided by the spacer.

A color filter, a common electrode, a black matrix, and the like, which are not shown, are formed in the display area of the color filter array substrate 102, that is, the image display unit 112. In this case, the common electrode may be formed on the transistor array substrate 104 or / and the color filter array substrate 102 according to the liquid crystal mode.

In the display area of the transistor array substrate 104, that is, the image display unit 112, signal wirings such as a plurality of data lines DL and a plurality of gate lines GL are formed, and data lines DL and gate lines ( A thin film transistor formed in the liquid crystal cell region defined by the intersection of GL and a pixel electrode connected to each thin film transistor TFT.

Each liquid crystal cell may be equivalently represented by a liquid crystal capacitor Clc and includes a storage capacitor Cst for maintaining a data signal charged in the liquid crystal capacitor Clc until the next data signal is charged. The thin film transistor switches an image signal to be transmitted from the data line DL to the liquid crystal cell in response to a scan signal (gate pulse) from the gate line GL to the pixel electrode.

Meanwhile, a data pad region connected to the data line DL is formed in the upper non-display area of the transistor array substrate 104. In addition, first and second gate driving circuits 150 and 160 connected to the gate line GL are formed in the left and right non-display regions of the transistor array substrate 104.

The sealant 170 is formed along the edge of the color filter array substrate 102 or / and the transistor array substrate 104 except for the liquid crystal injection hole 180 to bond the two array substrates 102 and 104 through a bonding process. .

The liquid crystal injection hole 180 is formed at one side of the two array substrates 102 and 104 bonded together, and the liquid crystal is injected during the liquid crystal injection process after the bonding process of the two array substrates 102 and 104. In this case, a plurality of sealing patterns 182 formed at regular intervals are formed in the liquid crystal injection hole 180 to serve as a dam when the liquid crystal is injected. The liquid crystal injection hole 180 including the plurality of sealing patterns 182 is sealed by an encapsulant during the encapsulation process after the liquid crystal injection process.

Each TCP 134 is electrically connected between the printed circuit board 120 and the liquid crystal panel 110 by a tape automated bonding (TAB) method. In this case, input pads of each TCP 134 are electrically connected to the printed circuit board 120, and output pads are electrically connected to the liquid crystal panel 110.

Each data integrated circuit 140 receives a control signal and a data signal through an input pad of the TCP 134 from a timing controller mounted on the printed circuit board 120, and converts the data signal into an analog signal using the input control signal. The image signal is converted into an image signal and supplied to the data line DL of the liquid crystal panel 110 through an output pad of the TCP 134.

The timing controller 122 aligns the source data supplied from the driving system with the driving of the liquid crystal panel 110 according to the vertical, horizontal synchronizing signal and the data enable signal supplied from an external driving system so that each data integrated circuit ( 140).

In addition, the timing controller 122 generates a data control signal for controlling the driving timing of each data integrated circuit 140 by using the vertical and horizontal synchronization signals and the data enable signal supplied from the driving system. Supply to 140. In addition, the timing controller 122 controls the driving timing of each of the first and second gate driving circuits 150 and 160 using the vertical and horizontal synchronization signals and the data enable signal supplied from the driving system. Is generated and supplied to the first and second gate driving circuits 150 and 160, respectively.

Each of the first and second gate driving circuits 150 and 160 has the same functional parts except that the positions of the first and second gate driving circuits 150 and 160 are different.

The first gate driving circuit 150 is formed directly on the transistor array substrate 104 between one side of the image display unit 112 and the sealant 170 to sequentially supply gate pulses to the gate line GL.

To this end, the first gate driving circuit 150 includes a plurality of first stages 1521 to 152n having an output terminal connected to each side of the gate lines GL as shown in FIG. 6.

Each of the plurality of first stages 1521 to 152n is connected to the start pulse GSP input line and connected to the at least one clock signal CLK input line, respectively. At least one clock signal CLK is supplied in the form of a phase delay sequentially by one clock. At this time, when the number of clock signals CLK supplied to the clock signal CLK input line is two, the first gate driving circuit 150 is referred to as a two-phase shift register.

Accordingly, each of the plurality of first stages 1521 to 152n shifts and outputs the start pulse GSP by one clock according to the two clock signals CLK1 and CLK3. At this time, the signals output from the first stages 1521 to 152n of the first gate driving circuit 150 are supplied to the gate pulses GP and to the next stages 1522 to 152n.

Meanwhile, each of the plurality of first stages 1521 to 152n includes a plurality of transistors having the same first channel width to shift the start pulse GSP by one clock according to the two clock signals CLK1 and CLK3. It is composed. Accordingly, the first gate driving circuit 150 has a constant first width W1 due to the area of each of the first stages 1521 to 152n having the plurality of transistors and partially overlaps the sealant 170. It is formed between one side of the image display unit 112 and the sealant 170. In this way, even if the first gate driving circuit 150 and the sealant 170 partially overlap, the entire output of one side of the first gate driving circuit 150 overlaps the sealant 170 so that the output voltage does not occur.

The second gate driving circuit 160 is directly formed on the transistor array substrate 104 between the other side of the image display unit 112 and the sealant 170 to sequentially supply gate pulses to the gate line GL.

To this end, the second gate driving circuit 160 includes a plurality of second stages 1621 to 162n having an output terminal connected to each other side of the gate lines GL, as shown in FIG. 6.

Each of the plurality of second stages 1621 to 162n is connected to the start pulse GSP input line and connected to the at least one clock signal CLK input line, respectively. At least one clock signal CLK is supplied in the form of a phase delay sequentially by one clock. In this case, when the number of clock signals CLK supplied to the clock signal CLK input line is two, the second gate driving circuit 160 is referred to as a two-phase shift register.

Accordingly, each of the plurality of second stages 1621 to 162n shifts and outputs the start pulse GSP by one clock according to the two clock signals CLK2 and CLK4. At this time, the signals output from the second stages 1621 to 162n of the second gate driving circuit 160 are supplied to the next stages 1622 to 162n as well as the gate pulse GP.

Meanwhile, each of the plurality of second stages 1621 to 162n includes a plurality of transistors having the same second channel width to shift the start pulse GSP by one clock according to the two clock signals CLK1 and CLK3. It is composed. Accordingly, the second gate driving circuit 160 has a constant second width W2 due to the area of each of the second stages 1621 to 162n having a plurality of transistors, and has a predetermined distance from the sealant 170. Gap) is formed between the other side of the image display unit 112 and the sealant 170 to be spaced apart.

Here, as shown in FIG. 7, the second channel width is formed to be narrower than the first channel width within a space that does not overlap with the sealant 170 at a predetermined gap Gap. That is, the channel width of each transistor constituting each of the second stages 1621 to 162n is within a range of outputting the same gate pulse Gp as the gate pulse Gp output from the first stages 1521 to 152n. Is set to be narrower than the channel width of each transistor constituting each of the first stages 1521 to 152n. Accordingly, the second gate driving circuit 160 is formed between the other side of the image display unit 112 and the sealant 170 so as not to overlap the sealant 170, and as shown in FIGS. 7 and 8. The spacers are spaced apart from each other to have a predetermined gap so as not to overlap the sealing patterns 182 formed in the injection hole 180.

Accordingly, the gate pulse Gp supplied from the second stages 1621 to 162n to the gate line GL is transferred from the first stages 1521 to 152n to the gate line GL as shown in FIG. 9. It becomes equal to the gate pulse Gp supplied.

As described above, the liquid crystal display according to the exemplary embodiment of the present invention sequentially performs gate pulses on the gate lines GL by using the first and second gate driving circuits 150 and 160 embedded in the liquid crystal panel 110. By supplying analog image signals from the plurality of data integrated circuits 140 to the data lines DL so as to be synchronized with the supply of GP), a desired image is displayed on the image display unit 112.

Accordingly, in the liquid crystal display according to the exemplary embodiment, the channel widths of the plurality of transistors constituting the second stages 1621 to 162n such that the second gate driving circuit 160 and the sealant 170 do not overlap each other. To reduce the width W2 of the second gate driving circuit 160 to prevent horizontal streaks caused by the overlap between the second gate driving circuit 160, the sealant 170, and the sealing pattern 82. can do.

Meanwhile, in the liquid crystal display according to the exemplary embodiment, the width of the second gate driving circuit 160 formed to be adjacent to the liquid crystal injection hole 180 is reduced so as to be spaced apart from the sealant 170 and the sealing pattern 182. The first gate driving circuit 150 may also be formed to be spaced apart from the sealant 170.

On the other hand, the present invention described above is not limited to the above-described embodiments and the accompanying drawings, it is a technology that the various permutations, modifications and changes are possible within the scope without departing from the spirit of the present invention It will be apparent to those skilled in the art.

The liquid crystal display according to the exemplary embodiment of the present invention can prevent horizontal streaks occurring in the liquid crystal injection hole region by reducing the width of the gate driving circuit formed adjacent to the liquid crystal injection hole so as not to overlap with the sealant. Accordingly, the present invention can prevent the horizontal stripe phenomenon, it is possible to improve the yield of the liquid crystal display device.

Claims (8)

A transistor and a color filter substrate bonded by a sealant to have an image display portion for displaying an image, wherein the sealant is formed along edges of the transistor substrate and the color filter substrate except for a liquid crystal injection hole, and the liquid crystal injection hole The liquid crystal panel, characterized in that the sealing pattern which serves as a dam (dam) during the liquid crystal injection is formed at regular intervals, A first gate driving circuit formed between one side of the image display unit and the sealant to supply a gate pulse to the image display unit; A gap formed between the other side of the image display unit and the liquid crystal injection hole to supply a gate pulse to the image display unit so as to be spaced apart from the sealant and the sealing pattern by a predetermined interval so as not to overlap the sealing pattern of the sealant and the liquid crystal injection hole; A second gate driving circuit, wherein the second gate driving circuit is formed; And a data driver for supplying an image signal to the image display unit. The method of claim 1, The width of the first gate driving circuit is different from the second gate driving circuit. The method of claim 1, The width of the first gate driving circuit is wider than the second gate driving circuit. The method of claim 1, The first gate driving circuit includes a plurality of first stages having a plurality of transistors for sequentially supplying a gate pulse to the image display unit according to at least two clock signals, And the second gate driving circuit includes a plurality of second stages having a plurality of transistors for sequentially supplying a gate pulse to the image display part in accordance with at least two clock signals. The method of claim 4, wherein The channel width of each transistor constituting the second stage is narrower than that of each transistor constituting the first stage. The method of claim 1, One side of the first gate driving circuit partially overlaps the encapsulant. The method of claim 1, And the liquid crystal injection hole injects liquid crystal through a space between the bonded transistor and the color filter substrate. The method of claim 7, wherein And the second gate driving circuit is formed between the image display portion adjacent to the liquid crystal injection hole and the sealant.

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