KR101144523B1 - Semiconductor light emitting device and method for fabricating thereof - Google Patents

Abstract

The embodiment relates to a semiconductor light emitting device and a method of manufacturing the same.

In one embodiment, a semiconductor light emitting device includes: a first conductive semiconductor layer; An active layer disposed on the first conductive semiconductor layer and having a single or multiple quantum well structure in which a well layer and a barrier layer are alternately formed; And a second conductive semiconductor layer on the active layer, wherein the well layer includes a cluster having a density of at least 1E11 / cm ^{2 and} a high concentration of indium.

LED, active layer, thermal annealing

Description

Semiconductor light emitting device and method of manufacturing the same {SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THEREOF}

The embodiment relates to a semiconductor light emitting device and a method of manufacturing the same.

III-V nitride semiconductors include optical devices including blue / green light emitting diodes (LEDs), high-speed switching devices such as metal semiconductor field effect transistors (MOSFETs) and hetero junction field effect transistors (HEMTs), and light sources for lighting or display devices. It has been applied to a variety of applications. In particular, the light emitting device using the group III nitride semiconductor has a direct transition band gap corresponding to the region from visible light to ultraviolet light, and high efficiency light emission can be realized.

The nitride semiconductor is mainly used as a light emitting diode (LED) or a laser diode (LD), and research for improving a manufacturing process or light efficiency has been continued.

The embodiment provides a semiconductor light emitting device having a thickness of at least 3 nm of a well layer of an active layer, and a method of manufacturing the same.

The embodiment provides a semiconductor light emitting device and a method for manufacturing the same, which perform a thermal annealing process after the formation of the active layer to change the wavelength and the light intensity of the active layer.

The embodiment provides a semiconductor light emitting device and a method of manufacturing the same, wherein the thermal annealing is performed at or above the growth temperature of the active layer.

In one embodiment, a semiconductor light emitting device includes: a first conductive semiconductor layer; An active layer disposed on the first conductive semiconductor layer and having a single or multiple quantum well structure in which a well layer and a barrier layer are alternately formed; And a second conductive semiconductor layer on the active layer, wherein the well layer includes a cluster having a density of at least 1E11 / cm ^{2 and} a high concentration of indium.

A method of manufacturing a semiconductor light emitting device according to an embodiment includes: forming a first conductive semiconductor layer on a substrate; Forming an active layer on which the well layer and the barrier layer are alternately formed on the first conductive semiconductor layer; And forming at least one second conductive semiconductor layer on the active layer, wherein the well layer includes a cluster having a density of at least 1E11 / cm 2 and a high concentration of indium.

The embodiment can improve the intensity of the peak wavelength.

According to the embodiment, the wavelength at the time of growth of the active layer may be shifted to a long wavelength by a thermal annealing process.

Embodiments may improve ESD immunity.

In an embodiment, the operating voltage may be improved.

Hereinafter, in describing the embodiments, the criteria for the top or bottom of each layer may be described with reference to the drawings, and the thickness of each layer is described as an example and is not limited to the thickness of the drawings.

In an embodiment, each layer, region, pattern, or structure is described as being formed "on" or "under" a substrate, each layer (film), region, pad, or pattern. Where "on" and "under" include both "directly" and "indirectly".

Hereinafter, a semiconductor light emitting device according to an embodiment will be described with reference to the accompanying drawings.

1 is a side cross-sectional view of a semiconductor light emitting device according to a first embodiment.

Referring to FIG. 1, the semiconductor light emitting device 100 includes a substrate 101, a buffer layer 103, a first conductive semiconductor layer 105, an active layer 107, and a second conductive semiconductor layer 109. .

The substrate 101 may include a light transmissive substrate such as sapphire substrate (Al ₂ O ₃ ) or glass. In addition, the substrate 101 may be selected from the group consisting of GaN, SiC, ZnO, Si, GaP, and GaAs, Ga ₂ O ₃ , a growth substrate, an insulating substrate, a conductive substrate, and the like. In addition, an uneven pattern such as a lens shape or a stripe shape may be formed on the upper surface of the substrate 101. In this embodiment, it is not specifically limited as the board | substrate 101 by which a group III nitride semiconductor crystal is epitaxially grown on the surface, Various conductive materials, an insulating material, and a metallic material can be selected and used.

A compound semiconductor layer of Group 2 to Group 6 elements may be formed as a layer or a pattern on the substrate 101, and such a semiconductor layer may be formed of a structure or a material which may improve a difference in light extraction structure or lattice constant. Can be.

The growth equipment of the plurality of compound semiconductor layers may include an electron beam evaporator, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporator sputtering, It can be formed by metal organic chemical vapor deposition (MOCVD) and the like, but is not limited to such equipment.

For example, a buffer layer 103 using a group III-V compound semiconductor may be formed on the substrate 101, and an undoped semiconductor layer (not shown) may be formed on the buffer layer 103. The buffer layer 103 may be selected from Group III-V compound semiconductors, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and the like. This reduces the difference in lattice constant between compound semiconductors. The undoped semiconductor layer may be implemented as an undoped GaN-based semiconductor, but is not limited thereto. The buffer layer 103 and / or the undoped semiconductor layer may be omitted.

The light emitting structure is formed on the buffer layer 103. The light emitting structure may be formed of any one of an N-P junction, a P-N junction, an N-P-N junction, and a P-N-P junction using a Group III-V compound semiconductor layer. Here, the lower or upper semiconductor layer may vary depending on the N-P junction, P-N junction, N-P-N junction, and P-N-P junction.

The light emitting structure includes, for example, a first conductive semiconductor layer 105, an active layer 107, and a second conductive semiconductor layer 109.

The first conductive semiconductor layer 105 may be formed on the buffer layer 103. The first conductive semiconductor layer 105 is a compound semiconductor of Group III-V elements doped with a first conductive dopant, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and the like can be selected. When the first conductive semiconductor layer 105 is an N-type semiconductor layer, the first conductive dopant includes an N-type dopant such as Si, Ge, Sn, Se, Te, or the like. The first conductive semiconductor layer 105 may function as an electrode contact layer, and may be formed as a single layer or a multilayer, but is not limited thereto.

The active layer 107 may be formed in a single quantum well structure or a multiple quantum well structure. The active layer 107 may be formed using a compound semiconductor material of Group III-V elements, and a period of a well layer and a barrier layer, for example, In _x Al _y Ga _(1-xy) N well layer / In _a Al _b Ga _{( 1-ab)} can be formed with a period of N barrier layer (0 <x≤1, 0≤y≤1, 0≤x + y≤1, 0≤a≤1, 0≤b≤1, 0≤a + b≤1). The period of the well layer and the barrier layer may be formed of 1 to 20 cycles, but is not limited thereto.

In addition, an n-type dopant may be doped or not doped in the lower barrier layer of the active layer 107, and a dopant concentration different from a dopant concentration of another barrier layer may be formed in the top barrier layer. It may have, but is not limited to this.

The active layer growth method uses a carrier gas with nitrogen or / and hydrogen at a growth temperature of the first temperature T1 and selectively supplies NH ₃ , TMGa (or TFGa), and TMln, TMAl to provide a well layer and a barrier layer. Can grow in turn. The T1 may be set to 700 to 800 ° C., and the growth temperature of the well layer and the barrier layer may be the same, or the growth temperature of the barrier layer may be higher.

In this case, the growth rate of the well layer may be grown at a low rate of 0.01 nm / sec or less, and the thickness of the well layer may be thickened to 3 nm or more. The thickness of the well layer may be preferably formed in 3 ~ 4nm. The indium composition in the well layer may be grown to 12% or more, and a single or multiple barrier layer may be formed on the well layer. The active layer 107 is formed by growing the pair of well layers / barrier layers single or multiple.

The difference between the InGaN well layer and the GaN-based barrier layer is the composition of In, and the controlling factor can be controlled by the flow rate of In during thin film growth. That is, the higher the growth temperature, the lower the In composition, and even if the flow rate of In is lowered, the In composition decreases. Here, the barrier layer may be grown with a semiconductor material lower than the In composition of the well layer.

Also, when the well layer and the barrier layer are alternately grown, in a section in which the growth temperature of the well layer and the growth temperature of the barrier layer are changed or in a section in which the growth temperature of the barrier layer and the growth temperature of the well layer are changed. A stabilization time is given so that the temperature can stabilize. This stabilization time can be used to form an active layer of multi-quantum well structure.

A conductive clad layer may be formed on or under the active layer 107, and the conductive clad layer may be formed of an AlGaN-based semiconductor.

The second conductive semiconductor layer 109 is formed on the active layer 107. The second conductive semiconductor layer 109 may be a compound semiconductor of a Group III-5 element doped with a second conductive dopant, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP and the like can be selected. When the second conductive semiconductor layer 109 is a P-type semiconductor layer, the second conductive dopant includes a P-type dopant such as Mg, Be, or Zn. The second conductive semiconductor layer 109 may function as an electrode contact layer, and may be formed as a single layer or a multilayer, but is not limited thereto.

In the light emitting structure, the first conductive semiconductor layer 105 may be a P-type semiconductor, and the second conductive semiconductor layer 109 may be formed of an N-type semiconductor. A third conductive semiconductor layer (not shown), for example, an N-type semiconductor layer may be formed on the second conductive semiconductor layer 109, and the light emitting structure may include an NP junction, a PN junction, an NPN junction, and a PNP junction structure. It may include at least one. At least one layer of the compound semiconductor layer may be formed of a semiconductor material having a composition formula of In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). It does not limit to this.

In general, as shown in FIG. 2, the active layer 107 is present in the metastable region D1 when the indium composition X _{In in} the well layer is 10-20%. However, when most of the characteristics of the active layer 107 are grown to determine the growth of the well layer, there is almost no wavelength change in the optimization by the subsequent processing after the active layer is grown.

According to the embodiment, the growth rate of the well layer of the active layer 107 is 0.01 nm / sec or less, the thickness thereof is 3 nm or more, the indium composition of the well layer is 12% or more, and the barrier layer is grown after the stabilization time. The well layer and the barrier layer can be grown alternately.

After the growth of the active layer 107, a thermal annealing process is performed to improve the optical properties. The thermal annealing process may be optimized by a heat treatment process at a second temperature (T2> T1) by growth conditions of the well layer of the active layer 107. Here, T2 may be higher than the growth temperature of the well layer, or may be set to 800 ~ 1100 ℃ higher than the T1, this temperature may be changed according to the growth temperature of the active layer. According to the embodiment, the thermal annealing process is performed before the second conductive semiconductor layer 109 is grown while the active layer 107 is completely grown. The thermal annealing process may protect the well layer of the active layer 107 to suppress decomposition and evaporation, and may improve interface properties, optical properties, and uniformity of thickness.

On the other hand, since the one annealing process for improving the light efficiency proceeds at a temperature higher than the growth temperature of the well layer of the active layer 107, the quality of the well layer can be prevented from being lowered, and the indium rich, which is a high concentration of indium, can be prevented. In rich clusters or quantum dot formation may be induced. Here, the high concentration of indium lumps are agglomerates having a larger amount of indium than the indium composition in the well layer, and the size thereof has a diameter of 20 nm or less (eg, 1 to 20 nm). The high concentration of indium in the well layer is 1E11 / cm ² or more (e.g .: 1E11 / cm ² It can be formed with a density of ~ 1E13 / cm ² ).

The high concentration of indium lumps may have irregular shapes or random shapes, and may be formed at irregular intervals.

In addition, the heat annealing time is to perform a heat treatment for a longer time (eg 20 minutes) than the stabilization time of the active layer 107.

The light emitting device 100 may have improved brightness and resistance to electrostatic discharge (ESD), and may improve electrical characteristics such as an operating voltage. Therefore, it is possible to provide a semiconductor light emitting device having high brightness and high reliability. Here, the light emitting device 100 may promote light emission of energy lower than the band gap of the materials of the active layer by a thermal annealing process. Here, the well layer band gap of the active layer may have any one of a rectangular type, a pyramid type, and an trapezoidal type.

The emission wavelength of the active layer 107 may be longer than 1 nm, and the PL (photoluinescence) luminous intensity may be increased by 10% or more.

By performing the heat treatment process after the active layer 107, the level of brightness between the active layer 107 and the second conductive semiconductor layer 109 without P-AlGaN or / and P-AlGaN / GaN superlattice structure Can be implemented. In addition, the active layer which can be optimized for emission without providing a separate pattern (eg, PSS) on the substrate 101 can be provided.

As shown in FIG. 3, it can be seen that the active layer of the embodiment is shifted to a longer wavelength by about 2.3 nm than the comparative example by the well layer and the thermal annealing process disclosed above, and the intensity is substantially lower than that of the comparative example. It can be seen that more than 50% increase. Here, in the comparative example, the growth condition of the active layer is a case in which the well layer has a thickness of 2 nm and the In composition is about 10%.

According to the embodiment, the active layer 107 is optimized according to the growth conditions of the well layer and the post-treatment process after the growth of the active layer 107, thereby improving the brightness of the light emitting device, ESD resistance, operating voltage, and the like. The electrical characteristics are improved, and as a result, a light emitting device having high brightness / high reliability can be realized.

Table 1 is a view comparing the voltage, power and ESD characteristics of the comparative example and the embodiment.

[Table 1]

 Comparative example  Example  VF1 (20mA)  3.22 V 3.1 V  VF2 (1uA)  2.25V 2.35V  VR (-10uA)  -20V -25V  Po (20mA) Min: 11.9mW
Max: 12.9mW Min: 12.5mW
Max: 13.5mW  ESD yield (-2kV) 4% / 19% / 5% 80% / 64% / 45%

The active layer 107 can confirm the formation of a high concentration of indium lumps of 2Onm or less by a thermal annealing process. As a result, the emission wavelength of the active layer 107 becomes longer by 1 nm or more, and the PL intensity becomes stronger by 10% or more. The high concentration of indium in the well layer is 1E11 / cm ² or more (e.g .: 1E11 / cm ² 1 E13 / cm ² ).

4 is a side cross-sectional view illustrating a semiconductor light emitting device according to a second embodiment. In the description of the second embodiment, the same parts as in the first embodiment will be referred to the first embodiment, and redundant description thereof will be omitted.

Referring to FIG. 4, the stacked structure of the semiconductor light emitting device 100A includes a substrate 101, a buffer layer 103, a first conductive semiconductor layer 105, an active layer 107, and a second conductive buffer layer 108. And a second conductive semiconductor layer 109.

The second conductive buffer layer 108 is formed on the active layer 107, and the second conductive semiconductor layer 109 is formed on the second conductive buffer layer 108.

Here, the growth method of the active layer 107 is the same as in the first embodiment, the detailed description will be referred to the first embodiment. That is, the thickness of the well layer of the active layer 107 is formed at least 3nm, the well layer is In _x Al _y Ga _(1-xy) N (0 <x ≤ 1, 0 _{≤ y ≤} 1, 0 ≤ x + y ≦ 1), and the amount of In is formed at least 12%.

The second conductive buffer layer 108 may be formed in a thin film form of a Group III-V compound semiconductor doped with the second conductive dopant, for example, InAlGaN. The second conductive buffer layer 108 may be formed of InAlGaN or AlGaN, and may have a thickness of several tens of micrometers to several nm.

After the growth of the second conductive buffer layer 108, a thermal annealing process before the growth of the second conductive semiconductor layer 109 is performed. The thermal annealing process is performed for 20 minutes at a temperature range of 800 ~ 1100 ℃. The thermal annealing temperature may be performed at a temperature higher than a growth temperature of the active layer 107 or the second conductive buffer layer 108.

By the thermal annealing process, a quantum dot for increasing light efficiency may be increased in the well layer of the active layer. According to the embodiment, the active layer 107 is optimized according to the growth conditions of the well layer and the post-treatment process after the growth of the active layer 107, thereby improving the brightness of the light emitting device, ESD resistance, operating voltage, and the like. The electrical characteristics are improved, and as a result, a light emitting device having high brightness / high reliability can be realized.

The thermal annealing process may be performed after the active layer growth, after the growth of the second conductive buffer layer, and after the growth of the second conductive semiconductor layer, but is not limited thereto.

5 is a diagram illustrating a semiconductor light emitting device according to a third embodiment. In the description of the third embodiment, the same parts as in the first embodiment are referred to the first embodiment, and redundant description thereof will be omitted.

Referring to FIG. 5, in the manufacturing process of the semiconductor light emitting device 100B, a buffer layer 103, a first conductive semiconductor layer 105, an active layer 107, and a second conductive semiconductor layer may be formed on a substrate 101. 109 and the third conductive semiconductor layer 110 may be sequentially grown.

The growth method of the active layer 107 is referred to the first embodiment, and description thereof will be omitted. That is, the thickness of the well layer of the active layer 107 is formed at least 3nm, the well layer is In _x Al _y Ga _(1-xy) N (0 <x ≤ 1, 0 _{≤ y ≤} 1, 0 ≤ x + y ≦ 1), and the amount of In is formed at least 12%.

The second conductive semiconductor layer 109 is formed on the active layer 107, and the third conductive semiconductor layer 110 is formed on the second conductive semiconductor layer 109. The third conductive semiconductor layer 110 is a semiconductor layer doped with a first conductive dopant and is formed of a thin film. The third conductive semiconductor layer 110 may be selected from Group III-V compound semiconductors such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and the like.

After the growth of the second conductive semiconductor layer 109 or after the growth of the third conductive semiconductor layer 110, a thermal annealing process is performed. The thermal annealing process is performed for 20 minutes at a temperature range of 800 ~ 1100 ℃. The thermal annealing process induces formation of quantum dots (QDs), which are high concentrations of indium lumps, in the well layer of the active layer 107, and the quantum dots may cause an improvement in optical properties. The thermal annealing process may be performed at a temperature higher than the growth temperature of the well layer of the active layer 107 or higher than the growth temperature of the second conductive semiconductor layer 109.

The thermal annealing process is described as being performed after the growth of the third conductive semiconductor layer, but may be performed before the growth of the third conductive semiconductor layer or after the growth of the active layer.

At least one of a transparent electrode layer, a reflective electrode layer, and a second electrode may be formed on the second conductive semiconductor layer or the third conductive semiconductor layer according to the embodiment, and the forming material and its structure are within the technical scope of the embodiment. It can be changed in various ways. In addition, the above embodiments are not limited to the features of the embodiments, and may be selectively applied to the technical features of the other embodiments.

In addition, after the reflective electrode layer is disposed on the second conductive semiconductor layer, the substrate may be removed to form a first electrode electrically connected to the first conductive semiconductor layer. The semiconductor light emitting device may be provided in a vertical chip structure in which electrodes are disposed on opposite sides of the chip.

The present invention has been described above with reference to the embodiments, which are merely examples and are not intended to limit the embodiments of the present invention. Those skilled in the art to which the embodiments of the present invention pertain have the essential characteristics of the present invention. It will be appreciated that various modifications and applications not illustrated above are possible without departing from the scope of the invention. For example, each component shown in detail in the embodiment of the present invention may be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 is a diagram illustrating a semiconductor light emitting device according to a first embodiment.

2 is a view showing a state diagram according to the growth temperature and indium of the active layer.

3 is a view comparing PL luminosities of Examples and Comparative Examples.

4 is a diagram illustrating a semiconductor light emitting device according to a second embodiment.

5 is a diagram illustrating a semiconductor light emitting device according to a third embodiment.

Claims (22)

A first conductive semiconductor layer; An active layer disposed on the first conductive semiconductor layer and having a single or multiple quantum well structure in which a well layer and a barrier layer are alternately formed; A second conductive semiconductor layer on the active layer; And A second conductive buffer layer between the active layer and the second conductive semiconductor layer, The well layer has a composition formula of In _x Al _y Ga _(1-xy) N (0.1≤x≤0.2, 0≤y≤1, 0 <x + y≤1), The well layer includes a cluster having a density in the range of 1E11 / cm ² to 1E13 / cm ² and having an indium composition higher than that of the well layer. At least one of a transparent electrode layer, a reflective electrode layer, and a second electrode is formed on the second conductive semiconductor layer, And a first electrode electrically connected to the first conductive semiconductor layer. The semiconductor light emitting device of claim 1, wherein the thickness of the well layer is 3 to 4 nm and the indium composition of the well layer is in the range of 12 to 20%. The semiconductor light emitting device of claim 1, wherein the clusters of the well layers are formed in a size ranging from 1 nm to 20 nm. The semiconductor light emitting device of claim 1, wherein the cluster of the well layers has an irregular shape or a random shape. The semiconductor light emitting device of claim 1, wherein the clusters of the well layers have irregular intervals. The semiconductor light emitting device of claim 1, further comprising at least one of an undoped semiconductor layer, a buffer layer, and a substrate under the first conductive semiconductor layer. delete The semiconductor light emitting device of claim 1, wherein the second conductive buffer layer comprises InAlGaN or AlGaN. delete The semiconductor device of claim 1, wherein the first conductive semiconductor layer is an N-type semiconductor layer, The second conductive semiconductor layer includes a P-type semiconductor layer. The method of claim 2, wherein the active layer has a period of a well layer / In _a Al _b Ga _(1-ab) N barrier layer, and wherein 0 ≦ a ≦ 1, 0 ≦ b ≦ 1, and 0 ≦ a + b ≦ 1. Phosphorus semiconductor light emitting element. delete The semiconductor light emitting device of claim 1, wherein the well layer has a thickness in a range of about 3 nm to about 4 nm. Forming a first conductive semiconductor layer on the substrate; On the first conductive semiconductor layer, a well layer having a composition formula of In _x Al _y Ga _(1-xy) N (0.1≤x≤0.2, 0≤y≤1, 0 <x + y≤1) and the well Forming an active layer of a multi-quantum well structure having barrier layers alternately formed on the layer; Forming a second conductive buffer layer on the active layer; Forming at least one second conductive semiconductor layer on the second conductive buffer layer; And After forming the active layer, thermal annealing at a temperature higher than a growth temperature of the active layer, And forming a cluster having a density in the range of 1E11 / cm ² to 1E13 / cm ² and having an indium composition higher than that of an indium (In) of the well layer by the thermal annealing. The method of claim 14, wherein the thermal annealing is performed before forming the second conductive semiconductor layer. The method of claim 14, wherein the thermal annealing is performed after the formation of the second conductive buffer layer. The method of claim 14, wherein the period between the well layer and the barrier layer of the active layer is 2-20 cycles. The method of claim 14, wherein the active layer has a period of a well layer / In _a Al _b Ga _(1-ab) N barrier layer, wherein 0 ≦ a ≦ 1, 0 ≦ b ≦ 1, and 0 ≦ a + b ≦ 1. Phosphorus semiconductor light emitting device manufacturing method. The method of claim 14, wherein the second conductive semiconductor layer comprises a P-type dopant. The method of claim 18, wherein an indium composition of the well layer is in a range of 12 to 20%. delete The method of claim 18, wherein the thickness of the well layer is 3 to 4 nm.

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