KR101137770B1 - 3-dimensional nonvolatile memory device, method of fabricating the same and memory chip - Google Patents

Abstract

A nonvolatile memory device having a three-dimensional structure, a manufacturing method thereof, and a memory chip are provided. According to the nonvolatile memory device, at least one NAND string is removed on the substrate. The at least one NAND string includes at least one semiconductor pillar extending upwardly onto the substrate and a plurality of memory cells connected in series along the at least one semiconductor pillar. The at least one semiconductor pillar includes at least one lateral extension in each NAND string.

Description

3-dimensional nonvolatile memory device, method of fabricating the same and memory chip}

The present invention relates to a semiconductor device, and more particularly, to a nonvolatile memory device having a three-dimensional structure and a memory chip using the same.

Electronic products are getting smaller and bulkier and require higher data throughput. Accordingly, there is a need to increase the degree of integration while reducing the volume of memory chips used in such electronic products. In this regard, a non-volatile memory device having a three-dimensional structure that vertically stacks memory cells on a substrate instead of a conventional planar structure is considered for such a highly integrated memory chip. In such a three-dimensional structure, the capacity of the nonvolatile memory device may be increased on the same plane by increasing the number of stacked memory cells.

However, as the number of stacked memory cells increases in a nonvolatile memory device having a three-dimensional structure, an aspect ratio increases, making the manufacturing process difficult. Accordingly, the reliability of the nonvolatile memory device having a three-dimensional structure is deteriorated.

Accordingly, the present invention is provided to solve the above-described problem, and provides a nonvolatile memory device and a method of manufacturing the same which can increase the reliability of a manufacturing process in a three-dimensional structure. In addition, the present invention provides a memory chip using a nonvolatile memory device having such a three-dimensional structure.

However, the above technical problem is provided by way of example, and the technical problem to be achieved by the present invention is not limited to the above-described example.

A nonvolatile memory device having a three-dimensional structure of one embodiment of the present invention is provided. A substrate is provided, and at least one NAND string is provided on the substrate. The at least one NAND string includes at least one semiconductor pillar extending upwardly onto the substrate and a plurality of memory cells connected in series along the at least one semiconductor pillar. The at least one semiconductor pillar includes at least one lateral extension in each NAND string.

According to an aspect of the nonvolatile memory device, a cross-sectional area parallel to the substrate of the at least one lateral extension may be greater than that of the remaining portion of the at least one semiconductor pillar.

According to another aspect of the nonvolatile memory device, the plurality of memory cells in each of the NAND strings include: a plurality of control gate electrodes stacked in a plurality of layers on the substrate and surrounding the at least one semiconductor pillar; And at least one charge storage layer between the at least one semiconductor pillar and the control gate electrodes.

According to another aspect of the nonvolatile memory device, at least one bit line connected to an end of the at least one NAND string may be further provided. Furthermore, the at least one NAND string may further include a string select transistor between the plurality of memory cells and the at least one bit line.

A method for manufacturing a nonvolatile memory device having a three-dimensional structure of one embodiment of the present invention is provided. A plurality of first conductive layers are laminated on the substrate. At least one first semiconductor pillar extending through the plurality of first conductive layers is formed. Forming at least one first lateral extension connected to an end of the at least one first semiconductor pillar on the plurality of first conductive layers. Laminating a plurality of second conductive layers on the at least one first lateral extension. At least one second semiconductor pillar connected to the at least one first lateral extension is formed through the plurality of second conductive layers.

According to an aspect of the manufacturing method, before forming the at least one first semiconductor pillar, at least one first through hole penetrating the plurality of first conductive layers is formed, and the at least one first through hole is formed. At least one first charge storage layer may be formed on the inner surface of the hole. Further, the at least one first semiconductor pillar may be formed on the at least one first charge storage layer in the at least one first through hole.

According to another aspect of the fabrication method, at least one agent exposing the at least one first lateral extension layer through the plurality of second conductive layers prior to forming the at least one second semiconductor pillar. The second through hole may be formed, and at least one second charge storage layer may be formed on an inner surface of the at least one second through hole. Further, the at least one second semiconductor pillar may be formed to be connected to the at least one first lateral extension layer on the at least one second charge storage layer in the at least one second through hole.

According to another aspect of the manufacturing method, the at least one first semiconductor pillar may be formed in a single crystal structure from the surface of the substrate by using a selective epitaxial growth method. Further, the at least one first lateral extension may be formed in a single crystal structure from the surface of the at least one first semiconductor pillar by using the selective epitaxial growth method. Wherein the at least one first semiconductor pillar is formed using a selective epitaxial growth method under a vertical stretching condition, and the at least one first lateral extension is formed using a selective epitaxial growth method under a side growth condition, 3 A method of manufacturing a nonvolatile memory device having a dimensional structure.

According to another aspect of the manufacturing method, forming at least one second lateral extension connected to an end of the at least one second semiconductor pillar on the plurality of second conductive layers, the at least one second Stacking a plurality of third conductive layers on the lateral extension, and further forming at least one third semiconductor pillar connected to the at least one second lateral extension through the plurality of third conductive layers have.

A memory chip of one embodiment of the present invention is provided. The memory cell array includes a nonvolatile memory device having the above-described three-dimensional structure. The row decoder is coupled to the word lines of the memory cell array. The column decoder is coupled to the bit lines of the memory cell array. Control logic is coupled to the row decoder and the column decoder.

According to the non-volatile memory device having a three-dimensional structure and a method of manufacturing the same according to embodiments of the present invention, when forming the aspect ratio of the through-hole at the time of forming each divided portion by dividing the semiconductor pillars Compared to this, it can be lowered significantly. This facilitates the manufacturing process of the through-hole and the semiconductor pillar filling the same. Further, by arranging the lateral extensions between the divided semiconductor pillars, the alignment margin between the divided semiconductor pillars can be increased. Accordingly, the reliability of the nonvolatile memory device can be improved.

In addition, using the manufacturing method according to the embodiments of the present invention, it is possible to increase the length of the semiconductor pillar of the vertical structure, thereby increasing the number of stacked control gate electrodes. As a result, the number of memory cells stacked in each NAND string is increased, so that the capacity of the nonvolatile memory device can be increased.

1 is a schematic perspective view showing a nonvolatile memory device according to an embodiment of the present invention;
2 is a cross-sectional view taken along the line II-II 'of FIG. 1;
3 is a cross-sectional view illustrating a nonvolatile memory device according to another embodiment of the present invention;
4 is an equivalent circuit diagram of a portion of non-volatile memory elements in accordance with embodiments of the present invention;
5 to 11 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention; And
12 is a schematic block diagram illustrating a memory chip according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. In the drawings, the size of components may be exaggerated for convenience of explanation.

1 is a schematic perspective view illustrating a nonvolatile memory device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II-II 'of FIG. 1.

1 and 2, a memory cell array having a vertical structure may be provided on a substrate 105. The substrate 105 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, the group IV semiconductor may comprise silicon, germanium or silicon-germanium. Substrate 105 may be provided as a bulk wafer or an epitaxial layer. For example, impurities may be doped into a portion of such a bulk wafer or epitaxial layer, and such doped regions may be used as a common source line (see CSL in FIG. 4).

The semiconductor pillars 130 may be disposed to extend upward on the substrate 105. For example, the semiconductor pillars 130 may extend perpendicular to the substrate 105. The semiconductor pillars 130 may have a cylindrical or polygonal pillar shape. The semiconductor pillar 130 may include a semiconductor material, for example, a group IV semiconductor material such as silicon, germanium, or silicon-germanium. The number of semiconductor pillars 130 may be appropriately selected depending on the capacity of the nonvolatile memory device, and does not limit the scope of this embodiment.

For example, each semiconductor pillar 130 may include first and second semiconductor pillars 130a and 130b and at least one lateral extension portion 135 of a vertical structure. The lateral extension 135 may be disposed between the first and second semiconductor pillars 130a and 130b. For example, the first semiconductor pillar 130a is disposed vertically on the substrate 105, the lateral extension 135 is disposed on the first semiconductor pillar 130a, and the second semiconductor pillar 130b. May be disposed vertically on the substrate 105 over the lateral extensions 135.

The lateral extension 135 may have a larger cross-sectional area than the first and second semiconductor pillars 130a and 130b based on a cross section parallel to the substrate 105. For example, the lateral extension 135 may substantially extend over the top surface of the first semiconductor pillar 130a and further extend laterally. The lower end of the second semiconductor pillar 130b may be in contact with the lateral extension 135 as a whole or at least a portion thereof.

The lateral extension 135 may be formed of the same semiconductor material as the first and second semiconductor pillars 130a and 130b or may be formed of different semiconductor materials. For example, the first and second semiconductor pillars 130a and 130b and the lateral extension 135 may be formed of the same semiconductor material having a substantially single crystal structure. However, in a modified example of this embodiment, some or all of the first and second semiconductor pillars 130a and 130b and the lateral extensions 135 may be formed of a semiconductor material having a polycrystalline structure. The semiconductor pillars 130 and the lateral extensions 135 may be doped with impurities.

Upper ends of the semiconductor pillars 130 may be connected to the bit lines 155 and BL. For example, when the semiconductor pillars 130 are arranged in a matrix, the semiconductor pillars 130 arranged in the same column may be connected to the same bit line 155. This arrangement can reduce the number of bit lines 155, thereby simplifying the structure of the nonvolatile memory device.

The control gate electrodes 140 may be stacked in a plurality of layers on the substrate 105 while surrounding the semiconductor pillars 130. An interlayer insulating layer 110 may be interposed between the control gate electrodes 140. The number of control gate electrodes 140 above and below the lateral extension 135 may or may not be the same. In FIG. 1, four control gate electrodes 140 are disposed below the lateral extension 135 and four control gate electrodes 140 are disposed on the lateral extension 135. Is shown. This stacking number of control gate electrodes 140 may be appropriately selected depending on the capacity of the nonvolatile memory device, and does not limit the scope of this embodiment.

The control gate electrodes 140 may be connected to the word lines 160 and WL through the via plugs 150. For example, the control gate electrodes 140 may be arranged in a line pattern in each plane, and the control gate electrodes 140 of the same layer may be connected to the same word line electrode 160. In order to arrange the via plugs 150, the control gate electrodes 140 may be disposed in a step-shaped narrower shape as the control gate electrodes 140 move away from the substrate 105.

The word lines 160 may extend perpendicular to the control gate electrodes 140 and parallel to the bit lines 155. In a modified example of this embodiment, the control gate electrodes 140 may be provided in a flat plate type, in which case one word line 160 may be connected to each flat plate, respectively.

The first and second charge storage layers 125a and 125b may be disposed between at least the control gate electrodes 140 and the semiconductor pillar 130. For example, the first charge storage layer 125a is provided between the first semiconductor pillar 130a and the control gate electrodes 140 under the lateral extension 135 and the second charge storage layer 125b. May be provided between the second semiconductor pillar 130b and the control gate electrodes 140 over the lateral extension 135. Optionally, a portion of the first charge storage layer 125a may further extend onto the control gate electrode 140 directly below the lateral extension 135.

The first and second charge storage layers 125a and 125b are data storage layers of memory cells (see T _MC of FIG. 4) having a stacked structure between the semiconductor pillar 130 and the control gate electrodes 140. It can be used as. For example, the first and second charge storage layers 125a and 125b may have a stacked structure of tunneling insulation layer / charge trap layer / blocking insulation layer between the semiconductor pillar 130 and the control gate electrodes 140 (not shown). May include). The charge trap layer has a charge storage capability, the tunneling insulating layer is used as a tunneling passage of the charge, and the blocking insulating layer may serve to suppress reverse tunneling of the charge.

For example, the charge trap layer may be a silicon nitride layer or may include an insulating layer including quantum dots or nano-particles. Quantum dots or nanoparticles can be composed of fine particles of a conductor, such as a metal or a semiconductor. The tunneling insulating layers and the blocking insulating layer may include any suitable insulating film, such as an oxide film, a nitride film or a high dielectric constant film. The high dielectric constant film may refer to a dielectric film having a higher dielectric constant than the oxide film and the nitride film.

The string select lines 145 may be disposed to surround the semiconductor pillar 130 between the bit lines 155 and the top control gate electrode 140. The second charge storage layer 125b may be further extended between the string selection lines 145 and the second semiconductor pillar 130b to serve as a gate insulating layer. In a modified example of this embodiment, a single gate insulating layer (not shown) may be interposed between the string select lines 145 and the second semiconductor pillar 130b instead of the second charge storage layer 125b.

The string select lines 145 may extend perpendicular to the bit lines 155 and may be provided in a line pattern. Accordingly, the semiconductor pillars 130 arranged in the same row may be surrounded by the same string selection line 145, respectively. Meanwhile, source / drain regions may be formed in portions of the semiconductor pillars 130 on both sides of the string select lines 145.

The stacked structure between the semiconductor pillar 130 and the string select lines 145 may constitute string select transistors (T _SS of FIG. 4). In this embodiment, the string select lines 145 may serve as gate electrodes of the string select transistors (T _SS of FIG. 4). In a modified example of this embodiment, string select gate electrodes may be provided to surround the semiconductor pillar 130, and string select lines may additionally be provided to be connected to the gate electrodes.

3 is a cross-sectional view illustrating a nonvolatile memory device according to another exemplary embodiment of the present invention. The nonvolatile memory device according to this embodiment may refer to the nonvolatile memory device of FIGS. 1 and 2, and thus, redundant descriptions of the two embodiments are omitted.

Referring to FIG. 3, a ground select line 147 may be further disposed between the substrate 105 and the lowermost control gate electrode 140. The ground select line 147 may be disposed on the substrate 105 to surround the semiconductor pillar 130. The first charge storage layer 125a may be further extended between the ground select line 147 and the first semiconductor pillar 130a to serve as a gate insulating layer.

In a modified example of this embodiment, a single gate insulating layer (not shown) may be interposed between the ground select lines 147 and the first semiconductor pillar 130a instead of the second charge storage layer 125b. For example, the ground select line 147 may extend perpendicular to the bit lines 155 and may be provided in a line pattern. As another example, the ground select line 147 may be provided in the form of a plate.

The stacked structure between the semiconductor pillar 130 and the ground select line 147 may constitute a ground select transistor (T _GS of FIG. 4). In this embodiment, the ground select line 147 may serve as the gate electrode of the ground select transistor (T _GS of FIG. 4). In a modified example of this embodiment, a ground select gate electrode may be provided to surround the semiconductor pillar 130 and a ground select line may additionally be provided to be connected to the ground select gate electrode.

The first lateral extension 135a may be provided on the first semiconductor pillar 130a, and the second lateral extension 135b may be provided on the second semiconductor pillar 130b. For example, the first lateral extension 135a is provided to cover the top surface of the first semiconductor pillar 130a and the second lateral extension 135b covers the top surface of the second semiconductor pillar 130b. Can be provided.

The third semiconductor pillar 130c may be provided on the second lateral extension 135b. The cross-sectional area in the direction parallel to the substrate 105 of the first and second lateral extensions 135a and 135b is parallel to the substrate 105 of the first to third semiconductor pillars 130a, 130b and 130c. It may be larger than the cross-sectional area of. The bit lines 155 may be connected to an upper surface of the semiconductor pillar 130, that is, an upper surface of the third semiconductor pillar 130c.

The control gate electrodes 140 may be provided to surround the first to third semiconductor pillars 130a, 130b, and 130c. The first to third charge storage layers 125a, 125b and 125c may be disposed between the first to third semiconductor pillars 130a, 130b and 130c and the control gate electrodes 140, respectively. Optionally, the first charge storage layer 125a may further extend onto the control gate electrode 140 directly below the first lateral extension 135a and the second charge storage layer 125b may have a second side. It may further extend onto the control gate electrode 140 directly below the directional extension 135b.

The number of control gate electrodes 140 between the first and second lateral extensions 135a and 135b may be appropriately selected. In FIG. 3, two control gate electrodes 140 are disposed below the first lateral extension 135a and three controls between the first and second lateral extensions 135a and 135b. The structure in which the gate electrodes 140 are disposed and the three control gate electrodes 140 are disposed on the second lateral extension 135b is illustrated.

In another embodiment of the present invention, the lateral extensions are provided in one or a plurality, and the control gate electrodes can be grouped into a plurality of groups by the lateral extensions. For example, the control gate electrodes of each group may be two to six, but this embodiment is not limited thereto. Grouping the control gate electrodes into a plurality of groups may increase manufacturing reliability of a memory cell array having a vertical stacked structure, as described below.

4 is an equivalent circuit diagram of a portion of non-volatile memory devices according to embodiments of the present invention. In this schematic, the number of bit lines and NAND strings is shown by way of example.

Referring to FIG. 4, the memory cell array having a vertical structure may include NAND strings NS1 and NS2 arranged in a vertical structure on a substrate 105 of FIGS. 1 to 3. Each of the NAND strings NS1 and NS2 may include a plurality of memory cells T _MC connected vertically in series on the substrate 105. One end of the NAND strings NS1 and NS2 is connected to the bit line BL, and the other end is connected to the common source line CSL.

String select transistors T _SS are disposed between the bit line BL and the memory cells T _MC , and ground select transistors T _GS are disposed between the common source line CSL and the memory cells T _MC . ) May be arranged. Optionally, in the case of the nonvolatile memory devices of FIGS. 1 and 2, the ground select transistors T _GS may be omitted.

The word lines WL01 to WLn may be arranged in multiple layers, and may be covalently coupled to the memory cells T _MC of the corresponding layer. Word lines WL01 to WLn may be appropriately selected and do not limit the scope of this embodiment. Word lines (WL01 ~ WLn) by controlling the memory cells (see 140 of FIG. 1 to FIG. 3), the control gate electrodes of the (T _MC), the program, erase and read operations of the memory cells (T _MC) Can be controlled. For example, a program operation may be performed by selecting one of the word lines WL01 to WLn to apply a program voltage, and may also read a program state by applying a read voltage.

The ground select line GSL may be covalently coupled to the ground select transistor T _GS . In the nonvolatile memory device of FIGS. 1 and 2, the ground select line GSL may be omitted. Since the ground select line GSL is covalently coupled to the NAND strings NS1 and NS2, a signal of the common source line CSL, for example, a ground voltage, may be simultaneously applied to the NAND strings NS1 and NS2. . The turn-on voltage for turning on the ground select transistors T _GS is applied to the ground select line GSL during the program and read operations of the memory cells T _MC , and the ground during the program protection operation. A turn-off voltage may be applied to turn off the selection transistors T _GS .

The string select lines SSL1 and SSL2 may be respectively coupled to the string select transistors T _SS . In order to separate signals of the NAND strings NS1 and NS2 sharing the bit line BL, the string select lines SSL1 and SSL2 may be respectively coupled to the string select transistors T _SS . However, when the NAND strings NS1 and NS2 are arranged in an array as in the case of FIG. 1, the string select lines SSL1 and SSL2 are covalently coupled to the string select transistors T _SS disposed in the same row. Can be.

For example, to select the NAND string NS1, a turn-on voltage for applying the string select transistors T _SS to the string select line SSL1 is applied and a turn for turning off the string select line SSL2 to the string select line SSL2. An off voltage can be applied. Accordingly, the signal of the bit line BL may be selectively applied to the memory cells T _MC in the NAND string NS1. Similarly, to select the NAND string NS2, the turn-on voltage for turning on the string select transistors T _SS is applied to the string select line SSL2 and the string select transistors are applied to the string select line SSL1. A turn-off voltage for turning off T _SS ) may be applied. Accordingly, the signal of the bit line BL may be selectively applied to the memory cells T _MC in the NAND string NS2.

5 through 11 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

Referring to FIG. 5, first conductive layers 115a may be stacked on a substrate 105. For example, by repeating the steps of forming the first insulating layer 110a on the substrate 105 and forming the first conductive layer 115a on the first insulating layer 110a, the first insulating layer ( A repeating laminated structure of 110a) / first conductive layer 115a can be formed.

For example, the first insulating layer 110a may form any insulator, such as an oxide, by an appropriate deposition method. The first conductive layer 115a may be formed by an appropriate deposition method such as polysilicon. For example, the first conductive layer 115a may be formed of a polysilicon layer by chemical vapor deposition (CVD), and may be formed by doping impurities with the deposition.

Subsequently, first through holes 120a penetrating through the first insulating layers 110a and the first conductive layers 115a may be formed. The number of first through holes 120a may be appropriately selected and does not limit the scope of this embodiment. For example, a photoresist mask (not shown) is formed using a photolithography technique, and the first through holes are formed by etching the first insulating layer 110a and the first conductive layers 115a using the mask as a protective film. 120a may be formed.

Referring to FIG. 6, first charge storage layers 125a may be formed on sidewalls of the first through holes 120a. Furthermore, the first charge storage layers 125a may be further extended onto the uppermost first conductive layer 115a. For example, a laminated structure of a tunneling insulating layer / charge trap layer / blocking insulating layer is formed on the resultant product on which the first through holes 120a are formed, and the laminated structure portion on the bottom surface of the first through holes 120a is etched. First charge storage layers 125a may be formed.

Optionally, the uppermost layer of the stacked structure of the first insulating layers 110a and the first conductive layers 115a may be the first insulating layer 110a, in which case the first charge storage layers 125a may be The deposition and dry etching techniques may be used to form spacers in the first through holes 120a and may not extend over the first insulating layer 110a and the first conductive layer 115a.

Subsequently, the first semiconductor pillars 130a may be formed on the first charge storage layers 125a in the first through holes 120a. The first semiconductor pillars 130a may be formed to fill the first through holes 120a. In a modified example of this embodiment, the thickness of the first semiconductor pillars 130a may be adjusted so as not to completely fill the first through holes 120a. The first semiconductor pillars 130a may be used as channel layers of memory cells (T _MC of FIG. 4).

For example, a columnar semiconductor layer may be formed on the substrate 105 by using a selective epitaxial growth (SEG) method, and planarized to form the first semiconductor pillars 130a. have. In this case, when the substrate 105 is a single crystal, the first semiconductor pillars 130a may have a single crystal structure. Further, when forming the first semiconductor pillars 130a, the SEG condition may be a vertical growth condition based on the substrate 105. For example, the semiconductor layer may comprise silicon, germanium or silicon-germanium.

As another example, an amorphous semiconductor layer may be formed in the first through holes 120a, and the first semiconductor pillars 130a may be formed by planarization and heat treatment. In this case, the semiconductor layer of the amorphous structure may be recrystallized into a substantially single crystal structure in the heat treatment step because the width of the first through holes 120a is small. As another example, the first semiconductor pillars 130a may be formed as a polycrystalline structure by forming a semiconductor layer having a polycrystalline structure in the first through holes 120a and planarizing the semiconductor layer.

Referring to FIG. 7, the lateral extension layer 135 may be formed on the first semiconductor pillars 130a. For example, the lateral extension layer 135 may be formed in a single crystal structure from the first semiconductor pillars 130a using a selective epitaxial growth (SEG) method. When forming the lateral extension layer 135, the SEG condition may be a lateral growth condition in which the horizontal direction is preferentially grown based on the substrate 105, unlike when the first semiconductor pillar 130a is formed. In this case, by adjusting the SEG time, the lateral extension layer 135 may be formed using only the SEG method without an additional patterning process. However, in a modified example of this embodiment, a patterning process may be added after SEG growth.

As another example, the lateral extension layer 135 may be formed through a patterning and heat treatment process after deposition of a semiconductor layer having an amorphous structure. Since the lateral extension layer 135 is not large in size, the semiconductor layer having an amorphous structure may be recrystallized into a single crystal structure by heat treatment. The patterning process may use photolithography and etching techniques. As another example, the lateral extension layer 135 may be formed into a polycrystalline structure by forming a polycrystalline semiconductor layer, and planarizing and patterning the polycrystalline semiconductor layer.

Referring to FIG. 8, a stacked structure of the second insulating layers 110b and the second conductive layers 115b may be formed on the resultant on which the lateral extension layer 135 is formed. For a description of the stacking structure, reference may be made to the stacking structure of the first insulating layers 110a and the first conductive layers 115a of FIG. 5.

Referring to FIG. 9, second through holes 120b may be formed through the second insulating layers 110b and the second conductive layers 115b. The second through holes 120b may expose a portion or the entire top surface of the lateral extension layer 135. Like the first through holes 120a of FIG. 5, the second through holes 120b may be formed using photolithography and etching techniques.

In the photolithography step, the second through holes 120b may be formed to align with the lateral extension layers 135. Since the lateral extension layers 135 have a larger cross-sectional area than the first semiconductor pillars 130a, the alignment of the second through holes 120b with the lateral extension layers 135 may be performed by the first semiconductor pillars ( More advantageous than aligning to 130a). Accordingly, by arranging the lateral extension layers 135, the alignment margin of the second through holes 120b may be improved.

Referring to FIG. 10, the second charge storage layers 125b and the second semiconductor pillars 130b may be sequentially formed in the second through holes 120b. The method of forming the second charge storage layers 125b and the second semiconductor pillars 130b may refer to the description of the first charge storage layer 125a and the first semiconductor pillars 130a of FIG. 6.

Referring to FIG. 11, the control gate electrodes 140 and the string select lines 145 may be formed by patterning the first and second conductive layers 115a and 115b. The control gate electrodes 140 may be patterned stepwise. Thereafter, the insulating layer 110 may be filled to form a third insulating layer (not shown), via holes (not shown) may be formed therethrough, and the via plugs 150 may be formed in the via holes.

Subsequently, bit lines 155 may be formed on the semiconductor pillars 130, and word lines 160 may be formed on the via plugs 150. The bit lines 155 and the word lines 160 may be disposed on the same plane or on different planes.

According to the manufacturing method according to this embodiment, the semiconductor pillar 130 may be formed by dividing the first semiconductor pillar 130a, the lateral extension layer 135, and the second semiconductor pillar 130b without forming them at once. . When the semiconductor pillars 130 are formed at one time, the aspect ratio of the through holes increases, making it difficult to form the through holes, and it becomes difficult to fill the semiconductor material in the through holes. This difficulty limits the height of the semiconductor pillar 130, which limits the number of memory cells T _MC in the vertical NAND strings NS1 and NS2 of FIG. 4.

However, by dividing the semiconductor pillar 130 into the first semiconductor pillar 130a and the second semiconductor pillar 130b, the aspect ratio of the first through hole 120a and the second through hole 120b can be greatly reduced. Can be. Accordingly, not only the formation of the first and second through holes 120a and 120b, but also the formation of the first and second semiconductor pillars 130a and 130b filling the same may be facilitated.

In addition, by arranging the lateral extension 135 between the first semiconductor pillar 130a and the second semiconductor pillar 130b, the first semiconductor pillar 130a is increased by increasing the alignment margin when the second through holes 120b are formed. ) And the connection reliability of the second semiconductor pillar 130b can be improved. In this regard, the number of lateral extensions 135 may be appropriately selected in view of the aspect ratios of the first and second through holes 120a and 120b. For example, a plurality of lateral extensions 135 may be provided between two to six control gate electrodes 140.

Accordingly, using the manufacturing method according to this embodiment, it is possible to increase the length of the semiconductor pillar 130 of the vertical structure, thereby increasing the number of stacking of the control gate electrodes 140. As a result, the number of memory cells stacked in each NAND string is increased, so that the capacity of the nonvolatile memory device can be increased.

With reference to the manufacturing method described above, the nonvolatile memory device of FIG. 3 may also be manufactured. For example, the nonvolatile memory device of FIG. 3 may be manufactured by repeating the steps of FIGS. 8 to 10 and then proceeding to the steps of FIG. 11 on the resultant of FIG. 10.

Furthermore, by repeating the steps of FIGS. 8 to 10 as many times as appropriate, a nonvolatile memory device having four or more lateral extensions can also be manufactured.

12 is a schematic block diagram illustrating a memory chip 300 according to an embodiment of the present invention.

Referring to FIG. 12, the memory cell array 310 may include at least one of the above-described nonvolatile memory devices having a three-dimensional structure. The memory cell array 310 may be combined with the X-buffer / row decoder 320 and the Y-buffer / column decoder 330. For example, word lines WL of the memory cell array 310 may be connected to the X-buffer / row decoder 320. The bit lines BL of the memory cell array 310 may be connected to the Y-buffer / column decoder 330. Control logic 340 may be coupled to and control X-buffer / row decoder 320 and Y-buffer / column decoder 330.

For example, in the process of transferring an address signal, the control logic 340 transmits a row address signal to the X-buffer / row decoder 320, and the X-buffer / row decoder 320 decodes these signals. The row address signal may be transferred to the memory cell array 310. In addition, the control logic 340 transmits the column address signal to the Y-buffer / column decoder 330, and the Y-buffer / column decoder 330 decodes the signal and passes through the memory cells through the bit lines BL. The column address signal may be transferred to the array 310.

The foregoing description of specific embodiments of the invention has been presented for purposes of illustration and description. Therefore, the present invention is not limited to the above embodiments, and various modifications and changes can be made by those skilled in the art within the technical spirit of the present invention in combination with the above embodiments. Do.

Claims (18)

Board; And
At least one NAND string on said substrate,
The at least one NAND string includes at least one semiconductor pillar extending upwardly onto the substrate and a plurality of memory cells connected in series along the at least one semiconductor pillar;
The at least one semiconductor pillar includes at least one lateral extension in each NAND string,
The plurality of memory cells in each NAND string,
A plurality of control gate electrodes stacked in a plurality of layers on the substrate and surrounding the at least one semiconductor pillar; And
And at least one charge storage layer between the at least one semiconductor pillar and the control gate electrodes. The nonvolatile memory device of claim 1, wherein the at least one semiconductor pillar extends perpendicular to the substrate. The non-volatile memory device of claim 1, wherein a cross-sectional area parallel to the substrate of the at least one lateral extension is greater than a cross-sectional area of the remaining portion of the at least one semiconductor pillar. The nonvolatile memory device of claim 1, wherein the at least one lateral extension is disposed between three to six of the plurality of memory cells in each NAND string. delete The method of claim 1, further comprising at least one bit line connected to an end of the at least one NAND string.
The at least one NAND string further comprises a string select transistor between the plurality of memory cells and the at least one bit line. Stacking a plurality of first conductive layers on a substrate;
Forming at least one first semiconductor pillar extending through the plurality of first conductive layers;
Forming at least one first lateral extension connected to an end of the at least one first semiconductor pillar on the plurality of first conductive layers;
Stacking a plurality of second conductive layers on the at least one first lateral extension; And
Forming at least one second semiconductor pillar connected to the at least one first lateral extension through the plurality of second conductive layers. 8. The method of claim 7, further comprising: forming at least one first through hole through the plurality of first conductive layers before forming the at least one first semiconductor pillar; And
Forming at least one first charge storage layer on an inner surface of the at least one first through hole,
And forming the at least one first semiconductor pillar on the at least one first charge storage layer in the at least one first through hole. The at least one second through hole of claim 8, wherein the at least one second lateral extension layer is exposed through the plurality of second conductive layers before forming the at least one second semiconductor pillar. Forming a; And
Forming at least one second charge storage layer on an inner surface of the at least one second through hole,
Wherein the at least one second semiconductor pillar is formed to be connected to the at least one first lateral extension layer on the at least one second charge storage layer in the at least one second through hole. Method of manufacturing volatile memory device. The method of claim 7, wherein the at least one first semiconductor pillar is formed from a surface of the substrate in a single crystal structure by using a selective epitaxial growth method. . The three-dimensional structure of claim 10, wherein the at least one first lateral extension is formed from a surface of the at least one first semiconductor pillar in a single crystal structure by using a selective epitaxial growth method. A method of manufacturing a nonvolatile memory device. 12. The method of claim 11, wherein the at least one first semiconductor pillar is formed using a selective epitaxial growth method under a vertical stretching condition, and the at least one first lateral extension uses a selective epitaxial growth method under a side growth condition. A method of manufacturing a nonvolatile memory device having a three-dimensional structure, which is formed by using the same. The method of claim 10, wherein the at least one first lateral extension is formed by depositing, patterning, and heat treating an amorphous semiconductor layer on the first semiconductor pillar. . The method of claim 7, wherein the at least one first semiconductor pillar is formed by depositing, patterning, and heat treating a semiconductor layer having an amorphous structure on a surface of the substrate. The method of claim 7, wherein the plurality of first conductive layers and the plurality of second conductive layers are patterned to form a plurality of control gate electrodes and string select gate electrodes stacked in a plurality of layers on the substrate. A method of manufacturing a nonvolatile memory device having a three-dimensional structure, further comprising the step. The method of claim 7, further comprising forming a bit line on the at least one second semiconductor pillar. 8. The method of claim 7, further comprising: forming at least one second lateral extension connected to an end of the at least one second semiconductor pillar on the second conductive layers;
Stacking a plurality of third conductive layers on the at least one second lateral extension; And
And forming at least one third semiconductor pillar connected to said at least one second lateral extension through said plurality of third conductive layers. A memory cell array comprising a non-volatile memory device having a three-dimensional structure according to any one of claims 1 to 4;
A row decoder coupled to word lines of the memory cell array;
A column decoder coupled to the bit lines of the memory cell array; And
And control logic coupled to the row decoder and the column decoder.

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