KR101132887B1 - Method of forming dual damascene pattern in semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a dual damascene pattern of a semiconductor device, and has an effect of preventing via poison and volcano from occurring in the dual damascene process.

 The dual damascene pattern forming method of the semiconductor device according to the present invention comprises the steps of depositing a diffusion barrier film, a first interlayer insulating film, a first hard mask film, a second interlayer insulating film and a second hard mask film on the semiconductor substrate in sequence; Forming a first photoresist pattern for forming a via hole exposing a portion of the second hard mask layer on the second hard mask layer; Etching the second hard mask layer, the second interlayer dielectric layer, the first hard mask layer, and the first interlayer dielectric layer using the first photoresist pattern as an etch mask to form a via hole; Removing the first photoresist pattern; Performing UV curing and hard baking on the semiconductor substrate from which the first photoresist pattern is removed; Forming a protective film filling the via hole; Forming a second photoresist pattern on the second hard mask layer, the second photoresist pattern forming a trench wider than the via hole with respect to the via hole; Forming a trench by etching the second hard mask layer and the second interlayer insulating layer using the second photoresist pattern as an etching mask; Removing the second photoresist pattern and the passivation layer; Performing a UV curing and hard baking process on the semiconductor substrate from which the second photoresist pattern is removed; And etching the diffusion barrier portion exposed by the via hole.

Amine, Via Poison, UV Curing, Hard Baking

Description

Method of forming dual damascene pattern in semiconductor device

1 is a photograph showing a state in which via hole poisoning occurs in a dual damascene pattern forming process according to the related art.

2A to 2J are cross-sectional views illustrating processes for forming a dual damascene pattern of a semiconductor device according to an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

100: semiconductor substrate 101: diffusion barrier film

102: first interlayer insulating film 103: first hard mask film

104: second interlayer insulating film 105: second hard mask film

106: first photosensitive film pattern 107: via hole

108: protective film 109: second photosensitive film pattern

110: trench 200: vacuum chamber

210: hot plate 220: UV lamp

220a: UV 230: lamp housing

The present invention relates to a method for forming a dual damascene pattern of a semiconductor device, and more particularly, to a method for forming a dual damascene pattern of a semiconductor device capable of preventing via poison and volcano phenomena generated in a dual damascene process.

As semiconductor devices have been highly integrated, research has been actively conducted on wiring technology that enables free and easy wiring design and allows setting of wiring resistance and current capacity.

In particular, in recent years, a metal wiring is formed using copper (Cu) having low resistance, and an insulating film is formed using a low k material, and a trench for forming via holes and metal wiring is formed in the insulating film. After the formation of the trench, a dual damascene process was formed in which a dual damascene pattern composed of the via hole and the trench was filled with Cu to form metal wiring.

Here, there are various methods of forming the dual damascene pattern, but in general, a via first trench last (VFTL) process is widely used. In the VFTL process, after depositing an interlayer insulating film using a low dielectric constant material such as FSG, OSG, SiO ₂ and the like and a hard mask film using SiN and SiC, the amine or amine like present in the interlayer insulating film ) The baking process is performed at a temperature of about 200 ° C. for degassing of the gas, and then a gas such as N _{2 is} flowed into the furnace, and the temperature is heated to about 400 ° C. to cure. While the amine or amine-based gases present in the interlayer insulating film are degassed to some extent during this process, when these gases are not completely degassed, via poisoning phenomenon as shown in FIG. 1 occurs, and in severe cases Volcano phenomenon may occur. The via poison and volcano phenomena cause problems such as deterioration of the reliability of the metal wiring.

In order to solve this via poisoning phenomenon, that is, to prevent out gassing of the amine or amine-based gas, a method of using a low dielectric constant containing no nitrogen (N) has been proposed. In this case, since the effective k value is somewhat higher, the metal wiring process to minimize the influence on the RC delay has no choice but to use a certain amount of N.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide a method of forming a dual damascene pattern of a semiconductor device capable of preventing via poison and volcano in a device to minimize RC delay. It is.

Dual damascene pattern forming method of a semiconductor device according to the present invention for achieving the above object,

Depositing a diffusion barrier film, a first interlayer insulating film, a first hard mask film, a second interlayer insulating film, and a second hard mask film on a semiconductor substrate in sequence;

Forming a first photoresist pattern for forming a via hole exposing a portion of the second hard mask layer on the second hard mask layer;

Etching the second hard mask layer, the second interlayer dielectric layer, the first hard mask layer, and the first interlayer dielectric layer using the first photoresist pattern as an etch mask to form a via hole;

Removing the first photoresist pattern;

Performing UV curing and hard baking on the semiconductor substrate from which the first photoresist pattern is removed;
Forming a protective film filling the via hole;

Forming a second photoresist pattern on the second hard mask layer, the second photoresist pattern forming a trench wider than the via hole with respect to the via hole;

Forming a trench by etching the second hard mask layer and the second interlayer insulating layer using the second photoresist pattern as an etching mask;

Removing the second photoresist pattern and the passivation layer;

Performing a UV curing and hard baking process on the semiconductor substrate from which the second photoresist pattern is removed; And

Etching the diffusion barrier portion exposed by the via hole.

The method may further include forming a protective film to fill the via hole before forming the second photoresist pattern.

The protective film may be a photosensitive film or a lower anti-reflection film.

The method may further include performing UV curing and hard baking after each deposition process of the first interlayer insulating film, the first hard mask film, the second interlayer insulating film, and the second hard mask film.

In addition, after the etching process of the diffusion barrier, characterized in that it further comprises the step of performing a UV curing and hard baking treatment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout.

2A through 2J are cross-sectional views illustrating processes for forming a dual damascene pattern of a semiconductor device according to an exemplary embodiment of the present invention.

As shown in FIG. 2A, a semiconductor substrate 100 having a predetermined substructure (not shown) is provided, and a diffusion barrier layer 101 and a first interlayer insulating film 100 are formed on the semiconductor substrate 100. 102, the first hard mask film 103, the second interlayer insulating film 104, and the second hard mask film 105 are sequentially deposited. The diffusion barrier film 101 and the first and second hard mask films 103 and 105 are preferably deposited using SiN or SiC. In addition, the first and second interlayer insulating films 102 and 104 may be deposited using a low dielectric constant material, such as a fluoro siicate glass (FSG) series. In this case, generally, the low dielectric constant material uses N ₂ O as an oxidant, and the low dielectric constant material of the FSG series contains NF ₂ therein.

Next, as shown in FIG. 2B, a first photosensitive film pattern 106 for forming a via hole exposing a portion of the second hard mask film 105 is formed on the second hard mask film 105. .

Next, as shown in FIG. 2C, the second hard mask film 105, the second interlayer insulating film 104, and the first hard mask film (using the first photoresist film pattern 106 as an etching mask) are used. 103 and the first interlayer insulating film 102 are etched to form via holes 107.

Thereafter, as shown in FIG. 2D, the first photoresist pattern 106 is removed. The removal process of the first photoresist layer pattern 106 may be performed using dilute O ₂ to minimize damage to the interlayer insulating layers 102 and 104 and the hard mask layers 103 and 105. Do.

Subsequently, as shown in FIG. 2E, the resultant obtained therefrom is simultaneously subjected to UV curing and hard baking. That is, the resultant of the substrate 100 on which the first photoresist pattern 106 is removed is placed on a hot plate 210 provided in the vacuum chamber 200, and the hard baking process is performed at a temperature of about 300 ° C. or less. At the same time, the resultant is cured using the UV 220a irradiated from the UV lamp 220 disposed on the resultant of the substrate 100.

In this case, as the UV curing and the hard baking process are simultaneously performed, degassing of amine-based gas such as N ₂ O or NF ₂ contained in the first and second interlayer insulating films 102 and 104 is performed. Treatment and surface hardening treatment can be made. That is, while the UV curing process is performed, UV (220a) of about 254 nm is irradiated to the substrate 100 to thereby produce the first and second interlayer insulating films 102 and 104 and the first and second hard films. The amine or the amine-based gas, etc. existing in the mask films 103 and 105 are removed, and the hard baking treatment that heats the lower surface of the substrate 100 further deepens the surface, and also hardens the surface. There is.

Here, in order to further enhance the effects as described above, the UV curing and hard baking treatment may be performed on the first interlayer insulating film 101, the first hard mask film 102, the second interlayer insulating film 103, and the second hard mask. It is desirable to perform additionally after each deposition process of films 104. Meanwhile, reference numeral 230 not described in FIG. 2E denotes a lamp housing. Then, while performing the UV curing and hard baking treatment as described above, as shown in the figure, a gas such as N _{2 is} flowed into the chamber.

Next, as shown in FIG. 2F, a protective film 108 filling the via hole 107 is formed. It is preferable to use a photosensitive film, a bottom anti-reflection coating, or the like as the protective film 108.

Next, as illustrated in FIG. 2G, a second photoresist pattern 109 for forming a trench wider than the via hole 107 is formed on the second hard mask film 105, centering on the via hole 107. do.

Next, as shown in FIG. 2H, the second hard mask layer 105 and the second interlayer dielectric layer 104 are etched using the second photoresist layer pattern 109 as an etching mask to form the trench 110. Form. Then, the second photosensitive film pattern 109 is removed. The removal process of the second photoresist pattern 109 is preferably performed using dilute O ₂ , similarly to the removal process of the first photoresist pattern 106.

Thereafter, as shown in FIG. 2I, the UV curing and the hard baking treatment as described above are simultaneously performed on the resultant of the substrate 100 on which the second photoresist pattern 109 is removed. Degassing treatment and surface hardening treatment.

Next, as shown in FIG. 2J, a portion of the diffusion barrier film 101 exposed by the via hole 107 is etched. Subsequently, although not shown in the drawings, in order to more fully perform the degassing treatment and the surface hardening treatment as described above, the UV curing and the hard baking treatment may be additionally performed.

Accordingly, the present invention can prevent via poisoning and volcano phenomena that occur when amines or amine-based gases present in an interlayer insulating film and the like are not completely degassed, which is, of course, degassing from the conventional process. It is much more advantageous from the side.

The present invention is not limited to the above-described embodiments, but can be variously modified and changed by those skilled in the art, which should be regarded as included in the spirit and scope of the present invention as defined in the appended claims. something to do.

As described above, according to the method for forming a dual damascene pattern of a semiconductor device according to the present invention, UV curing and hard baking are simultaneously performed in a vacuum chamber to completely remove amine or amine-based gases present in an interlayer insulating film. Can be gassed Therefore, the present invention can prevent via poison and volcano phenomena in the device to minimize the RC delay. In addition, the present invention is much advantageous in terms of degassing as well as process time, compared to the existing process, there is an effect that can improve the yield.

Claims (5)

Depositing a diffusion barrier film, a first interlayer insulating film, a first hard mask film, a second interlayer insulating film, and a second hard mask film on a semiconductor substrate in sequence; Forming a first photoresist pattern for forming a via hole exposing a portion of the second hard mask layer on the second hard mask layer; Etching the second hard mask layer, the second interlayer dielectric layer, the first hard mask layer, and the first interlayer dielectric layer using the first photoresist pattern as an etch mask to form a via hole; Removing the first photoresist pattern; Performing UV curing and hard baking on the semiconductor substrate from which the first photoresist pattern is removed; Forming a protective film filling the via hole; Forming a second photoresist pattern on the second hard mask layer, the second photoresist pattern forming a trench wider than the via hole with respect to the via hole; Forming a trench by etching the second hard mask layer and the second interlayer insulating layer using the second photoresist pattern as an etching mask; Removing the second photoresist pattern and the passivation layer; Performing a UV curing and hard baking process on the semiconductor substrate from which the second photoresist pattern is removed; And And etching the portion of the diffusion barrier film exposed by the via hole. The method of claim 1, Hardening the semiconductor substrate from which the first photoresist pattern or the second photoresist pattern is removed at a temperature of 300 ° C. or less under vacuum while irradiating and curing UV through UV lamps disposed on the semiconductor substrate. A dual damascene pattern forming method of a semiconductor device. The method of claim 1, And the protective film is a photosensitive film or a lower anti-reflection film. The method of claim 1, And performing UV curing and hard baking after each of the first interlayer insulating film, the first hard mask film, the second interlayer insulating film, and the second hard mask film. How to form a damascene pattern. The method of claim 1, After the etching process of the diffusion barrier, the method of forming a dual damascene of the semiconductor device further comprising the step of performing a UV curing and hard baking treatment.

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