KR101111509B1 - Method and Apparatus for frequency-domain equalizing - Google Patents

Abstract

The present invention relates to an apparatus and method for converting an error obtained in a time domain into a signal block for coefficient update of a frequency domain equalizer. The present invention provides a method of generating a data block of a double symbol clock for an FFT by receiving a received signal, equalizing in a frequency domain using the generated data block, and validating a symbol clock in the equalized signal. Extracting a signal, calculating a signal error of the extracted valid signal, converting an error signal of the calculated symbol clock into an input format of a frequency domain equalizer of a double symbol clock, and converting And returning a signal to the frequency domain equalization step to update the equalizer coefficients. Therefore, according to the present invention, there is an effect of efficiently updating the coefficients of the frequency domain equalizer by converting the feedback error signal to match the error input signal format of the frequency domain equalizer.

Frequency Domain Equalizer, Valid Data Extraction, Error Calculation, Error Signal Block

Description

Frequency domain equalization method and apparatus {Method and Apparatus for frequency-domain equalizing}

1 is a block diagram showing the configuration of a receiving system using a frequency domain equalizer according to the present invention.

2 to 3 is a view showing the signal flow of the signal block generator for error feedback according to the present invention

4 is a block diagram showing an internal configuration of an error signal block generator according to the present invention.

5 is a diagram illustrating timing of an error feedback signal block according to the present invention.

6 is a flowchart showing an operation relationship of a write address generation block according to the present invention.

7 is a flowchart illustrating an operation relationship of an output address generation block according to the present invention.

-Explanation of symbols for the main parts of the drawings-

100: demodulator 200: data formatter

300: frequency domain equalizer 400: valid data extractor

500: error calculator 600: error signal block generator

The present invention relates to a frequency domain equalizer, and more particularly, to an apparatus and method for converting an error obtained in a time domain into a signal block for coefficient update of a frequency domain equalizer.

ATSC (Advanced Television Systems Committee) 8VSB (Vestigial Side Band) transmission system proposed for US digital TV transmission, and in most digital transmission systems such as Pulse Amplitude Modulation (PAM) or Quadrature Amplitude Modulation (QAM) When data is transmitted by air or wire, the transmitted signal is received by combining the signals reflected by the various reflectors. The reflected components distort the original signal so that the original signal cannot be obtained only by the received signal.

In this way, an equalizer is used to compensate for a component (ghost or fading) that distorts the transmission signal between the transmitting end and the receiving end. The equalizer can be divided into a time-domain equalizer and a frequency-domain equalizer, all of which remove components that distort the original signal.

The frequency domain equalizer used in the VSB digital transmission system converts the time domain signal into the frequency domain to compensate for the signal distortion caused by the channel change, and then converts it back to the time domain.

At this time, in a system that does not use a cyclic prefix (CP) for copying and transmitting the rear part of the signal block in front of the block, such as the VSB signal, when the frequency domain equalization is performed, interference (IBI: Inter) is performed between the equalization blocks. Block Interference occurs.

To solve this problem, currently implemented frequency domain equalizers use twice the valid signal length as the size of the input fast fourier transform (FFT) block.

Therefore, the output unit of the frequency domain equalizer needs a function of extracting a valid block among the output signal blocks, and the extracted signals must be continuously extracted without time interruption between the blocks.

At this time, a signal error obtained from the extracted signal and the signal from which the extracted signal is determined is fed back to the frequency domain equalizer and used to update the coefficient of the frequency domain equalizer.

When the error is obtained from the extracted signal, the length of the error is shorter than the FFT (Fast Fourier Transform) length for converting the time domain error signal into a frequency domain error signal for updating the equality coefficient.

Therefore, it is an important problem to convert the time-domain error into a desired FFT signal block while matching the length of the error conversion FFT.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method and apparatus for converting an error obtained from a time domain signal that is an output of a frequency domain equalizer into a signal block for coefficient update of the frequency domain equalizer. To suggest.

In order to achieve the above object, the present invention comprises the steps of: receiving a received signal to generate a data block of a double symbol clock for the FFT, equalizing in the frequency domain using the generated data block, the equalization Extracting a valid signal of a symbol clock from the extracted signal, calculating a signal error of the extracted valid signal, and converting the calculated error signal of the symbol clock into an input format of a frequency domain equalizer of a double symbol clock And updating the equalizer coefficients by feeding back the converted signal to the frequency domain equalization step.

The converting of the error signal to match an input format of a frequency domain equalizer may include detecting a starting point of the error signal block and generating an address of a memory in which the error signal is written using the detected starting point. Storing the error signal according to the generated address, converting the block start signal of the symbol clock into a symbol start signal of a double clock reference, and converting the symbol start signal of the converted double clock reference And generating an output address for generating an error signal block, and outputting the stored error signal according to the generated output address.

The output address generating step may include inserting 0 in an invalid error time interval.

The generating of the address of the memory may include initializing the address of the memory to 0, and when the starting point of the error signal block is detected, increasing the address of the memory and storing the error signal in a buffer memory; And re-initializing the address of the memory and repeating the process when the address of the memory reaches N, the total valid error number.

The output address generating step may include initializing a delay counter value and a read address value to 0, and enabling a '0' enable signal to 1, and increasing the delay counter value when the symbol start signal based on the double clock is detected. And setting the '0' enable signal to '0' and increasing a read address when the increased delay counter reaches M, which is a time delay of an invalid error signal interval. And re-initializing when the read address reaches N, the total number of valid signals in the block.

The present invention provides a data formatter for receiving a received signal and generating a data block of a double symbol clock for an FFT, an equalizer for equalizing in a frequency domain using the generated data block, and a symbol clock in the equalized signal. A valid data extractor for extracting a valid signal, an error calculator for calculating a signal error of the extracted valid signal, and an error signal block generator for converting the error signal of the calculated symbol clock to the equalizer input format of a double signal clock It provides a frequency domain equalizer configured to include.

The error signal block generator may include a SOB detector for detecting a start point of the error signal block, a write address generator for generating an address of a memory in which the error signal is written using the detected start point, and an address according to the generated address. Generating an error signal block using a memory in which the error signal is stored, an SOB 2fs converter converting the block start signal of the symbol clock into a symbol start signal of a double clock reference, and a symbol start signal of the converted double clock reference And an output address generator for generating an output address for outputting and an '0' inserting portion for inserting and outputting '0' in an invalid signal section according to the generated output address.

Therefore, according to the present invention, there is an effect of efficiently updating the coefficients of the frequency domain equalizer by converting the feedback error signal to match the error input signal format of the frequency domain equalizer.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described.

In addition, the term used in the present invention was selected a general term that is widely used at present, but according to the emergence of a new technology, the term that the applicant deemed most appropriate in the present invention was arbitrarily used, and the meaning of the term in the corresponding description. It will be explained clearly. Therefore, in the understanding of the present invention, it is intended that the present invention should be understood as the meaning of terms rather than simple names of terms.

1 is a block diagram showing the configuration of a receiving system using a frequency domain equalizer according to the present invention.

As shown in FIG. 1, a signal received through an antenna and a tuner (not shown) is input to an equalizer through an demodulator 100.

The equalizer largely receives an effective signal from an output signal of a data formatter 200, a frequency domain equalizer 300, and the frequency domain equalizer 300, which generates an equalizer input signal for frequency domain equalization. It consists of an Effective Data Extractor 400 to extract.

The data formatter 200 generates a signal for inputting the frequency domain equalizer 300 at a later stage with a signal of twice the clock of the symbol clock with respect to the signal input to the symbol clock fs. This is to avoid the interference (IBI) between each equalization block has been described above.

The frequency domain equalizer 300 receiving the double clock input signal through the data formatter 200 performs frequency domain equalization on the signal and outputs the same.

With respect to the output signal of the equalizer 300, the valid data extractor 400 extracts the valid signal of the output signal as a signal of the original symbol clock.

In this case, in order to update the coefficient of the frequency domain equalizer 300, an error signal obtained from the output of the equalizer 300 is required. Therefore, an error calculator 500 for calculating a signal error and an error signal block generator for converting the calculated error signal to match an input format of the frequency domain equalizer 300 ( 600) is additionally needed.

The error calculator 500 calculates and outputs a signal error based on a difference between a valid signal extracted from the valid data extractor 400 and a determined value of the extracted signal, and the calculation is performed. The error is converted into a form suitable for the error input format of the frequency domain equalizer 300 through an error block generator 600 and input to the frequency domain equalizer 300.

If described in more detail with reference to the accompanying drawings the operation relationship of the equalizer (Equalizer Module) as follows.

2 to 3 are diagrams illustrating the signal flow of the error feedback signal block generator according to the present invention.

First, as shown in Fig. 2, E1, E2, E3,... The signal block shown as is an error signal block generated from the valid signal output from the valid data extractor 400 based on the symbol clock. Below that is a block start point signal (SOB) representing each output block of the valid output signal.

For the error signal generated as described above, the error signal block generator 600 inserts 0 between the error signal blocks as shown in FIG. 3 in order to convert the error signal into a double symbol clock reference signal. .

Block a, block b, block c,... Figure 3 shows the structure of the error signal block when feeding back to the input of the frequency domain equalizer 600. As shown in FIG. 3, 0 is inserted between the error signal blocks to generate and output a signal based on a double symbol clock reference.

In this case, a block start point signal SOB for informing the start point of each block of the generated signal on a double symbol clock basis is also required as shown in FIG. 3.

As such, the internal configuration of the error signal block generator 600 for converting the generated error signal into a signal of a double symbol clock reference is illustrated in FIG. 4.

4 is a block diagram showing an internal configuration of an error signal block generator according to the present invention.

As shown in FIG. 4, the error signal block generator 600 is divided into a portion that operates as a double clock (2 * fs) and a portion that operates as a symbol clock (fs).

The SOB (fs) detector 610 of the part operating as the symbol clock extracts the starting point of the error signal block input from the SOB (fs) signal.

The extracted block start signal is input to a write address generator 620. The write address generator 620 uses the block start signal to write a write address for specifying an address at which the error signal is written to the next buffer memory 630 in which the error signal is stored. Create

At this time, as shown in FIG. Are continuously generated, the write address generator 620 receives the block start signal and starts writing an error signal to the buffer memory 630 immediately after the block start. The write address is initialized each time a block starts and sequentially generates an address of a memory to be stored.

In addition, the address may be arbitrarily determined according to the structure of the memory 630. That is, for example, 0, 1, 2,... Or 0,2,4,6,... An appropriate value may be generated according to the structure of the memory 630 of FIG.

On the other hand, the buffer memory 630 is an error signal is stored before the conversion to the symbol clock, according to the present invention is a memory block that outputs the error signal in accordance with the clock twice the symbol clock.

To this end, the SOB (2fs) converter 640 converts the block start signal of the fs clock reference into a symbol start signal of twice the clock of the symbol clock.

Therefore, the error signal stored on the basis of the symbol clock is output on the basis of twice the clock of the symbol clock, and after the input of the error signal on the basis of the symbol clock, the error signal block outputting on the basis of the double clock of the symbol clock is finished. Should give a time delay.

The signal converted to the double symbol clock in this way is input to an output address generator 650. The output address generator 650 starts generating an address for generating an error signal block for outputting an error signal after a predetermined time delay based on a block start signal of twice the clock of the input symbol clock.

During the predetermined time delay, an invalid error time interval is inserted so that 0 is inserted, and when the output of the error signal is finished, 0 is inserted again before the start of the next block to generate an error feedback signal block synchronized with twice the clock of the symbol clock. A read address of the memory 630 is generated.

On the other hand, in the 'zero' insertion unit 660, the '0' enable signal is activated (1) according to the '0' enable signal generated from the output address generator 650. If it is 0, it outputs a valid error feedback signal.

The timing of the error feedback signal block generated in this manner is shown in FIG. 5.

As shown in FIG. 5, for the block start signal SOB (fs) and the error input signal Error-in based on the symbol clock, there is an output signal of an error signal block generated according to the present invention. In this case, it can be seen that the error input signal starts and exists simultaneously with the start of each signal block. In addition, the block start signal of the clock reference twice the symbol clock generated from the SOB 2fs converter 640 of FIG. 4 is denoted as SOB 2fs.

After all of the error input signals are stored in the memory 630, the block start signal is delayed and output by a time delay added by a predetermined time delay so that the error input signal is output to the output of the error feedback signal block. A time point stored in the memory 630 should be earlier than a time point output from the memory 630.)

A signal generated as an error feedback signal block by inserting 0 based on the SOB 2fs is a formatted error out signal.

6 is a flowchart illustrating an operation relationship of a write address generation block according to the present invention.

As shown in FIG. 6, the write address generation unit 620 according to the present invention first initializes the write address to '0'. (S10) After the SOB (fs) is detected (S20), the write address is set by one. The error signal is increased and input to the buffer memory 630 in synchronization with the symbol clock. (S30) When the write address reaches N, which is the total valid error signal number of the block (S40), the write address is reinitialized and the Repeat the process.

7 is a flowchart illustrating an operation relationship of an output address generation block according to the present invention.

As shown in FIG. 7, in the output address generator 650 according to the present invention, a value of a delay counter and a read address of an invalid section are 0 and '0'. The enable signal is initialized to 1 (S10).

Thereafter, if the SOB (2fs) signal is detected, the delay counter is incremented by one (S30), and if not detected, the delay counter is kept in the initial state.

When the increased delay counter reaches M, which is a time delay of an invalid error signal section, the enable signal is set to '0' so that a valid error signal is output. (S50) In this case, the buffer memory 630. The error signal stored in) is outputted, and the read address is also increased by one.

When the increased read address reaches N, which is the total number of valid signals in the block (S60), it returns to the initial state again.

The present invention is not limited to the above-described embodiments, and as can be seen in the appended claims, modifications can be made by those skilled in the art to which the invention pertains, and such modifications are within the scope of the present invention.

The frequency domain equalization method and apparatus according to the present invention described above have an effect of efficiently updating the coefficients of the frequency domain equalizer by converting the feedback error signal to match the error input signal format of the frequency domain equalizer.

Claims (7)

Receiving a received signal and generating a data block of a double symbol clock for an FFT; Equalizing in a frequency domain using the generated data block; Extracting a valid signal of a symbol clock from the equalized signal; Calculating a signal error of the extracted valid signal and outputting an error signal of a symbol clock; Format converting the error signal of the calculated symbol clock into an error signal of a double symbol clock; And And returning the converted error signal to the frequency domain equalization step to update an equalizer coefficient. The method of claim 1, Format converting the error signal of the calculated symbol clock into an error signal of a double symbol clock, Detecting a starting point of the error signal block; Generating an address of a memory in which the error signal is written using the detected starting point; Storing the error signal according to the generated address; Converting a block start signal of the symbol clock into a symbol start signal of a double clock reference; Generating an output address for generating an error signal block by using the converted symbol start signal of the double clock reference; And And outputting the stored error signal in accordance with the generated output address. The method of claim 2, The output address generation step, And zero in an invalid error time interval. The method of claim 2, Generating an address of the memory, Initializing the address of the memory to zero; If the starting point of the error signal block is detected, increasing the address of the memory and storing the error signal in a buffer memory; And And reinitializing the address of the memory when the address of the memory reaches N, the total significant error number. The method of claim 2, The output address generation step, Initializing a delay counter value and a read address to 0 and a '0' enable signal to 1; Incrementing the delay counter value when the symbol start signal of the double clock reference is detected; Setting the '0' enable signal to '0' and increasing a read address when the increased delay counter reaches a time delay counter value of an invalid error signal interval; And And reinitializing when the increased read address reaches the total valid signal number in the block. A data formatter for receiving a received signal and generating a data block of a double symbol clock for an FFT; An equalizer for equalizing in a frequency domain by using the generated data block; A valid data extractor for extracting a valid signal of a symbol clock from the equalized signal; An error calculator for calculating a signal error of the extracted valid signal and outputting an error signal of a symbol clock; And And an error signal block generator to format convert the error signal of the calculated symbol clock into an error signal of a double symbol clock. The method of claim 6, The error signal block generator, An SOB detector for detecting a starting point of the error signal block; A write address generator configured to generate an address of a memory to which the error signal is written using the detected starting point; A memory in which the error signal is stored according to the generated address; A SOB 2fs converter converting the block start signal of the symbol clock into a symbol start signal of a double clock reference; An output address generator configured to generate an output address for generating an error signal block using the converted double clock reference symbol start signal; And And an '0' inserting unit inserting and outputting a '0' in an invalid signal section according to the generated output address.

Images