KR101108409B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display device having a uniform cell gap by compensating the step difference of the cell gap for each position of the liquid crystal panel, the first and second substrates; A plurality of gate lines arranged in a first direction on the first substrate; A plurality of data lines arranged perpendicular to the gate line to define an image display unit in which a plurality of pixels are formed; A gate pad part formed on one side of the gate line; A data pad unit formed at one side of the data line; A gate TCP electrically connected to the gate pad unit and having a plurality of first gate signal transmission lines and a gate driving IC mounted thereon; A data TCP electrically connected to the data pad unit, the data TCP including a plurality of second gate signal transmission lines, and mounted with a data driving IC; A LOG wiring part formed on the first substrate and electrically connecting the first gate signal transmission line and the second gate signal transmission line; An antistatic circuit formed on the other side of the gate line and the data line; A ground wire for grounding the antistatic circuit; And a liquid crystal layer formed on the first and second substrates, wherein the first cell gap of the gate pad part and the data pad part, the second cell gap of the LOG wiring part, and the third cell gap of the ground wiring part are the same. A display element is provided.

Description

Liquid crystal display device {LIQUID CRYSTAL DISPLAY DEVICE}

1 is a cross-sectional view showing a portion of a LOG wiring portion, a pad portion, and a ground wiring portion of a conventional liquid crystal display device.

2 is a view showing a liquid crystal display device according to the present invention.

3A and 3B show a part of the gate pad portion of FIG. 2 in detail, FIG. 3A is a plan view, and FIG. 3B is a sectional view taken along the line II ′ of FIG. 3A.

4A and 4B show a part of the data pad portion of FIG. 2 in detail, FIG. 4A is a plan view, and FIG. 4B is a sectional view taken along line II-II 'of FIG. 4A.

5A and 5B show a part of the LOG wiring portion of FIG. 2 in detail, FIG. 5A is a plan view, and FIG. 5B is a sectional view taken along line III-III 'of FIG. 5A.

6A and 6B show a part of the ground wiring part of FIG. 2 in detail, FIG. 6A is a plan view, and FIG. 6B is a sectional view taken along line IV-IV 'of FIG. 6A.

*** Explanation of symbols for main parts of drawing ***

110: first substrate 120: second substrate

123: seal pattern 137: LOG wiring

153: ground wiring 161: gate pad

162: gate insulating film 163: data pad                 

165: active pattern 181: protective film

170a-170c: Halls 1-3

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device that can compensate for the step difference of the cell gap for each position of the liquid crystal panel.

In general, a liquid crystal display device displays a desired image by separately supplying data signals according to image information to liquid crystal cells arranged in a matrix, and adjusting the light transmittance of the liquid crystal cells. to be.

Accordingly, the liquid crystal display device comprises: a liquid crystal panel in which liquid crystal cells in pixel units are arranged in a matrix form; And a driving circuit for driving the liquid crystal cells.

The liquid crystal panel includes a color filter substrate and a thin film transistor array substrate, and a liquid crystal layer formed between the color filter substrate and the thin film transistor array substrate. In this case, the color filter substrate and the thin film transistor array substrate are bonded to each other by a seal pattern formed on the outer side of the liquid crystal panel.

The color filter substrate is formed with a black matrix to prevent light leakage between the color filter and the pixels.

The thin film transistor array substrate has a gate line and a data line arranged vertically and horizontally to define a plurality of pixels, and a switching element for switching each pixel is formed at an intersection of the gate line and the data line. .

One side of the gate line and the data line is provided with a gate pad and a data pad for electrically connecting the driving circuit, and the other side of the gate line and the data line, that is, an antistatic circuit on the opposite side of the gate pad and the data pad Is provided. In addition, a ground line connecting the antistatic circuit to one is formed.

The driving circuit includes a gate driver for supplying a scan signal to a gate pad of the liquid crystal panel and a data driver for supplying image information to a data pad, wherein the gate driver and the data driver are a plurality of integrated circuits. Are integrated into

The data driver ICs and the gate driver ICs are respectively mounted on a tape carrier package (TCP) and connected to a liquid crystal panel using a tap automated bonding (TAB) method or chip on glass (chip on glass). on glass: Hereafter, it is mounted on a liquid crystal panel by a COG) method.

The data driver ICs and gate driver ICs mounted on the TCP and connected to the liquid crystal panel in a tap method are input from the outside through signal lines mounted on a printed circuit board (PCB) connected to the TCP. Control signals are supplied.

Meanwhile, data driver ICs and gate driver ICs mounted on the liquid crystal panel using the COG method are input from the outside through line on glass (LOG) wires mounted on the thin film transistor array substrate of the liquid crystal panel. Control signals are supplied. In recent years, even when the data driver ICs or the gate driver ICs are connected to the liquid crystal panel in a tapped manner, a technology for removing PCBs by mounting LOG wirings on the liquid crystal panel has been developed. The display element can be further thinned.

In particular, the LOG PCB is mounted on the liquid crystal panel for the gate driving ICs that require fewer signals than the data driving ICs, thereby eliminating the gate PCB.

Since the types of patterns formed according to the liquid crystal display device configured as described above are different from each other, the image quality deterioration due to the cell gap nonuniformity appears. In particular, since the heights of the patterns are formed differently according to the position where the seal pattern passes, screen stains are generated due to the cell gap difference around the seal pattern.

In more detail, in the liquid crystal panel in which the LOG wiring is formed, a seal pattern for bonding the color filter substrate and the thin film transistor array substrate is formed along the outer edge of the panel. In particular, the corner area of the panel where the LOG wiring is formed (hereinafter, And a ground line for connecting an antistatic circuit to opposite sides of the gate / data pad portion.

On the other hand, the hole is formed along the region where the seal pattern is formed in order to improve the adhesion between the seal pattern and the substrate. That is, a hole is formed between the LOG wiring and the ground wiring part and the gate pad or the data pads, and the depth of the hole is formed differently in the LOG wiring part, the gate / data pad part, and the ground wiring part. Thus, cell gap nonuniformity occurs in the region where the seal pattern is formed.

1 illustrates a cross section of a LOG wiring part, a pad part, and a ground wiring part in which a conventional hole is formed.

First, the LOG wiring 3 and the gate insulating film 5 are stacked on the transparent substrate 10 in the LOG wiring part, and a protective film 9 is formed on the gate insulating film 5. In addition, a first hole 8a is formed in the passivation layer 9 to improve adhesion to the seal pattern, and an active pattern 7 is formed on the gate insulating layer 5 corresponding to the first hole 8a. It is. At this time, the active pattern 7 is for preventing the LOG wiring 3 from being exposed to air and corroded. That is, in the process of forming the first hole 8a, since the protective film 9 and the gate insulating film 5 are etched at the same time to expose the LOG wiring 3, the gate insulating film 5 is formed on the gate insulating film 5. As the etch stop film (5), an active pattern 7 is provided to prevent the LOG wiring 3 from being exposed.

In addition, a gate insulating film 5 and a protective film 9 are stacked on the transparent substrate 10 in the pad part (gate and data pad part), and a part of the gate insulating film 5 and the protective film 9 is removed. The second hole 8b exposing the substrate 10 is formed.

In the ground wiring portion, the ground wiring 6 is formed on the transparent substrate 10, and the gate insulating film 5 and the protective film 9 are stacked thereon. A portion of the gate insulating film 5 and the protective film 9 is removed to form a third hole 8c exposing the ground wiring 6.                         

As shown in the figure, since the types of patterns formed on the LOG wiring part, the pad part, and the ground wiring part are different, the depths of the first to third holes 8a to 8c are different from each other. That is, the depth of the first hole 8a in the LOG wiring part is formed deeper than the second hole 8b in the pad part and the third hole 8c in the ground wiring part. The depth of the second hole 8b is formed deeper than the depth of the third hole 8c.

As described above, since the depth of the hole is different for each position where the seal pattern is formed in the liquid crystal panel, the thickness of the seal pattern is different for each position of the liquid crystal panel, resulting in a problem of uniform cell gap around the seal pattern.

Accordingly, the present invention has been made to solve the conventional problems as described above, an object of the present invention is to compensate for the step difference of the cell gap for each position of the liquid crystal panel, the liquid crystal to maintain a uniform cell gap throughout the liquid crystal panel It is to provide a display element.

The present invention for achieving the above object is the first and second substrate; A plurality of gate lines arranged in a first direction on the first substrate; A plurality of data lines arranged perpendicular to the gate line to define an image display unit in which a plurality of pixels are formed; A gate pad part formed on one side of the gate line; A data pad unit formed at one side of the data line; A gate TCP electrically connected to the gate pad unit and having a plurality of first gate signal transmission lines and a gate driving IC mounted thereon; A data TCP electrically connected to the data pad unit, the data TCP including a plurality of second gate signal transmission wiring lines and mounted with a data driving IC; A LOG wiring part formed on the first substrate and electrically connecting the first gate signal transmission line and the second gate signal transmission line; An antistatic circuit formed on the other side of the gate line and the data line; A ground wire for grounding the antistatic circuit; And a liquid crystal layer formed on the first and second substrates, wherein the first cell gap of the gate pad part and the data pad part, the second cell gap of the LOG wiring part, and the third cell gap of the ground wiring part are the same. A display element is provided.

The first substrate corresponding to the gate pad part may include a gate pad disposed at a predetermined distance on the first substrate, a gate insulating film formed on the gate pad, and a gate insulating film corresponding to a spaced area between the gate pads. A protective film having a first compensation pattern formed, an active pattern formed on the first compensation pattern, and a first hole exposing the active pattern is formed. In this case, the gate pad may be formed of Mo / AlNd, and the first compensation pattern may be formed of Mo. The first compensation pattern is formed together in the process of forming the data pad.

On the first substrate corresponding to the data pad part, a second compensation pattern disposed at a predetermined distance on the first substrate, a gate insulating film formed on the second compensation pattern, and a corresponding second compensation pattern A data pad formed on the gate insulating layer corresponding to an active pattern formed on the gate insulating layer and a spaced apart area between the second compensation pattern; A passivation layer having a second hole exposing the active pattern is formed on the data pad. In this case, the second compensation pattern may be formed of Mo / AlNd, the data pad may be formed of Mo, and the second compensation pattern is formed together in a process of forming a gate pad.

On the first substrate corresponding to the LOG wiring part, a LOG wiring formed on the first substrate, a gate insulating film formed on the LOG wiring, an active pattern formed on the gate insulating film, and a third active pattern exposed through the gate wiring film. A protective film having a hole is formed.

A protective film having a ground wiring formed on the first substrate, a gate insulating film formed on the ground wiring, a fourth hole on the gate insulating film, and a fourth hole on the first substrate corresponding to the ground wiring part; An active pattern is formed on the corresponding gate insulating film. In this case, the ground line may be formed of Mo / AlNd, and together with the gate pad and the second compensation pattern.

The protective film formed on the gate and data pad part, the LOG wiring part, and the ground wiring part may include a first inorganic film formed on the gate insulating film, an organic film formed on the first inorganic film, and a second inorganic film formed on the organic film. It consists of a membrane. The first and second inorganic layers may be formed of SiNx or SiOx, and the organic layer may be formed of BenzoCyloButene (BCB) or photo acryl.

On the other hand, the second substrate is formed with a black matrix for preventing light leakage between the color filter and the pixel to implement the color.

As described above, the present invention compensates for the difference in cell gaps between the gate and data pad parts, the LOG wiring part, and the ground wiring part. That is, a first compensation pattern and an active pattern are further formed in the data pad part, and a second compensation pattern and an active pattern are formed in the gate pad part so that the LOG wiring part and the cell gap are the same. An active pattern is further formed in the ground wiring part so that the cell gap is the same as that of the LOG wiring part.

Hereinafter, the liquid crystal display device according to the present invention will be described in more detail with reference to the accompanying drawings.

2 is a plan view schematically showing a liquid crystal display device according to the present invention.

As shown in the figure, the liquid crystal display device 100 includes a liquid crystal panel 100a in which an image display unit 121 is defined, and a plurality of data TCPs 130 provided on one long side of the liquid crystal panel 100a. ; A plurality of gate TCPs (140) provided at one side of the liquid crystal panel (100a); Data driver ICs 135 mounted on the data TCPs 130, respectively; The gate driver ICs 145 are respectively mounted on the gate TCPs 140.

The liquid crystal panel 100a is a liquid crystal layer (not shown) formed between the first substrate 110, which is a thin film transistor array substrate, the second substrate 120, which is a color filter substrate, and the first and second substrates 110, 120. The first and second substrates 110 and 120 are bonded to each other by a seal pattern 123 formed along an outer edge thereof.

One short side and one long side of the first substrate 110 protrude from the second substrate 120, and the protruded region is electrically connected to the gate driving IC 145 through the gate TCP 140. A gate pad portion and a data pad portion electrically connected to the data driver IC 135 through the data TCP 130 are provided.                     

The first substrate 110 of the image display unit 121 includes a plurality of gate lines 119 connected to the gate pad unit and arranged in a direction perpendicular to the gate lines, and unit pixels together with the gate lines 119. And a data line 118 connected to the data pad part. At the intersection of the gate line 119 and the data line 118, a switching element for independently switching each unit pixel is provided.

Meanwhile, a LOG wiring unit 137 is provided in one corner area of the first substrate 110 to receive control signals and driving voltages to the gate TCP 140 through the data TCP 130. Accordingly, a first gate transmission wiring 137a for transmitting the gate signals supplied from the printed circuit board 150 to the LOG wiring unit 137 of the first substrate 110 is additionally provided at one side of the data TCP 130. The gate TCP 140 has a second gate transfer wiring 137b for transmitting a signal to the gate TCP 140 through the first gate transfer wiring 137a and the LOG wiring 137. . In this case, the LOG wiring part 137 is patterned together in the process of forming the gate line and the gate pad part.

In addition, an antistatic circuit 151 is provided on the other side of the gate line 119 and the data line 118, that is, at opposite sides of the gate pad part and the data pad part, and is formed along the outer side of the first substrate 110. The ground wiring part 153 which grounds the antistatic circuit is formed. In this case, the ground wiring part 153 is also formed in the gate line and the gate pad process.

In addition, the second substrate 120 is formed with a color filter layer for realizing color and a black matrix for preventing light leakage between each pixel.                     

The first substrate 110 and the second substrate 120 configured as described above are bonded to each other by a seal pattern 123 formed along the periphery of the image display unit 121. In particular, the seal pattern 123 may be a second substrate. The gate pad part and the data pad part overlapping the outer side of the substrate 120 are also formed in the area where the LOG wiring part 137 and the ground wiring part 153 are formed.

Although not shown in detail in the drawing, the adhesive force with the seal pattern 123 is improved on the gate pad portion, the data pad portion, the LOG wiring portion 137 and the ground wiring portion 153 on which the seal pattern 123 is formed. The same type of pattern is formed in the first substrate corresponding to the region in which the hole is formed, and the gate pad portion, the data pad portion, the LOG wiring portion 137, and the ground wiring portion ( 153) maintain the same cell gap.

According to the region where the seal pattern 123 is formed, the patterns formed on the first substrate 110 will be described in more detail. A gate insulating layer, an active pattern, a compensation pattern, and a protective layer are formed on the gate pad part. The data pad part includes a compensation pattern, a gate insulating film, an active pattern, and a protective film. LOG wiring, a gate insulating film, an active pattern, and a protective film are formed in the LOG wiring part 137, and a ground wiring, a gate insulating film, an active pattern, and a protective film are formed in the ground wiring part 153. At this time, the compensation pattern of the gate and the data pad part is formed for the compensation of the cell gap with the other area, and the LOG wiring and the ground wiring are patterned and formed in the same process, and have the same thickness pattern.

3A to 3B, 4A to 4B, 5A to 5B, and 6A to 7B show detailed drawings of regions of a liquid crystal panel in which a seal pattern is formed.

3A and 4A are plan views showing portions of the gate pad portion and the data pad portion, respectively, and FIG. 3B is a sectional view taken along line II ′ of FIG. 3A, and FIG. 4B is a cross-sectional view taken along line II-II ′ of FIG. 4A, respectively. will be.

5A and 6A are plan views showing portions of a LOG wiring part and a ground wiring part, respectively, and FIG. 5B is a sectional view taken along line II ′ of FIG. 5A, and FIG. 6B is a II-II ′ of FIG. 6A, respectively. .

First, referring to the gate pad part (see FIGS. 3A and 3B), the gate pad part is formed with gate pads 161 regularly arranged on the first substrate 110 at predetermined intervals, and the seal pattern 123. The first holes 170a are formed in the spaced areas of the gate pads 161 formed therein to improve adhesion to the seal pattern 123.

A gate insulating layer 162 is formed on the first substrate 110 including the gate pad 161, and a passivation layer 181 is formed on the gate insulating layer 162. In particular, a compensation pattern 163a and an active pattern 165 are formed on the gate insulating layer 162 corresponding to the first hole 170a.

In this case, the gate pad 161 may be formed of a double metal layer made of Mo / AlNd, and the compensation pattern 163a may be formed without patterning by patterning the data pad and the data pad together. . The compensation pattern 163a may be formed of a Mo metal layer.

In addition, the active pattern 165 may be formed without an additional process in the process of forming the active layer of the switching device, and may be formed of a semiconductor layer.

In addition, the passivation layer 181 exposing the active pattern 165 through the first hole 170a may be formed of only an organic layer or may be formed by mixing an organic layer and an inorganic layer. That is, the first and second inorganic films 181a and 181c and the organic film 181b interposed therebetween may be formed as a triple film. This is because the adhesion of the organic film is weak, and an inorganic film is added to improve the adhesion with the lower layer and the upper layer of the protective film. The first and second inorganic layers 181a and 181c may be formed of SiNx or SiOx, and the organic layer 181b may be formed of BCB (BenzoCyloButene) or photoacryl.

Further, in the data pad part (see FIGS. 4A and 4B), a compensation pattern 161a is formed on the first substrate 110, and a gate is formed on the first substrate 110 including the compensation pattern 161a. An insulating film 162 is formed. In this case, the compensation pattern 161a may be formed together in a process of forming a gate pad, and thus may be formed without an additional process. In particular, the compensation pattern 161a may be formed of a double metal layer made of Mo / AlNd.

In addition, data pads 163 regularly arranged at predetermined intervals are formed on the gate insulating layer 162, and the pads 163 may be formed to improve adhesion to the seal pattern 123 in the spaced areas of the pads 163. Two holes 170b are formed. The data pad 163 may be formed of a Mo metal layer.

In addition, an active pattern 165 is formed on the gate insulating layer 162 corresponding to the second hole 170b, and a triple layer (first and first layers) is formed on the gate insulating layer 162 including the data pad 163. A protective film 181 made of two inorganic films 181a and 181c and an organic film 181b is formed.

As such, a gate insulating layer 162, a compensation pattern 163a, and an active pattern 165 are formed on the first substrate 110 corresponding to the first hole 170a in the gate pad part. The compensation pattern 161a, the gate insulating layer 162, and the active pattern 165 are formed on the first substrate 110 corresponding to the second hole 170b. In this case, the compensation pattern 163a of the gate pad part is formed together with the data pad, and the compensation pattern 161a of the data pad part is formed together with the gate pad. Since the thickness difference between the two is very small, the first and The patterns corresponding to the second holes 170a and 170b have almost the same height. That is, the compensation pattern 163a of the gate pad part is about 2500 mW, and the compensation pattern 161a of the data pad part is about 2000 mW. Therefore, the depths of the first and second holes 170a and 170b are the same.

Further, in the LOG wiring part (refer to FIGS. 5A and 5B), the LOG wiring 137 regularly arranged at a predetermined interval is formed on the first substrate 110. The LOG wiring 137 and these A third hole 170c is formed in the spaced area to improve adhesion to the seal pattern 123. In this case, the LOG wiring 137 may be formed together in the process of forming the gate line and the gate pad, and may be formed of a double metal layer made of Mo / AlNd.

A gate insulating film 162 is formed on the first substrate 110 including the LOG wiring 137, and an active pattern 165 is formed on the gate insulating film 162. The third hole 170c exposing the active pattern 165 is formed on the substrate.                     

The protective layer 181 of the triple layer (the first and second inorganic layers 181a and 181c and the organic layer 181b) is formed on the gate insulating layer 162.

In addition, a ground wiring 153 is formed on the first substrate 110 in the ground wiring part (see FIGS. 6A and 6B), and the adhesive force with the seal pattern 123 is applied on the ground wiring 153. A fourth hole 170d is formed to make it good. In this case, the ground line 153 may be formed together in the process of forming the gate line and the gate pad, and may be formed of a double metal layer made of Mo / AlNd.

A gate insulating layer 162 is formed on the first substrate 110 including the ground wiring 153, and a passivation layer 181 is formed on the gate insulating layer 162. In particular, an active pattern 165 is formed on the gate insulating layer 162 corresponding to the fourth hole 170d, and triple layers (first and second inorganic layers 181a and 181c) are formed on the gate insulating layer 162. And a protective film 181 of the organic film 181b are formed.

As such, the LOG wiring 137, the gate insulating layer 162, and the active pattern 165 are formed on the first substrate 110 corresponding to the third hole 170c in the LOG wiring portion. The ground wiring 153, the gate insulating layer 162, and the active pattern 165 are formed on the first substrate 110 corresponding to the fourth hole 170d. In this case, since the LOG wiring 137 and the ground wiring 153 are formed in the same process, the patterns are the same, and the depths of the third and fourth holes 181c and 181d are also the same.

Meanwhile, in the active pattern 165 formed on the LOG wiring part, the gate insulating film 162 is etched together with the passivation layer 181 in the process of forming the third hole 170c to prevent the LOG wiring from being exposed. In order to do this, the etch stop layer of the gate insulating layer 162 is formed. Therefore, an active pattern must be formed in the LOG wiring part.

The active pattern formed on the gate pad part, the data pad part, and the ground wiring part is formed to match the depth of the LOG wiring part and the hole. Further, the compensation pattern of the gate pad portion and the data pad portion is also formed so that the depth of the hole in this region is equal to the hole depth of the LOG wiring portion.

Therefore, by equalizing the depths of the holes formed along the gate pad portion, the data pad portion, the LOG wiring portion, and the ground wiring portion in which the seal pattern is formed, the height of the seal pattern is formed uniformly, so that the cell gap unevenness can be solved. do.

As described above, the present invention further provides active patterns and compensation patterns on the area where the seal pattern is formed, in particular, on the first substrate corresponding to the formed hole to improve the adhesion with the seal pattern. The cell gap difference for each position can be reduced. That is, the compensation pattern and the active pattern are additionally formed in the gate pad part and the data pad part, and the active pattern is further formed in the ground wiring part to form the height of the pattern formed in the gate pad part, the data pad part and the ground wiring part. By making the same as the LOG wiring part, the depth of the holes formed in each is equalized to make the cell gap around the seal pattern uniform.

As described above, according to the present invention, the active pattern and the compensation pattern are additionally formed in the seal pattern region formed along the periphery of the liquid crystal panel, thereby compensating cell gap unevenness for each position of the liquid crystal panel.                     

As such, by compensating the cell gap for each position of the liquid crystal panel, the image quality defect can be eliminated and the image quality of the liquid crystal panel can be further improved.

Claims (14)

First and second substrates; A plurality of gate lines arranged in a first direction on the first substrate; A plurality of data lines arranged perpendicular to the gate line to define an image display unit in which a plurality of pixels are formed; A gate pad part formed on one side of the gate line; A data pad unit formed at one side of the data line; A gate TCP electrically connected to the gate pad unit and having a plurality of first gate signal transmission lines and a gate driving IC mounted thereon; A data TCP electrically connected to the data pad unit, the data TCP including a plurality of second gate signal transmission lines, and mounted with a data driving IC; A LOG wiring part formed on the first substrate and electrically connecting the first gate signal transmission line and the second gate signal transmission line; An antistatic circuit formed on the other side of the gate line and the data line; A ground wiring part for grounding the antistatic circuit; And And a liquid crystal layer formed on the first and second substrates, wherein the first cell gap of the gate pad part and the data pad part, the second cell gap of the LOG wiring part, and the third cell gap of the ground wiring part are the same. device. The method of claim 1, wherein the first substrate corresponding to the gate pad portion, A gate pad disposed at a predetermined distance on the first substrate; A gate insulating film formed on the gate pad; A first compensation pattern formed on the gate insulating layer corresponding to the space between the gate pads; An active pattern formed on the first compensation pattern; And And a protective film having a first hole exposing the active pattern. The liquid crystal display of claim 2, wherein the gate pad is formed of Mo / AlNd. The liquid crystal display device of claim 3, wherein the first compensation pattern is formed of Mo. According to claim 1, On the first substrate corresponding to the data pad unit, A second compensation pattern disposed at a predetermined distance on the first substrate; A gate insulating film formed on the second compensation pattern; An active pattern formed on the gate insulating layer corresponding to the second compensation pattern; A data pad formed on the gate insulating layer corresponding to the spaced apart region between the second compensation patterns; And a protective film having a second hole exposing the active pattern on the data pad. The liquid crystal display device of claim 5, wherein the second compensation pattern is formed of Mo / AlNd. 6. The liquid crystal display device according to claim 5, wherein the data pad is formed of Mo. According to claim 1, On the first substrate corresponding to the LOG wiring portion, A LOG wiring formed on the first substrate; A gate insulating film formed on the LOG wiring; An active pattern formed on the gate insulating layer; And And a protective film having a third hole exposing the active pattern. According to claim 1, On the first substrate corresponding to the ground wiring portion, A ground wiring formed on the first substrate; A gate insulating film formed on the ground wiring; A protective film having a fourth hole on the gate insulating film; And And an active pattern formed on the gate insulating layer corresponding to the fourth hole. The liquid crystal display of claim 1, wherein the ground wiring portion is formed of Mo / AlNd. The protective film according to any one of claims 2, 5, 8, and 9, wherein: A first inorganic film formed on the gate insulating film; An organic film formed on the first inorganic film; And And a second inorganic film formed on the organic film. 12. The liquid crystal display device according to claim 11, wherein the first and second inorganic films are SiNx or SiOx. The liquid crystal display device of claim 11, wherein the organic layer is BCB (BenzoCyloButene) or photoacryl. The liquid crystal display of claim 1, wherein a color filter and a black matrix are formed on the second substrate.

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