KR101106467B1 - Timing controller, clock synchronization apparatus comprising the same timing controller and method for acquiring clock synchronization using the same timing controller in orthogonal frequency division multiplexingOFDM communication system - Google Patents

Abstract

The present invention provides a timing adjusting device capable of minimizing power consumption and minimizing symbol interference in timing adjustment, and a clock synchronizing device including the adjusting device and a clock synchronizing method using the adjusting device. . The timing adjusting device includes a clock generator for generating a clock signal equal to the sampling frequency of the transmitter; A phase adjustment signal generator for generating a phase adjustment signal (Fraction-D); And a clock and phase adjustment signal updating unit for updating the clock and phase adjustment signals, wherein updating of the clock and phase adjustment signals by the update unit is a guard symbol period of an orthogonal frequency division multiplexing (OFDM) symbol. Is done in

Sampling Frequency Offset (SFO), Sampling Frequency Offset Recovery (SFOR), Decimation Filter, Timing Error Detector (TED), Timing controller

Description

Timing controller, clock synchronization apparatus comprising the same timing controller and method for acquiring clock in timing synchronization apparatus and clock adjusting apparatus in orthogonal frequency division multiplexing (OPDM) communication system synchronization using the same timing controller in orthogonal frequency division multiplexing (OFDM) communication system}

The present invention relates to Orthogonal Frequency Division Multiplexing (OFDM) communication, and more particularly, to an apparatus and a clock synchronization acquisition method for clock synchronization acquisition in an OFDM communication system.

The OFDM communication system is positioned as a representative system of the wireless communication market in recent years. In general, an OFDM transmission system transmits information on a sub-carrier by using a fast fourier transform (FFT). In order to reduce the influence of the multipath, a guard interval is inserted before the effective symbol interval. The OFDM system receives a boundary between a guard period (guard symbol period) and a valid symbol period (FFT symbol period) in the received OFDM signal and performs FFT only on the valid symbol period.

On the other hand, since the OFDM communication system carries information on a plurality of subcarriers at the same time, the clock synchronization must be accurate to increase the reception rate. In a communication system using 16-QAM or a higher QAM modulation scheme, failure to obtain clock synchronization affects reception rates such as symbol interference and phase rotation within symbols.

The apparatus for clock synchronization acquisition is largely composed of an interpolation filter unit, a clock error estimation unit, and a timing adjusting unit. The timing adjusting unit inputs a phase error value obtained from the clock error estimator to the interpolation filter unit and extracts a symbol transmitted through the clock of the transmitter. The timing adjustment unit generates a phase adjustment signal [Fraction-D] and a clock selection signal [SKIP / DUP]. The phase adjustment signal is used as the phase adjustment of the interpolation filter unit, and the range generally operates between 0 and 1. The clock selection signal converts the phase of the clock 180 degrees when the phase adjustment signal exceeds 1 and returns to 0 again. That is, the clock selection signal is used to adjust the integer part phase error (Integer-D) and the phase adjustment signal is used to adjust the fractional part phase error (Fraction-D).

The clock used in the conventional clock selection signal uses a clock that is twice as fast as the sampling frequency of the transmitter, and the role of converting the clock phase by 180 degrees is performed by selecting one of the next clocks and then resting the clock generated twice as fast. On the other hand, if you need to pull the clock forward, you can pull the section of the FFT forward one sample.

FIG. 1 is a graph illustrating a method of estimating a clock error through a structure in which a range of a conventional phase adjustment signal is limited to [0, 1], and the integer part skips / copys a sample.

As can be seen from FIG. 1, the clock error between transmission and reception increases with time, so that the estimated curve of the clock error has a straight line with a predetermined slope. However, the range of the phase adjustment signal is limited to [0, 1] and the integer part adjusts the clock error by periodically updating the estimation curve in a structure that skips / copyes the samples. Here, the phase adjustment signal is used to define the phase change of 360 ° to 1. In other words, 0 corresponds to no phase change, 1 corresponds to 360 °, and -1 corresponds to -360 °. Hereinafter, the same meaning is used.

FIG. 2 is a graph showing a clock for skip / dup, i.e., a sample selection signal, in the conventional clock synchronizing apparatus, selecting an appropriate clock in a phase change part by using a multi-clock which is twice as fast as a sampling frequency.

As shown in FIG. 2, the conventional clock selection signal converts the clock phase by 180 degrees using a multi-clock which is twice as fast as the sampling frequency of the transmitter. As described above, the phase shift may be performed by omitting one clock and selecting the next clock in the portion where the phase adjustment signal needs to be updated. This figure shows that the clock is 4 times faster.

However, such a conventional timing adjuster uses a clock frequency more than twice as large as the sampling frequency and consumes a lot of power, and in case of a communication system using a high QAM modulation scheme, when an incorrect clock flows between the transmission and reception independently. ISI symbol interference may occur, resulting in poor reception.

Accordingly, a problem to be solved by the present invention is a timing adjusting device capable of minimizing power consumption and minimizing symbol interference in timing adjustment, and using a clock synchronizing device including the adjusting device and the adjusting device. It is to provide a clock synchronization acquisition method.

In order to achieve the above object, the present invention provides a clock generator for generating a clock signal equal to the sampling frequency of the transmitter; A phase adjustment signal generator for generating a phase adjustment signal (Fraction-D); And a clock and phase adjustment signal updating unit for updating the clock and phase adjustment signals, wherein updating of the clock and phase adjustment signals by the update unit is a guard symbol period of an orthogonal frequency division multiplexing (OFDM) symbol. It provides a timing adjustment device, characterized in that made in.

In the present invention, the phase adjustment signal may operate between -2 and 2, particularly, in order to reduce the error between the estimated sample of the interpolation filter and the sample of the transmission signal, preferably in the range of -1.5 to 1.5. On the other hand, the starting point of the guard symbol of the OFDM symbol can be obtained by using the maximum likelihood estimation (Maximum-likelihood estimation) method.

In the present invention, when the phase adjustment signal is greater than 1 or less than -1 in the interval of the guard symbol, the phase adjustment signal and the clock signal are subtracted by 2, and the phase adjustment signal is greater than -1. In the case of up to 1, by subtracting 1 from the phase adjustment signal and the clock signal, the clock and phase adjustment signal can be updated in the guard symbol period. On the other hand, when the clock and the phase adjustment signal is smaller than zero, it is compensated by the step code, which is a phase shift signal. The clock and phase adjustment signal may be updated by using a step code.

In the present invention, in the guard symbol period, if the phase adjustment signal is greater than 1, 2 is subtracted from the phase adjustment signal and the clock signal, and if the phase adjustment signal is greater than 0.5, 1 from the phase adjustment signal and the clock signal. If the phase adjustment signal is less than -0.5, add 1 to the phase adjustment signal and the clock signal, and if the phase adjustment signal is less than -1, add 2 to the phase adjustment signal and the clock signal. In addition, the clock and phase adjustment signal may be updated in the guard symbol period. The update of the clock and phase adjustment signals in this manner can be accomplished without using a step code, which is a phase shift signal.

The present invention also provides an analog-to-digital converter (ADC) for converting the transmitted analog signal into a digital signal to achieve the above object; An interpolation filter for sampling the digital signal; An FFT unit performing a fast Fourier transform (FFT) on the sampled signal; A clock error estimator for estimating a clock error with respect to the signal output to the FFT unit; A rope filter controlling amplitude distortion on the signal output from the clock error estimator; And a timing adjusting device providing a clock to the ADC and providing a phase error value to the interpolation filter.

The clock synchronizing apparatus may include a clock selection signal (SKIP / DUP) unit positioned between the interpolation filter and the FFT unit to update a clock through the timing adjusting device.

Furthermore, in order to achieve the above object, the present invention provides a clock synchronization acquisition method in an orthogonal frequency division multiplexing (OFDM) communication system, comprising: generating a clock and phase adjustment signal (Fraction-D) for the OFDM symbol; ; Obtaining a guard symbol interval start point of the OFDM symbol; And updating the clock and phase adjustment signals in the guard symbol period.

In the present invention, the clock synchronization acquisition method is characterized in that the clock has the same frequency as the sampling frequency of the transmitter, thereby minimizing power consumption in timing adjustment.

The clock synchronizing apparatus including the timing adjusting apparatus and the adjusting apparatus according to the present invention, and the clock synchronizing obtaining method using the adjusting apparatus can dramatically reduce power consumption by using the same clock frequency as the sampling frequency.

In addition, by updating the clock and phase adjustment signal in the guard symbol period, it is possible to minimize the ISI symbol interference to prevent the constellation of the FFT symbol from spreading, thereby improving the reception rate.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, when a component is described as being connected to another component, it may be directly connected to another component, but a third component may be interposed therebetween. In addition, in the drawings, the structure or size of each component is exaggerated for convenience and clarity of explanation, and parts irrelevant to the description are omitted. Like numbers refer to like elements in the figures. It is to be understood that the terminology used is for the purpose of describing the present invention only and is not used to limit the scope of the present invention.

3A is a schematic structural diagram of a clock synchronizing apparatus according to an embodiment of the present invention.

Referring to FIG. 3A, the clock synchronizing apparatus 1000 according to the present embodiment includes an analog-to-digital converter (ADC) 200, an interpolation filter 300, a hopping / copying unit 400, an FFT unit 500, and a clock error estimating unit. 600, a rope filter 700, and a timing adjusting device 100. Here, the clock 100a of the clock synchronizing device is generated by a clock generator (not shown) included in the timing adjusting device.

The analog-digital converter 200 converts the transmitted analog signal into a digital signal. In this case, the clock uses a clock generated by a clock generator (not shown) included in the timing adjusting device. The interpolation filter 300 samples the digital signal. The digital signal sampling by the interpolation filter 300 is performed by inputting a phase error value input from the timing adjusting device 100. The signal sampling process is repeatedly performed through a feedback process, so that a more accurate sampling process is performed. This makes it possible to extract the correct symbol signal accordingly. Here, the phase error value can be known through the phase adjustment signal in the timing adjusting device 100.

The hopping / copying unit 400 converts a phase by 360 degrees using a clock or a clock adjusting signal of the timing adjusting device 100. Conventionally, the hop / copy unit 400 performs a 180 degree phase shift by using a clock twice as fast, but the hop / copy unit 400 of the present embodiment uses a clock having the same frequency as the clock of the transmitter. Phase shift is also performed. On the other hand, since the jump / dup for adjusting the phase error of the constant part requires a proper clock selection, the clock selection signal is named as a clock selection signal. Name it.

The FFT unit 500 performs Fast Fourier Transfrom (FFT) on the sampled signal, and the clock error estimator 600 estimates the clock error of the signal output to the FFT unit. The estimated clock error is input to the timing adjusting device 100 again and used for clock timing adjustment. Meanwhile, the rope filter 700 is connected between the clock error estimator 600 and the timing adjusting device 100 to control the amplitude distortion of the signal.

On the other hand, the transmitter is shown schematically, the transmitter 2000 is generally provided with a transmitter 2100 for generating a digital signal, a digital-to-analog converter (DAC, 2200) for converting the digital signal into an analog signal. Meanwhile, the transmitter clock generated by the transmitter clock generator 2300 is used for analog signal conversion.

The clock synchronizing apparatus 1000 of the present embodiment adjusts clock timing by using a clock having the same frequency as the transmitter clock frequency, and thus has an advantage of significantly reducing power consumption of clock generation. On the other hand, as will be described later, in the clock synchronization device of the present embodiment, 360 phase shift should be performed according to the use of the same frequency clock, and the resulting phase change is generated only in the guard symbol period, thereby solving the problem of constellation spreading. Can be. That is, by updating the clock and phase adjustment signal only in the guard symbol period, the constellation is solved.

FIG. 3B is a structural diagram illustrating in detail the timing adjusting device in the clock synchronizing apparatus of FIG. 3A.

Referring to FIG. 3B, the timing adjusting device 100 includes a clock generating unit 100a, a phase adjusting signal generating unit 100b, and a clock and phase adjusting signal updating unit 100c. The clock generator 100a generates the same clock as the sampling frequency of the transmitter, and the phase adjust signal generator 100b generates the phase adjust signal Fraction-D. On the other hand, the clock and phase adjustment signal update unit 100c updates the clock and phase adjustment signals, and controls them to be updated only in the guard symbol period of the OFDM symbol.

Unlike the conventional embodiment, the phase adjusting signal operates in the range of -2 to 2, and more preferably operates in the range of -1.5 to 1.5 in order to reduce the error between the estimated sample of the interpolation filter and the sample of the transmission signal. In this way, by operating the phase adjustment signal to less than -1 or more than one, it is possible to update the phase adjustment signal only in the guard symbol period. In other words, the clock error, that is, the phase adjustment signal increases with time, and updates the phase adjustment signal when the portion corresponding to the guard symbol section is reached. Accordingly, the operation range of the phase adjustment signal may be greater than 1, thereby limiting the update period to the guard symbol period. Here, the phase adjustment signal is also used to define the phase change of 360 ° to 1.

FIG. 4 is a simulation picture showing a transition error occurring at a point where a transition is performed when the phase adjustment signal is updated in a jump / dup scheme.

Referring to FIG. 4, where A and B refer to the portions indicated in FIG. 3A, where AB (I) is the difference for the two signals I and AB (Q) is the difference for the Q signals for those two parts. Means. After performing Skip / Dup on such a signal, an enlarged picture is shown at the end. As you can see, a transition error occurs after executing Skip / Dup.

FIG. 5 is a simulation picture showing a result of performing FFT when a transition error occurs in a guard symbol section and an FFT section when performing a skip / dup using the same clock as the sampling period.

Referring to FIG. 5, when the phase adjustment signal is updated through the Skip / Dup method as shown in FIG. 4, a transition error necessarily occurs. However, the transition error is an output signal after the FFT according to the generated portion. There is a difference in quality.

That is, FIG. 5 shows the FFT output when the Skip / Dup is performed in the FFT symbol section and the guard symbol section. As shown in the last part of FIG. 5, when Skip / Dup is performed in the guard symbol section, there is no problem. When Skip / Dup is performed in the FFT symbol period, it can be seen that the signal is distorted much.

 6A and 6B are photographs showing constellation results after performing FFT when a transition error occurs in a guard symbol section and an FFT section.

6A and 6B represent the FFT output signal in FIG. 5 through constellations. As illustrated, when a transition error occurs in the FFT symbol section through Skip / Dup, that is, the constellations of FIG. 6B are severely spread. can confirm.

 This result can be seen as a natural result since only the FFT symbol period is performed during FFT and the FFT is not performed in the guard symbol period.

The feature of the timing adjustment according to the present invention will be briefly described again. In order to update the phase adjustment signal in the receiver, the receiver performs a clock having the same frequency as the sampling frequency of the transmitter. However, unlike the prior art which uses at least two types of 0/180 degree clocks, only one clock is used, so when the phase needs to be changed 180 degrees, 0/360 degree phase rotation occurs, resulting in phase error. Done.

Due to this phase error, the clock phase is shifted each time, and the sample sent by the transmitter and the sample sent by the receiver cause errors of about 7 to 17 samples. This phase change may occur anywhere, such as the FFT symbol section and the guard symbol section, when the phase adjustment signal (Fractional-D) exceeds 1 and returns to 0 again. If this phase change occurs in the FFT symbol period, the constellation spreads.

However, if the phase change occurs in the guard symbol section in which no FFT is performed, the constellation does not spread. That is, in general, there is interference between symbols at the end of the symbol and the first part of the next symbol or the first part of the guard symbol, and this section is a section that cannot be used when performing the FFT. Therefore, the timing adjustment signal is updated in this guard symbol section to prevent the constellation from spreading. As a result, the timing adjusting device according to the present invention updates the phase adjustment signal (Fraction-D) and the clock adjustment signal (SKIP / DUP), that is, the clock only in every guard symbol period, thereby preventing the constellation from spreading after performing the FFT. This can increase the signal reception rate accordingly.

On the other hand, if the phase adjustment signal is out of the range of -1.5 to 1.5, the error between the estimated sample through the interpolation filter and the sample of the transmission signal may become large. Therefore, the estimated range of the phase adjustment signal (Fraction-D) is changed at every guard symbol. Do not deviate between -2 and 2. Accordingly, it is preferable to allow the phase adjustment signal to operate in the range of -1.5 to 1.5.

7A and 7B are graphs exemplarily showing that there is an intersymbol interference at the start of the guard symbol.

As shown in FIGS. 7A and 7B, it can be seen that an Inter Symbol Interference (ISI) region occurs at the end of the symbol and the guard portion of the next symbol. The ISI waveforms of FIGS. 7A and 7B are exemplary, and the ISI generated between the end of the symbol and the guard portion of the next symbol may appear in various forms.

FIG. 8 is a graph showing a starting point of a guard symbol obtained by using a maximum likelihood estimation method.

Referring to FIG. 8, in order to update the aforementioned phase adjustment signal and clock only in the guard symbol period, finding the starting point of the guard symbol should be preceded. The method for finding a point at the start of the guard symbol uses a maximum likelihood estimation method as shown. Since the maximum likelihood estimation method is already known, a detailed description thereof is omitted.

9A and 9B are circuit diagrams for updating a clock and phase adjustment signal applied to a timing adjusting device of the present invention in a guard symbol period.

Referring to FIG. 9A, the circuit updates a clock and phase adjustment signal through a step code. Briefly, if the phase adjustment signal is in the guard symbol period, and the absolute value is greater than 1, 2 is subtracted from the phase adjustment signal (Fraction-D) and the clock (Skip / Dup). When the phase adjustment signal is in the guard symbol section and the absolute value is greater than zero, the phase adjustment signal and the clock are updated in the guard symbol section by subtracting 1 from the phase adjustment signal and the clock. On the other hand, if the phase adjustment signal exceeds one or more or less than -1 through such an update, the phase adjustment signal operates in the range of -1.5 to 1.5 by appropriately applying a step code, which is a phase shift signal, to compensate.

9B is an example of a circuit for updating a clock and phase adjustment signal without a step code. When the phase adjustment signal is in a guard symbol period and is larger than 1, the phase adjustment signal is subtracted by 2 from the clock and phase adjustment signal. If the signal is in the guard symbol period and is greater than 0.5, subtract one from the clock and phase adjustment signal.If the signal is in the guard symbol interval, and if it is less than -0.5, add one from the clock and phase adjustment signal. When the phase adjustment signal is in the guard symbol period and is less than 1, the clock and phase adjustment signals are updated by adding 2 to the clock and phase adjustment signals.

The circuits of FIGS. 9A and 9B are exemplary circuits for updating the clock and phase adjustment signal by limiting the guard symbol period, and the update method of the clock and phase adjustment signal of the present invention is not limited to the above circuit. .

10 is a graph showing the clock and phase adjustment signal waveform of the timing adjustment device according to the present invention.

As shown in Fig. 10, the phase adjustment signal operates in excess of 0 to 1, and the phase adjustment signal is updated only in the guard symbol section. Although the update of the phase adjustment signal on the graph is shown to be updated at a constant interval, it is generally updated only in the guard symbol section, so that the update interval is generally arbitrary. On the other hand, the clock shown in the lower portion has the same frequency as the sampling frequency sent from the transmitter as described above. Therefore, power consumption can be minimized in updating the phase adjustment signal.

On the other hand, since the update is performed only in the guard symbol section in which the FFT is not performed, a symbol having no constellation can be extracted. As a result, the reception rate can be significantly improved.

FIG. 11 is a flowchart illustrating a clock synchronization acquisition method according to another exemplary embodiment of the present invention, which will be described with reference to FIG. 3B for convenience of description.

Referring to FIG. 11, first, a clock and a phase adjustment signal are generated according to a symbol signal transmitted through the clock generation unit 100a and the phase adjustment signal generation unit 100b (S100). Next, the start point of the guard symbol interval for the transmitted symbol signal is obtained (S200). The starting point of the guard symbol interval may be obtained by using the maximum likelihood estimation method as described above. When the guard symbol section is found as described above, the clock and phase adjustment signals are limited to the guard symbol section and updated to perform phase adjustment (S300). The method of limiting the update of the clock and phase adjustment signal to the guard symbol period may be performed through the circuits of FIGS. 9A and 9B, but is not necessarily limited to such a circuit.

The timing adjusting device and the clock synchronizing device including the adjusting device according to the present invention are all OFDM employing OFDM schemes such as DAB Eureka 147, DVB-T, DVB-H, DMB-T / H, and IEEE 802.11a / g. It can be usefully used for efficient clock synchronization acquisition in the system.

While the present invention has been described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. will be. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

FIG. 1 is a graph illustrating a method of estimating a clock error through a structure of limiting a range of a conventional phase adjustment signal (Fraction-D) to [0, 1] and skipping / duplicate a sample.

FIG. 2 is a graph illustrating selecting an appropriate clock in a phase change part by using a multiclock in which a Skip / Dup is twice as fast as a sampling frequency in a conventional clock synchronizer.

3A is a schematic structural diagram of a clock synchronizing apparatus according to an embodiment of the present invention.

FIG. 3B is a structural diagram illustrating in detail the timing adjusting device in the clock synchronizing apparatus of FIG. 3A.

FIG. 4 is a simulation picture illustrating a transition error occurring at a point where a transition is performed when the phase adjustment signal is updated in a skip / dup method.

FIG. 5 is a simulation picture showing a result of performing FFT when a transition error occurs in a guard symbol section and an FFT section when performing a skip / dup using the same clock as the sampling period.

 6A and 6B are photographs showing constellation results after performing FFT when a transition error occurs in a guard symbol section and an FFT section.

7A and 7B are graphs exemplarily illustrating that there is an intersymbol interference at the start of the guard symbol.

FIG. 8 is a graph showing a starting point of a guard symbol obtained by using a maximum likelihood estimation method.

9A and 9B are circuit diagrams for updating a clock and phase adjustment signal applied to a timing adjusting device of the present invention in a guard symbol period.

10 is a graph showing the clock and phase adjustment signal waveform of the timing adjustment device according to the present invention.

11 is a flowchart illustrating a clock synchronization acquisition method according to another embodiment of the present invention.

Claims (24)

A clock generator for generating a clock equal to the sampling frequency of the transmitter; A phase adjustment signal generator for generating a phase adjustment signal (Fraction-D); And And a clock and phase adjustment signal updating unit which updates the clock and phase adjustment signal. The update of the clock and phase adjustment signal by the update unit is performed in a guard symbol period of an orthogonal frequency division multiplexing (OFDM) symbol. If you define a phase change of 360 ° as 1, In order to update the phase adjustment signal in a guard symbol period, And the phase adjustment signal operates between -2 and 2. delete The method according to claim 1, And the phase adjustment signal operates in a range of -1.5 to 1.5 to reduce an error between the estimated sample of the interpolation filter and the sample of the transmission signal. The method according to claim 1, And a starting point of a guard symbol of the OFDM symbol is obtained by using a maximum likelihood estimation method. The method according to claim 1, In the section of the guard symbol, The clock when the phase adjustment signal is greater than 1 or less than -1. And subtracts 2 from the phase adjustment signal, and the clock when the phase adjustment signal is from -1 to 1 or more. And subtracting one from the phase adjustment signal, thereby updating the clock and phase adjustment signal in the guard symbol period. 6. The method of claim 5, And updating the clock and phase adjustment signal by using a step code. The method according to claim 1, In the guard symbol section, If the phase adjustment signal is greater than 1, clock And Subtract 2 from the phase adjustment signal, The clock when the phase adjustment signal is greater than 0.5; And Subtract 1 from the phase adjustment signal, The clock when the phase adjustment signal is less than -0.5. And Add 1 by the phase adjustment signal, The clock when the phase adjustment signal is less than -1; And The clock is added by adding 2 to the phase adjustment signal. And And the phase adjustment signal is updated in the guard symbol section. 8. The method of claim 7, The clock And The updating of the phase adjustment signal is performed without using a step code which is a phase shift signal. An analog-to-digital converter (ADC) for converting the transmitted analog signal into a digital signal; An interpolation filter for sampling the digital signal; An FFT unit performing a fast Fourier transform (FFT) on the sampled signal; A clock error estimator for estimating a clock error with respect to the signal output to the FFT unit; A rope filter controlling amplitude distortion on the signal output from the clock error estimator; And A timing adjuster providing a clock to the ADC and providing a phase error value to the interpolation filter; The timing adjusting device A clock generator for generating a clock equal to the sampling frequency of the transmitter; A phase adjustment signal generator for generating a phase adjustment signal (Fraction-D); And And a clock and phase adjustment signal updating unit which updates the clock and phase adjustment signal. The update of the clock and phase adjustment signal by the update unit is performed in a guard symbol interval of an orthogonal frequency division multiplexing (OFDM) symbol. If you define a phase change of 360 ° as 1, In order to update the phase adjustment signal in a section of the guard symbol, And the phase adjust signal is operated between -2 and 2. The method of claim 9, And a clock adjustment signal (SKIP / DUP) unit positioned between the interpolation filter and the FFT unit to update a clock through the timing adjustment device. delete The method of claim 9, The starting point of the guard symbol of the OFDM symbol is obtained by using a maximum likelihood estimation method. The method of claim 9, In the section of the guard symbol, The clock when the phase adjustment signal is greater than 1 or less than -1. And Subtract 2 from the phase adjustment signal, and if the phase adjustment signal is from -1 to 1, the clock and The clock is subtracted by subtracting 1 from the phase adjustment signal. And And updating the phase adjustment signal in the guard symbol section. The method of claim 9, In the section of the guard symbol, If the phase adjustment signal is greater than 1, clock And Subtract 2 from the phase adjustment signal, The clock when the phase adjustment signal is greater than 0.5; And Subtract 1 from the phase adjustment signal, The clock when the phase adjustment signal is less than -0.5. And Add 1 by the phase adjustment signal, The clock when the phase adjustment signal is less than -1; And The clock is added by adding 2 to the phase adjustment signal. And And updating the phase adjustment signal in the guard symbol section. A method of acquiring clock synchronization in an orthogonal frequency division multiplexing (OFDM) communication system, Generating a clock and phase adjustment signal (Fraction-D) for the OFDM symbol; Obtaining a guard symbol interval start point of the OFDM symbol; And And updating the clock and phase adjustment signals in the guard symbol period. If you define a phase change of 360 ° as 1, In order to update the phase adjustment signal in a guard symbol period, And the phase adjustment signal operates between -2 and 2. The method of claim 15, And the clock has a frequency equal to the sampling frequency of the transmitter. delete The method of claim 15, The start point of the guard symbol of the OFDM symbol is obtained by using a maximum likelihood estimation method. The method of claim 15, The starting point of the guard symbol is obtained by obtaining the starting point of the guard symbol, When the phase adjustment signal is greater than 1 or less than -1 in the guard symbol period, the clock And Subtract 2 from the phase adjustment signal, and if the phase adjustment signal is from -1 to 1, the clock And The clock is subtracted by subtracting 1 from the phase adjustment signal. And And updating the phase adjustment signal in the guard symbol section. The method of claim 15, In the section of the guard symbol, If the phase adjustment signal is greater than 1, clock And Subtract 2 from the phase adjustment signal, The clock when the phase adjustment signal is greater than 0.5; And Subtract 1 from the phase adjustment signal, The clock when the phase adjustment signal is less than -0.5. And Add 1 by the phase adjustment signal, The clock when the phase adjustment signal is less than -1; And The clock is added by adding 2 to the phase adjustment signal. And And updating the phase adjustment signal in the guard symbol section. delete delete delete delete

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