KR101104917B1 - Circuit for processing gray scales of electric sign board - Google Patents

Abstract

PURPOSE: An electric signboard capable of increasing a gradation bit in a driving IC by a PWM(Pulse Width Modulation) scanning is provided to implement a high image quality by expressing a gradation of a high bit through a gradation processing circuit of a low bit. CONSTITUTION: A signal processing unit converts 8 bit gradation image input data into 16 bit gradation image data. A timing control logic(20) generates a gradation clock signal. A gradation bit converting logic(10) converts the 16 bit gradation image data into 12 bit gradation signal of the PWM method to be divided into 32 sections and outputs the converted gradation data. A PWM type gradation driver IC turns on the pixel of an LED unit by processing the 12 bit gradation image data from a parallel to serial converter.

Description

Circuit for Processing Gray Scales of Electric Sign Board with pulse width modulation (PWM) distributed scanning

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an electronic board that increases gradation bits in a driving IC by pulse-width modulation (PWM) distributed scanning. More specifically, a new pulse-width modulation (PWM) that allows the use of low-bit grayscale processing circuits to display high-bit grayscales, resulting in relatively high resolution using relatively simple and inexpensive hardware circuitry. The present invention relates to an electronic display board that increases gradation bits in a driving IC by distributed scanning.

Recently, with the development of image technology, commercialization of high-definition broadcasting such as HDTV broadcasting has been realized. In the case of an outdoor display board, an apparatus capable of processing high-quality and high-quality digital video signals is required.

In the image display of the electric signboard, the uniform brightness and chromaticity are reproduced in the same brightness and chromaticity data, so that there are no spots, the density of pixels is increased to realize high resolution image quality, and furthermore, the number of gradation levels is realized by high quality. There is a technical need to be able to provide an electronic sign.

In order to implement the gradation level, a gradation driver IC using a pulse width modulation (PWM) method has been developed and commercially available. There are many types of gradation driver ICs available on the market, ranging from 8-bit gradation to 16-bit gradation.The 8-bit gradation driver IC enables to express gradation over 256 levels of gradation levels, which are 8 powers of 2. The IC can express gradation over gradation levels of 65,536 steps, which is 16 in two. Therefore, the higher the bit, the faster the number of gradation levels, thus enabling higher gradation image processing.

However, a relatively high bit gray scale driver IC has a higher component price than a low bit gray scale driver IC, thereby causing an increase in the manufacturing cost of an electronic board. For example, a price increase of about 7% could occur when 1 bit is added. Furthermore, there was a limit that it was not possible to express gradation of a higher number of bits than the gradation of the number of bits sold. For example, since the highest bit gray scale driver IC is a 16 bit gray scale driver IC, higher gray scale expression is not possible.

Therefore, in the field of high quality image processing of electronic display panels, there is still a need for a new electronic display gradation processing technology that enables free expression of gradations without being limited to commercially available components without increasing the manufacturing price of electronic displays.

An object of the present invention is to invent and improve the above-described gray scale processing technology of the image display and to provide various additional advantages, it is possible to express a high bit gray scale using a low bit gray scale processing circuit. The present invention provides an electronic display board that increases grayscale bits in a driver IC by pulse width modulation (PWM) distributed scanning, which enables relatively high image quality by using a relatively simple and inexpensive hardware circuit.

According to an embodiment of the present invention, there is provided an electronic board for increasing grayscale bits in a driving IC by pulse width modulation (PWM) distributed scanning, the signal processing unit converting 8-bit grayscale image input data into 16-bit grayscale image data; Timing control logic to generate a gradation clock signal; The 16-bit grayscale image data input from the signal processor is separated into upper bits of the 11-bit grayscale and the remaining lower 5 bits, which are one step lower than the 12-bit grayscale, which is the gray scale capability of the driving IC, to separate the 16-bit grayscale image data of the driving IC. In order to adapt to the gradation capability, the upper 11 bits and the lower 5 bits are divided into 32 sections which are 5 bits in time and space, and the gradation data which is converted into 12 bits by outputting the lower 11 bits to the upper 11 bits and the data value is converted to 12 bits. Bit conversion logic; A parallel-to-serial converter for converting parallel 12-bit gradation image data output from the gradation bit conversion logic into serial 12-bit gradation image data corresponding to a driving IC; It includes a PWM type gray scale driver IC for processing the 12-bit grayscale image data output from the parallel-to-serial converter to turn on the pixel of the LED display, the gray scale bit data beyond the capability of the driving IC for the target image gray bit Is divided into space-time and distributedly arranges the gray-bit that is lacking in the divided space-time to achieve gradation above the driving IC capability.
The gradation bit conversion logic may include: ID0 to ID15, which are 16-bit grayscale image input data, are divided into 11 bits by selecting ID5 to ID15, the upper digits of the digits, and output as D0 to D10, and the remaining ID0 to ID4 are output to AD0 to AD4. Separation and conversion circuits; A pulse insertion order converting circuit for generating a scan address signal having the same number of bits as the lower bit data AD0 to AD4 from the control signal input from the timing control logic and outputting the same as the comparison data BD0 to BD4; Compare the lower bit data AD0 to AD4 output from the data separation and conversion circuit with the comparison data BD0 to BD4 output from the pulse insertion order conversion circuit, and generate the insertion data P according to the comparison result. An output comparator circuit; And an adder circuit for adding the 11-bit converted data D0 to D10 output from the data separation and conversion circuit 11 to the inserted data P output from the comparator and outputting 12-bit image grayscale data. It features.
In addition, the data separation and conversion circuit inputs '0' to the most significant bit MSB D11 of the conversion data D0 to D10 in order to prevent the rounding number from being generated by the insertion data P and smaller than the actual data. Characterized in that.
In addition, since the BCD maximum value is 31 when the 32 sections, which are the lower five bits corresponding to the inserted data, are space-time-divided, one dummy section is added to match 32 PWM cycle sections.
The pulse insertion order converting circuit is characterized in that the data order is distributed randomly or alternately when converting the generated scan address signal to comparative data in order to reduce flicker in the lower bits.

delete

delete

delete

delete

According to the present invention, a high bit gray level can be expressed using a low bit gray level processing circuit, so that a relatively high resolution can be realized using a relatively simple and inexpensive hardware circuit.

Accordingly, it is possible to provide an electronic display board that can freely express high-quality gradation desired without being limited to the performance of components without increasing the manufacturing cost of the electronic display board.

1 and 2 are conceptual diagrams for explaining the operation of a general 16-bit gradation driver IC.
Fig. 3 is a conceptual diagram for explaining a concept of division of 32 divisions of 5 bits, which are 5 powers of two.
4 is a conceptual diagram illustrating a concept of distributedly inserting bits in a gray scale processing circuit according to an embodiment of the present invention.
5 is a block diagram showing the overall configuration of a gray scale gray scale processing circuit according to an embodiment of the present invention.
FIG. 6 is a block diagram showing details of a gradation bit conversion logic circuit in the configuration shown in FIG. 5; FIG.
FIG. 7 is a schematic diagram for explaining an operation of a data separation and change circuit of the gradation bit conversion logic circuit shown in FIG. 6; FIG.
8 is a schematic diagram for explaining the operation of the pulse insertion order conversion circuit of the gradation bit conversion logic circuit shown in FIG.
9 is a schematic diagram for explaining the operation of timing control logic in the configuration shown in FIG.

Hereinafter, with reference to the accompanying drawings illustrating the present invention with a specific example as follows.

Gray scale processing circuit of the electronic display board provided in accordance with the present invention is PWM dispersion The scanning method is applied to enable the same gray level expression as that using the high bit gray scale drive IC while using the low bit gray scale drive IC.

In general, as the gradation bit increases, the image may be reproduced more smoothly with improved contrast. Furthermore, the flicker phenomenon of the image caused by the long blank period during PWM control can be reduced. On the other hand, an electronic board using a dynamic module has a problem that scan line noise or screen flicker due to scanning occurs when the line of sight moves quickly. To solve this problem, the screen is reproduced by faster and faster scanning. The frequency needs to be increased, in which case one PWM cycle is shortened, making it difficult to improve many gradations. According to the present invention, the gradation can be improved even in the case of such a dynamic display board.

Hereinafter, according to the present invention, a specific embodiment for implementing 16-bit gradation using a 12-bit gradation driver IC when the frame rate is 60 frames / second will be described, but the embodiment will be described. It is not limited to this.

In the past, a 16-bit gray scale driver IC was used to process 16-bit gray scales using a PWM method. 16-bit gradation processing refers to subdividing the level of the lightest gradation level from the darkest gradation level into 16 powers of 2, that is, 65,536 gradation levels. 1 illustrates a correlation between a vertical synchronization signal supplied to a 16-bit gray scale driver IC and a gray clock signal GSCLK, and FIG. 2 illustrates a correlation between GSCLK and gray data (GS data). When the frame rate is 60 frames / sec, the LED is a light emitting device by dividing the vertical synchronization signal section of 60 Hz into 16 bits, that is, 65,536 sections, and by dividing gradation data based on the subdivided sections. By expressing contrast. Therefore, 65,536 gradation clock pulses for PWM control are also required. In this specification, the term section refers to a time section unless otherwise specified.

According to the present invention, when 16-bit gradation is applied using a 12-bit gradation driver IC, there is a situation in which 4 bits are insufficient in the performance that the gradation driver IC can process. Therefore, the present invention implements a target 16-bit gradation by inserting gradation data set when the 12-bit gradation driver IC normally operates within the set virtual section after setting the virtual section corresponding to the insufficient 4 bit number. Use

By the way, in the case of actually using in the form of insertion by 12 bit gradation + 4 bit division, in the case of binary number (111 111 111 111) in which each bit is all 1 in the normal gradation data of the 12 bit gradation driver IC, 1 bit by division If is added, the rounding number is generated and becomes a binary number (000 000 000 000), which is all zeros, and thus an error in which the LED does not light despite the brightest gray scale data occurs.

Therefore, in the present invention, the 12-bit gradation driver IC is used as an 11-bit gradation driver IC, sets 32 virtual sections of 5 bits, that is, 5 powers, which are the remaining shortages, and inserts the normal gradation data into each virtual section. In other words, hardware uses 12-bit gray scale driver IC, but logically, 11-bit gray scale driver IC is used to set 16-bit gray scale by setting 5 bit virtual section.

FIG. 3 shows that one frame section is divided into 5 bits, that is, 32 virtual sections, and then 2049 GSCLKs are allocated and 2048 gradation levels are inserted in each virtual section. As shown, the 2048 gradation levels consist of 11 bits of gradation, that is, 2047 gradation levels and one gradation level inserted, which are distributedly inserted every 32 PWM cycles and subtract one dummy gradation, 16 bits, or 65536 gray levels, may be implemented.

In this case, 11 bits are upper bits and 5 bits of the divided virtual section may be generated based on the lower bits. The dummy gradation level refers to a gradation section generated as an extra 1 PWM cycle period because the maximum BCD value of the lower 5 bits excluding the upper 11 bits among the extended 16 bit gradation levels is 31.

4 illustrates a bit distributed insertion concept in accordance with the present invention. 5 bits, or 32 gray scale data, are distributed and inserted by 1 gray pulse in each PWM cycle of 32 scan intervals. At this time, one PWM cycle section (32th section in the drawing) is left blank without inserting data. This arrangement of distributed arrangements reduces flicker in low gradations.

5 and 6 show an example of a circuit configuration for implementing gradation bit extension according to the present invention. The gradation processing circuit 1 shown in FIG. 5 includes a signal processing section 2, a parallel to serial converter 3, a gradation driver IC 4 of a PWM method, and an LED display 5 In particular, the grayscale bit conversion logic 10 and the timing control logic 20 may be included.

The signal processor 2 processes red, blue, and green signals of the image signals displayed on the LED display 5 constituting the screen of the electronic display and generates grayscale data. In the illustrated example, the signal processor 2 processes an 8-bit input image signal to generate desired 16-bit grayscale data, and uses the same to process luminance corresponding to each color signal, that is, to display the grayscale.

The parallel to serial converter 3 is a device for converting parallel signals into serial signals, and the PWM type gray scale driver IC 4 is a 12-bit gray scale driver IC in this embodiment.

The gradation bit conversion logic 10 is provided for each of red, green, and blue colors, has the same configuration for each color, and a detailed internal configuration is shown in FIG. The 16-bit gradation signal is input to the gradation bit conversion logic 10, and is a logic for converting the 16-bit gradation signal into a 12-bit gradation signal (11 bits + 1 bit addition) of a PWM system divided into 32 sections.

The timing control logic 20 receives a vertical synchronization signal and provides a control signal based on the vertical synchronization signal. In particular, the timing control logic 20 includes a counter for providing a gray scale clock signal GSCLK and a frequency dividing counter for distributing 32 PWM cycles.

Referring to FIG. 6, the gradation bit conversion logic 10 may include a data separation and conversion circuit 11, a pulse insertion order conversion circuit 13, a comparator circuit 15, and an adder circuit 17. have.

As shown in Fig. 7, the data separation and conversion circuit 11 separates the high-bit or 16-bit input grayscale data ID input from the signal processing unit 2 for processing the color signal of the video signal, and The upper bits, that is, the upper 11 bits, are converted and output as low-bit, 11-bit converted data D, and the lower bits, that is, the lower 5 bits, are output as the lower bit data AD. The data separation and conversion circuit 11 puts the upper 11 bit IDs 15 to 5 of the input grayscale data into the conversion data D 10 to 0, and puts "0" in the MSB D 11. Inserting "0" into the MSB D 11 causes an overflow when the insertion data "1" from the comparator circuit 15 is added when the upper bits of the input data are all "1", and thus the data is all "." This is to prevent a case where an error of 0 "is turned off and a pixel is turned off occurs.

The comparator circuit 15 is a 5-bit low-bit data AD AD 4 to 0 output from the data separation and conversion circuit 11 and a 5-bit scan address output from the pulse insertion order conversion circuit 13, i.e. Comparison data BD The BDs 4 to 0 are sequentially compared 32 times, and 32 single gray scale insertion data P are generated and output according to the comparison result. An example of the VHSL hardware description language (VHDL) of the comparison logic used in the comparator circuit 15 is as follows. In other words, if the 5 bit low-bit data is larger than the comparison data, '1' is inserted into the inserted data, and if it is small, '0' is inserted.

P <= '1' when (AD (4 ~ 0)> BD (4 ~ 0)) else '0'

The pulse insertion order converting circuit 13 generates a scan address signal SA having the same number of bits as the lower bit data AD, i.e., 5 bits, from the control signal inputted from the timing control logic 20, that is, the gradation clock signal, As intuitively shown in FIG. 8, this is distributed as comparison data BD and then output. The reason for this dispersion is to eliminate the flicker phenomenon as mentioned above.

The adder circuit 17 adds the converted data D outputted from the data separation and conversion circuit 11 to the inserted data P output from the comparator 15 and outputs it as display data CD. do. This output display data CD is used by the 12-bit gradation driver IC 4 after passing through the parallel-to-serial converter 4 to implement 16-bit gradation.

9 shows a time chart of the timing control logic 20. In this embodiment, the frame rate is 60 frame / sec, and the refresh rate is 60 frame / sec? 32 cycles / frame = 1.92 kHz. The red, green, and blue color data are each 16 bits, and the gray scale driver IC used is a 12-bit PWM gray scale driver, and the gray scale bits actually used are used as 11-bit PWM drivers.

In this case, the setting of the gradation clock GSCLK is as follows. The condition that the first GSCLK> screen refresh rate ㅧ (2 ^N +1) must be satisfied. In this embodiment, 1.92 kHz ㅧ (2 ¹¹ +1) = 3.94 MHz, so that the number of clocks in one PWM cycle is (4 MHz / 60 Hz) / 32 Interval = 2083 clocks. The condition that the second GSCLK count number <(2 ^N +1) + control signal must be satisfied. (2 ¹¹ +1) + 34 = 2083 clock, and all are satisfied because GSCLK is 2049 within 1 address period.

Also included in the timing control logic 20 is a 32 PWM Cycle dividing counter. The division counter may be a BCD counter that divides the vertical synchronization signal period by 32 in units of 2083 clocks in synchronization with the vertical synchronization signal. This BCD counter generates a 5-bit scan address signal SA (4 to 0) and passes it to the gradation bit conversion logic 10 for PWM cycle decoding. At this time, 2049 clocks are counted and sent as GSCLK in one address period.

As described above, the present invention is not limited to the function of the component (IC) modeled by hardware, but introduces a temporal concept so that the upgraded function can be exhibited rather than the inherent function of the part.

In recent years, as a side effect of commercialization of HDTV, consumer demand for electronic display boards is increasing and manufacturing cost is required to satisfy these requirements, but according to the present invention, high-quality images can be realized by control technology without cost increase.

Imaging technology and data transmission technology are expected to be further developed in the future, but parts that continuously increase gradation bits may not be developed in a timely manner. However, according to the present invention, it is possible to freely display high-quality gray scales regardless of the development of such components.

In the above, the present invention has been described through specific embodiments, but those skilled in the art can refer to and combine various features described in the present disclosure, and various and modified construction methods are possible. Although the present invention has been described with reference to an embodiment of expressing 16-bit grayscale using a 12-bit grayscale driver IC, increasing the number of lower bits also enables 17-bit grayscale and 18-bit grayscale. Therefore, it should be pointed out that the scope of the present invention should not be limited to the described embodiments, but should be interpreted by the appended claims.

1: gradation processing circuit
2: signal processing unit
3: parallel-serial converter
4: 12-bit gradation driver IC
5: LED indicator
10: gradation bit conversion logic
11: data separation and conversion circuit
13: pulse insertion order conversion circuit
15: comparator circuit
17: adder circuit
20: Timing Control Logic

Claims (5)

A signal processor for converting 8-bit grayscale image input data into 16-bit grayscale image data;
Timing control logic to generate a gradation clock signal;
The 16-bit grayscale image data input from the signal processor is separated into upper bits of the 11-bit grayscale and the remaining lower 5 bits, which are one step lower than the 12-bit grayscale, which is the gray scale capability of the driving IC, to separate the 16-bit grayscale image data of the driving IC. In order to adapt to the gradation capability, the upper 11 bits and the lower 5 bits are divided into 32 sections which are 5 bits in time and space, and the gradation data which is converted into 12 bits by outputting the lower 11 bits to the upper 11 bits and the data value is converted to 12 bits. Bit conversion logic;
A parallel-to-serial converter for converting parallel 12-bit gradation image data output from the gradation bit conversion logic into serial 12-bit gradation image data corresponding to a driving IC; And
It includes a PWM (Pulse Width Modulation) type gray scale driver IC for processing the 12-bit grayscale image data output from the parallel-to-serial converter to turn on the pixel of the LED display, and the driving IC for the target image gray bit An electronic board that increases gradation bits in a driver IC by pulse width modulation (PWM) distributed scanning, which divides gradation bit data beyond capability into space-time and distributes gradation bits insufficient in the divided space-time to achieve gradation above the driving IC capability. The method of claim 1, wherein the gradation bit conversion logic is:
A data separation and conversion circuit for selecting 16 bits of gradation image input data ID0 to ID15, selecting ID5 to ID15, which are upper order digits, and dividing them into 11 bits to output D0 to D10, and outputting remaining ID0 to ID4 to AD0 to AD4; A pulse insertion order converting circuit for generating a scan address signal having the same number of bits as the lower bit data AD0 to AD4 from the control signal input from the timing control logic and outputting the same as the comparison data BD0 to BD4; Compare the lower bit data AD0 to AD4 output from the data separation and conversion circuit with the comparison data BD0 to BD4 output from the pulse insertion order conversion circuit, and generate the insertion data P according to the comparison result. An output comparator circuit; And an adder circuit for adding the 11-bit converted data D0 to D10 output from the data separation and conversion circuit 11 to the inserted data P output from the comparator and outputting 12-bit image grayscale data. An electronic board for increasing gradation bits in a driving IC by pulse width modulation (PWM) distributed scanning. The data separation and conversion circuit of claim 2, wherein the data separation and conversion circuit generates a '0' in the most significant bit (MSB) D11 of the conversion data D0 to D10 in order to prevent the rounding number from being generated and becomes smaller than the actual data. An electronic board for increasing gradation bits in a driving IC by pulse width modulation (PWM) distributed scanning. 3. The method of claim 2, wherein when the 32 subsections, which are the lower 5 bits corresponding to the inserted data, are space-time-divided, the maximum value of BCD is 31, thereby adding 32 dummy cycle sections to fit 32 PWM cycle sections. An electronic board that increases gradation bits in a driving IC by pulse width modulation (PWM) distributed scanning. The method of claim 2, wherein the pulse insertion order converting circuit randomly or alternately distributes the data order when converting the generated scan address signal to the comparative data to reduce the flicker in the lower bits. An electronic board that increases gradation bits in a driving IC by pulse width modulation (PWM) distributed scanning.

Images