KR101102036B1 - Analog buffer and liquid crystal display apparatus using the same and driving method thereof - Google Patents

Abstract

The present invention provides an analog buffer, a liquid crystal display using the same, and a driving method thereof, which can reduce power consumption and prevent image quality errors.

An analog buffer according to the present invention is an analog buffer for buffering an input voltage from an input line to an output line, comprising: a comparator comprising an inverter connected in series with the input line; A feedback switch connected between the input line and the output line; A charge switch connected between said output line and a common voltage source to form a closed loop; Connected between the comparator and the output line to precharge the output line to the common voltage of the common voltage source by the closed loop in a reset period, wherein the precharged voltage is fed back to the input line through the feedback switch in a feedback period And an output inverter which cuts off the first and second driving voltage sources when converged to the input voltage.

Description

ANALOG BUFFER AND LIQUID CRYSTAL DISPLAY APPARATUS USING THE SAME AND DRIVING METHOD THEREOF}             

1 is a view schematically showing a conventional liquid crystal display device.

2 is a conventional analog buffer circuit diagram.

FIG. 3 is a driving waveform diagram of the buffer shown in FIG. 2.

4 is an analog buffer circuit diagram according to an embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of the comparator shown in FIG. 4.

FIG. 6 is a detailed circuit diagram of the inverter shown in FIG. 5.

FIG. 7 is a detailed circuit diagram of the third inverter shown in FIG. 4.

FIG. 8 is a driving waveform diagram of the buffer shown in FIG. 4.

9 is a diagram illustrating a driving waveform and an output according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

2r: liquid crystal panel 4r: gate driver

6r: data driver 8r: timing controller

10r: gamma voltage generator

1, 8, 9, 10, 11, SW1, SW2, SW3, SW-Vcom: switch

2, 4, 6, C1,: Capacitor

3, 5, 7, 24, 26: inverter

20, 22: comparator

PT, PT1, PT2: P-type thin film transistor

NT, NT1, NT2: N-type thin film transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog buffer, and more particularly, to an analog buffer capable of reducing power consumption and preventing image quality errors, and a liquid crystal display using the same, and a driving method thereof.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal panel having a pixel matrix and a driving circuit for driving the liquid crystal panel.

Specifically, as shown in FIG. 1, the liquid crystal display includes a liquid crystal panel 2r having a pixel matrix, a gate driver 4r for driving gate lines GL1 to GLn of the liquid crystal panel 2r, A data driver 6r for driving the data lines DL1 to DLm of the liquid crystal panel 2r, and a timing controller 8r for controlling the driving timing of the gate driver 4r and the data driver 6r. do.

The liquid crystal panel 2r includes a pixel matrix composed of pixels 12r formed at respective regions defined by intersections of the gate lines GL and the data lines DL. Each of the pixels 12r includes a liquid crystal cell Clc for adjusting light transmittance according to a pixel signal, and thin film transistors TFT for driving the liquid crystal cell Clc.

The thin film transistor TFT is turned on when the gate driving signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the video signal from the data line DL to the liquid crystal cell Clc. . The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the video signal charged in the liquid crystal cell Clc.

The liquid crystal cell Clc is equivalently represented by a capacitor and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT. The liquid crystal cell Clc further includes a storage capacitor (not shown) so that the charged video signal is stably maintained until the next video signal is charged. The liquid crystal cell Clc realizes gradation by adjusting light transmittance by changing an arrangement state of liquid crystals having dielectric anisotropy according to a video signal charged through the thin film transistor TFT.

The liquid crystal panel 2r is driven by an inversion method of inverting the polarity of the liquid crystal cell Clc by a predetermined unit using a data signal in order to prevent degradation of the liquid crystal and to improve display quality. In Inversion method, Frame Inversion, in which the polarity of the liquid crystal cell is inverted in units of frames, Line Inversion, in which the polarity of liquid crystal cells are inverted in units of horizontal lines, and Liquid crystal cells in units of vertical lines. Column Inversion, the polarity of which is inverted, and Dot Inversion, in which the polarity of the liquid crystal cell is inverted in units of liquid crystal cells, are used. Among these, the line inversion method of inverting the polarity of the liquid crystal cell in horizontal line units is advantageous in terms of power consumption compared to the column inversion and dot inversion methods. This is because the column and dot inversion methods require polarity inversion using only the data signal, whereas the driving voltage range of the data signal is relatively large, whereas the line inversion method is supplied with the data signal to the liquid crystal cell Clc as a reference voltage. This is because the driving voltage range of the data signal can be lowered by alternatingly driving the common voltage Vcom.

The gate driver 4r shifts the gate start pulse GSP from the timing controller 8r according to the gate shift clock GSC to sequentially gate the gate lines GL1 to GLm. Supply a scan pulse of high voltage (VGH). The gate driver 4r supplies the gate low voltage VGL to the gate lines GL in the remaining periods during which the scan pulse of the gate high voltage VGH is not supplied.

The data driver 6r generates a sampling signal by shifting the source start pulse SSP from the timing controller 8r according to the source shift clock SSC. In addition, the data driver 6r latches the video data RGB input according to the source shift clock SSC according to the sampling signal and then line-by-line in response to a source output enable (SOE) signal. To supply. The data driver 6r converts the digital video data RGB, which is supplied in units of lines, into analog video signals using different gamma voltages supplied from the gamma voltage generator, and supplies them to the analog video signals DL1 through DLm. Here, the data driver 6r determines the polarity of the video signal in response to the polarity control signal POL from the timing controller 8r when converting the video data into the video signal.

The timing controller 8r generates a gate start pulse GSP and a gate shift clock GSC for controlling the gate driver 4r, and a source start pulse SSP and a source shift clock for controlling the data driver 6r. (SSC), source output enable signal SOE, polarity control signal POL, and the like. In this case, the timing controller 8r transmits a data enable (DE) signal, a horizontal sync signal (Hsync), a vertical sync signal (Vsync), and pixel data (RGB) indicating a valid data section input from the outside. Control signals such as the GSP, GSC, GOE, SSP, SSC, SOE, and POL are generated by using a dot clock (DCLK) that determines timing.

In such a liquid crystal display device, the data driver 6r includes an analog buffer for preventing the video signal supplied to the data line from being distorted in accordance with the RC load amount of the data line. The gate driver 4r also includes an analog buffer to prevent the gate driving signal supplied to the gate line from being distorted according to the RC load amount of the gate line. In general, an amplifier (OP-AMP) is mainly used as an analog buffer, but recently, a scheme for simplifying a circuit configuration using an inverter or the like has been proposed.

For example, the analog buffer disclosed by PP21-24 of "AMLCD '02" in Toshiba uses three inverters as shown in FIG. The analog buffer shown in FIG. 2 is an input terminal of each of the first to third inverters 3, 5 and 7 and the first to third inverters 3, 5 and 7 connected in series between the input line and the output line. First to third capacitors 2, 4, and 6 respectively connected in series to the first switch, first switch 1 for supplying an input voltage Vin connected between the input line and the first capacitor 2, and For the feedback connected between the input line and the output line, and the second to fourth switches 8, 9, and 10 respectively connected between the input and output terminals for the initialization of the first to third inverters 3, 5, and 7 respectively. The fifth switch 11 is provided.

First, the first to fourth switches 1, 8, 9, and 10 are turned on in response to the first control signal CS1 supplied as shown in FIG. 3 in the reset period RESET. Accordingly, each of the first to third inverters 3, 5, and 7 is shortened by the input / output terminal and initialized to an inverter logic threshold voltage (hereinafter, VTH) which is an intermediate voltage of the power supply voltage. Accordingly, each of the first to third capacitors 2, 4, and 6 connected to the input terminal of each of the first to third inverters 3, 5, and 7 is charged with a difference voltage between the input voltage Vin and VTH. .

Subsequently, in the feedback period FEEDBACK, the fifth switch 11 for feedback is turned on by the second control signal CS2 supplied as shown in FIG. 3 so that the output voltage Vout corresponding to the input voltage Vin is increased. Monitored at the output line. In other words, when the fifth switch 11 is turned on and the feedbacked output voltage Vout is higher than the input voltage Vin, since the input voltage Vin is higher than VTH, the first to third inverters 3 and 5 , 7) lowers the output voltage Vout. On the contrary, when the feedback output voltage Vout is lower than the input voltage Vin, since the input voltage Vin is lower than VTH, the first to third inverters 3, 5, and 7 increase the output voltage Vin. . As described above, the first to third inverters 3, 5, and 7 undergo an oscillation process in which the output voltage Vout rises and falls repeatedly at the beginning of the feedback period FEEDBACK. To converge.

This analog buffer can be implemented using a simpler configuration than the conventional analog buffer using an amplifier (OPAMP) by using only an inverter. However, in the analog buffer shown in FIG. 2, since the third inverter 7 of the output terminal needs to drive the data line DL having the large capacitance C, the size is large and the output voltage Vout is the input voltage Vin. The power consumption is high because VTH is always maintained even after convergence.

Accordingly, an object of the present invention is to provide an analog buffer, a liquid crystal display device using the same, and a driving method thereof capable of reducing power consumption and preventing image quality errors.

In order to achieve the above object, an analog buffer according to the present invention comprises an analog buffer for buffering an input voltage from an input line to an output line, comprising: a comparator comprising an inverter connected in series with the input line; A feedback switch connected between the input line and the output line; A charge switch connected between said output line and a common voltage source to form a closed loop; Connected between the comparator and the output line to precharge the output line to the common voltage of the common voltage source by the closed loop in a reset period, wherein the precharged voltage is fed back to the input line through the feedback switch in a feedback period And an output inverter which cuts off the first and second driving voltage sources when converged to the input voltage.

The comparator includes a plurality of inverters connected in series between the input line and the output inverter; A capacitor connected in series with the input of the inverter; And an initialization switch for initializing the inverter to the input / output terminal connection in the reset period.

And an input switch for supplying the input voltage to the input line in the reset period.

The output inverter comprises first and second transistors connected between the comparator and the output line to constitute an inverter; A third transistor connected between a supply line of the first driving voltage source and the first transistor and controlled by a first control signal; And a fourth transistor connected between the supply line of the second driving voltage source and the second transistor and controlled by a second control signal.

The first and third transistors are PMOS transistors, and the second and fourth transistors are NMOS transistors.

The output inverter is characterized in that the output of the output inverter is in a high impedance state by turning off the third transistor and the fourth transistor by the first and second control signals in the reset period.

The output inverter turns off the third and fourth transistors according to the first and second control signals supplied to the input line in the reset period to precharge the output line to the common voltage source, and the feedback period. And turn on the first and third transistors so that the voltage on the output line is charged by the first driving voltage source and converges to the input voltage.

And a second capacitor connected between the feedback switch and the input line, wherein the output voltage of the output line is adjusted by the ratio of the capacitor and the second capacitor.

The common voltage source may be configured to precharge the output line by using the common voltage driven by AC.

A liquid crystal display according to the present invention comprises: a comparator comprising an inverter connected in series with an input line; A feedback switch connected between the input line and the output line; A charge switch connected between said output line and a common voltage source to form a closed loop; Connected between the comparator and the output line to precharge the output line to the common voltage of the common voltage source by the closed loop in a reset period, wherein the precharged voltage is fed back to the input line through the feedback switch in a feedback period An analog buffer having an output inverter for blocking the first and second driving voltage sources when converged to the input voltage from the input line, and a data driver for driving the data lines of the pixel matrix; And a gate driver for driving the gate lines of the pixel matrix, wherein at least one of the data driver, the gate driver, and the common voltage source includes the analog buffer.

The data driver supplies a data signal that is polarized inversion to the data line in response to an input polarity control signal, and the common voltage source supplies the common voltage, which is AC driven, to the common electrode.

When the common voltage source supplies a positive common voltage and the data driver supplies a negative data signal, the analog buffer of the data driver precharges the data line in the reset period, and precharges the data line. And the voltage is discharged toward the second driving voltage in the feedback period so as to converge with the negative data signal.

A driving method of a liquid crystal display according to the present invention comprises: a comparator including an inverter connected in series with an input line; A feedback switch connected between the input line and the output line; A charge switch connected between said output line and a common voltage source to form a closed loop; Connected between the comparator and the output line to precharge the output line to the common voltage of the common voltage source by the closed loop in a reset period, wherein the precharged voltage is fed back to the input line through the feedback switch in a feedback period Providing an analog buffer having an output inverter to block first and second driving voltages when converged to an input voltage from the input line, and a data driver including the analog buffer to drive data lines of a pixel matrix. And the analog buffer of the data driver includes a period for outputting a positive common voltage generated in the common voltage source and a period for outputting a negative common voltage to the data line, wherein the reset is performed when the common voltage is positive. When a negative data signal is input in the period, A pre-charged common voltage precharges the data line, causes the pre-charged voltage to discharge toward the second driving voltage in a feedback period, converges to the negative data signal, and resets when the common voltage is negative When the positive data signal is input in the period, the common voltage of the positive precharges the data line, and the precharged voltage rises by the first driving voltage in the feedback period to converge to the positive data signal. It is characterized by.

The analog buffer of the data driver has a high impedance state during the reset period, and a closed loop including the data line, the common voltage source, and the charge switch is formed to precharge the data line.

Other objects and advantages of the present invention in addition to the above objects will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 10.

4 illustrates an analog buffer, that is, an analog buffer of a data driver according to an exemplary embodiment of the present invention.

The analog buffer of the data driver shown in FIG. 4 includes first and second comparators 20 and 22 and an output inverter 24 connected in series between an input line and a data line DL, and an input line and a first comparator. An input switch SW1 connected between the input lines 20, a feedback switch SW2 connected between the input line and the data line DL, and a current path connected between the data line DL and the common voltage source Vcom. The charging switch (SW-Vcom) to form a.

Each of the first and second comparators 20, 22 is composed of an inverter. Specifically, each of the first and second comparators 20 and 22 includes an inverter 26, a capacitor C1 connected to an input terminal of the inverter 26, and input / output of the inverter 26, as shown in FIG. 5. Initialization switch SW3 connected between stages is provided. The initialization switch SW3 is driven by the first control signal CS1 together with the input switch SW1. The inverter 26 is connected between the supply line of the high potential driving voltage VDD and the output terminal as shown in FIG. 6 and controlled by the input terminal, and the supply line of the low potential driving voltage VSS. And an NMOS transistor NT connected between the output terminal and the output terminal and controlled by the input terminal.

The output inverter 24 is constituted by an inverter which is switched by the third and third control signals CS3a and CS3b. Specifically, as shown in FIG. 7, the output inverter 24 controls the first PMOS transistor PT1 and the first NMOS transistor NT1 constituting the inverter connected between the input terminal IN and the output terminal, and the third a control. A second PMOS transistor PT2 for switching the high potential driving voltage VDD to the first PMOS transistor PT1 in response to the signal CS3a, and a low potential driving voltage in response to the third b control signal CS3b. A second NMOS transistor NT2 for switching VSS to the first NMOS transistor NT1 is provided.

The feedback switch SW2 is controlled by the second control signal CS2 having a polarity opposite to the first control signal CS1.

The driving method of the analog buffer having such a configuration will be described with reference to the driving waveform shown in FIG.

Referring to FIG. 8, the common voltage Vcom, which is AC driven for line inversion, is inverted by one horizontal line unit. The polarity control signal POL, which determines the polarity of the data signal, is inverted to a polarity opposite to the common voltage Vcom. Accordingly, when the common voltage Vcom becomes positive (+), the data signal Data of negative polarity (-) (Vcom reference) is supplied, and when the common voltage Vcom becomes negative (-), the positive polarity is supplied. The data signal Data of (+) (Vcom reference) is supplied. As a result, the voltage range of the data signal Data can be reduced by the common voltage Vcom driven by AC, thereby reducing power consumption. In addition, the voltage supplied to the data line DL is adjusted to the common voltage Vcom by switching of the charging switch SW-Vcom. Accordingly, the voltage difference between the data line DL and the common electrode line does not occur, thereby minimizing the voltage distortion caused by the parasitic capacitor CDC generated between the data line DL and the common electrode line. As a result, the analog buffer according to the embodiment of the present invention can prevent crosstalk due to voltage distortion in the related art. In addition, the voltage distortion caused by the parasitic capacitor CDG formed between the data line DL and the gate line GL may be minimized by adjusting the voltage supplied to the data line DL. Since the data line and the common voltage are short-circuited during the precharge period, the parasitic capacitor (CDC), which causes the charge and discharge delay when the common voltage rises or falls, is reduced, thereby reducing the common voltage charge and discharge time.

Specifically, when the positive data signal is input during the reset period, the second NMOS transistor of the output inverter 24 turned off by the low thirda control signal CS3a. The output of the output inverter 24 is brought into a high impedance state by the second PMOS transistor PT2 of the output inverter 24 turned off by the NT2 and the high state 3b control signal CS3b. At the same time, a closed loop including the data line DL and the common voltage source Vcom is formed by the first control signal CS1 in the high state, and the data line DL is precharged by the common voltage source Vcom. Will be.

Next, the feedback switch SW2 is turned on by the second control signal CS2 in the high state during the feedback period FEEDBACK, that is, the data charge period, so that the voltage Vcom precharged to the data line DL is obtained. It converges to the input positive data signal Vin. Specifically, the voltage Vcom precharged on the data line DL is controlled by the second PMOS transistor PT2 of the output inverter 24 and the input terminal voltage by the third b control signal CS3b in the low state. The voltage is raised by the high potential supply voltage source VDD supplied through the turned-on first PMOS transistor PT1. Accordingly, when the output voltage Vout of the data line DL becomes equal to or higher than the input positive polarity data signal Vin, the input terminal voltage of the output inverter 24 by the first and second comparators 20 and 22. As a result, the first PMOS transistor PT1 is turned off to terminate the charging of the data line DL. As a result, when the positive data signal input to the data line DL is charged, the current path in the output inverter 24 is blocked, thereby reducing power consumption.

When the negative (-) data signal is input, the output inverter 24 operates in a manner opposite to the above.

Specifically, when the negative data signal is input in the reset period RESET, the input switch SW1 and the initialization switch SW3 are turned on in response to the first control signal CS1 in the high state. . As a result, the input and output terminals of the inverters 26 constituting the first and second comparators 20 and 22 are initialized to VTH, and the capacitor C1 is charged with the difference voltage between the input voltage Vin and VTH. At this time, the output is turned off by the second NMOS transistor NT2 of the output inverter 24 turned off by the third control signal CS3a in the low state and the third b control signal CS3b in the high state. The output of the output inverter 24 is in a high impedance state by the second PMOS transistor PT2 of the inverter 24. At the same time, a closed loop is formed between the data line DL and the common voltage source Vcom by the charging switch SW-Vcom turned on by the first control signal CS1. Accordingly, the data line DL is precharged by the common voltage source Vcom.

Next, in the feedback period FEEDBACK, the input switch SW1 and the initialization switch SW3 are turned off by the first control signal CS1 in the low state, and the second control signal CS2 in the high state. As the feedback switch SW2 is turned on, the voltage Vcom precharged to the data line DL converges to the input negative data signal. Specifically, the voltage Vcom precharged on the data line DL is dependent on the second NMOS transistor NT2 of the output inverter 24 and the input terminal voltage by the third a control signal CS3a in the high state. The discharge is performed while discharged toward the low potential supply voltage VSS through the first HMOS transistor NT1 turned on. Subsequently, when the voltage Vout of the data line DL becomes equal to or lower than the input positive data signal Vin, the input terminal voltage of the output inverter 24 is increased by the first and second comparators 20 and 22. As the first NMOS transistor NT1 is turned off, the charging of the data line DL is terminated. As a result, when the negative polarity (-) data signal input to the data line DL is charged, the current path in the output inverter 24 is blocked, thereby reducing power consumption. Here, the common voltage source Vcom is AC driven so that the polarity of the voltage is opposite to the voltage of the common voltage source Vcom in the negative polarity data signal.

As described above, in the output inverter 24 of the analog buffer according to the present invention, the voltage Vout output to the data line DL is not the same as the input data signal Vin so that the current flows only when the voltage is charged and discharged. When the charging to the data line DL is completed, no current flows, thereby reducing power consumption. In the output inverter 24 of the analog buffer according to the present invention, since the PMOS transistors PT1 and PT2 and the NMOS transistors NT1 and NT2 of the output inverter 24 are not turned on at the same time, the output voltage Vout is increased. In the process of converging to the input voltage Vin, oscillation such as rising and falling repeatedly can be prevented. In addition, in the analog buffer according to the present invention, power consumption may be reduced by minimizing the size of the transistors included in the remaining inverters 26 except for the output inverter 24.

FIG. 9 illustrates an example of charging an output of an analog buffer to a data line DL of 10 pF according to an embodiment of the present invention.

Referring to FIG. 9, when the polarity of the POL is positive (+), the output voltage Vout is initialized to Vcom-High by the first control signal CS1. When the first control signal CS1 is low, the data line DL is charged by the NTFT by the third a control signal CS3a. On the other hand, when the POL polarity is negative, the data line DL is initialized to Vcom-Low and charged to the PTFT by the third b control signal CS3b.

As described above, the analog buffer according to the present invention can reduce the power consumption since the current flows only when the output inverter of the output stage is not the same as the input voltage of the buffer to charge and discharge the voltage. In addition, in the output inverter of the analog buffer according to the present invention, since the PMOS transistor and the NMOS transistor are not turned on at the same time, no conduction current is generated, so that the power consumption is very small and the oscillation of rising and falling is repeated. It is possible to prevent circuit instability such as) phenomenon. In the liquid crystal display device and the driving method thereof, the data line is initialized to the common voltage so that the difference between the voltage of the data line and the common electrode line does not occur, thereby minimizing the influence of the parasitic capacitor. Accordingly, the image quality error such as crosstalk can be prevented and the same polarity can be used, which is efficient in terms of power consumption.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (14)

In the analog buffer for buffering the input voltage from the input line to the output line, A comparator comprising an inverter connected in series with said input line; A feedback switch connected between the input line and the output line; A charge switch connected between said output line and a common voltage source to form a closed loop; Connected between the comparator and the output line to precharge the output line to the common voltage of the common voltage source by the closed loop in a reset period, wherein the precharged voltage is fed back to the input line through the feedback switch in a feedback period And an output inverter for blocking the first and second driving voltage sources when converged to the input voltage. The method of claim 1, The comparator A plurality of inverters connected in series between the input line and the output inverter; A capacitor connected in series with the input of the inverter; And an initialization switch for initializing the inverter to the input / output terminal connection in the reset period. The method of claim 1, And an input switch for supplying the input voltage to the input line in the reset period. The method of claim 1, The output inverter First and second transistors connected between the comparator and the output line to constitute an inverter; A third transistor connected between a supply line of the first driving voltage source and the first transistor and controlled by a first control signal; And a fourth transistor connected between the supply line of the second driving voltage source and the second transistor and controlled by a second control signal. The method of claim 4, wherein The first and third transistors are PMOS transistors, and the second and fourth transistors are NMOS transistors. The method of claim 5, The output inverter And the third transistor and the fourth transistor are turned off by the first and second control signals in the reset period so that the output of the output inverter is in a high impedance state. The method of claim 5, The output inverter Pre-charging the output line to the common voltage source by turning off the third and fourth transistors according to the first and second control signals supplied to the input line in the reset period; And the first and third transistors are turned on in the feedback period such that the voltage on the output line converges to the input voltage while being charged by the first driving voltage source. The method of claim 2, Further comprising a second capacitor connected between said feedback switch and said input line, And an output voltage of the output line is adjusted by a ratio of the capacitor and the second capacitor. The method of claim 1, The common voltage source is an analog buffer, characterized in that for precharging the output line by using the common voltage is driven AC. A comparator including an inverter connected in series with the input line; A feedback switch connected between the input line and the output line; A charge switch connected between said output line and a common voltage source to form a closed loop; Connected between the comparator and the output line to precharge the output line to the common voltage of the common voltage source by the closed loop in a reset period, wherein the precharged voltage is fed back to the input line through the feedback switch in a feedback period An analog buffer having an output inverter which, when converged to an input voltage from the input line, cuts off the first and second drive voltage sources; A data driver for driving data lines of the pixel matrix; A gate driver for driving gate lines of the pixel matrix, And at least one of the data driver, the gate driver, and the common voltage source includes the analog buffer. 11. The method of claim 10, The data driver supplies a polarized inversion data signal to the data line in response to an input polarity control signal, And wherein the common voltage source supplies the common voltage driven by an alternating current to a common electrode. The method of claim 11, When the common voltage source supplies a positive common voltage and the data driver supplies a negative data signal The analog buffer of the data driver causes the common voltage source to precharge the data line in the reset period, and causes the precharged voltage to discharge toward the second driving voltage in the feedback period to converge to the negative data signal. A liquid crystal display device, characterized in that. A comparator including an inverter connected in series with the input line; A feedback switch connected between the input line and the output line; A charge switch connected between said output line and a common voltage source to form a closed loop; Connected between the comparator and the output line to precharge the output line to the common voltage of the common voltage source by the closed loop in a reset period, wherein the precharged voltage is fed back to the input line through the feedback switch in a feedback period Providing an analog buffer having an output inverter to block first and second driving voltages when converged to an input voltage from the input line, and a data driver including the analog buffer to drive data lines of a pixel matrix. Wow, The analog buffer of the data driver includes a period for outputting a common common voltage generated in the common voltage source to the data line and a period for outputting a common common voltage of negative polarity, When the common voltage is positive, when a negative data signal is input in a reset period, the negative common voltage precharges the data line, and the precharged voltage discharges toward the second driving voltage in a feedback period. Converge to a negative data signal, When the common voltage is negative, when a positive data signal is input in the reset period, the positive common voltage precharges the data line, and the precharged voltage is increased by the first driving voltage in the feedback period. And converging the positive data signal. The method of claim 13, The analog buffer of the data driver And a closed loop made up of the data line, the common voltage source, and a charge switch to precharge the data line.

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