KR101100762B1 - MIM capacitor and fabricating method thereof - Google Patents

Abstract

The present invention relates to an M capacitor and a method of manufacturing the same, and more particularly, by forming the lower electrode longer than the metal wiring region to simplify the process by the lower electrode includes a metal diffusion prevention function and electromigration of the metal wiring (electromigration) It is a technique of improving the integration characteristics by forming a thin film resistor (EM) characteristics and improve the EM capacitor manufacturing. To this end, the M capacitor of the present invention is formed by sequentially stacking a metal wiring formed of a metal material and a lower electrode, a dielectric film, and an upper electrode so as to be connected to the metal wiring, and the range of the lower electrode and the dielectric film is defined. A capacitor formed wider than the metal wiring by a predetermined range, a thin film resistor formed by depositing an upper electrode in parallel with the capacitor, and a plurality of via contact plugs for connecting the capacitor and the thin film resistor with a second metal wiring; It is characterized by including the configuration.

Description

MIM capacitor and fabrication method

1 is a cross-sectional view of a conventional M capacitor.

2 is a cross-sectional view of an M capacitor according to an embodiment of the present invention.

Figures 3a to 3g is a process diagram showing a method of manufacturing the M capacitor of Figure 2;

The present invention relates to an M capacitor and a method of manufacturing the same, and more particularly, by forming the lower electrode longer than the metal wiring region to simplify the process by the lower electrode includes a metal diffusion prevention function and electromigration of the metal wiring (electromigration) It is a technique of improving the integration characteristics by forming a thin film resistor (EM) characteristics and improve the EM capacitor manufacturing.

In general, a capacitor stores electric charges and supplies electric charges necessary for the operation of the semiconductor device. As the semiconductor device becomes highly integrated, the capacitance of the device becomes smaller while the size of the unit cell becomes smaller. Is a general trend.                         

In particular, analog capacitors applied to CMOS IC logic devices that require high precision are advanced analog MOS technologies, in particular, A / D converters or switching capacitor filters. It is a key element of the field. The structure of the analog capacitor is PIP (Poly-Insulator-Poly), PIM (Poly-Insulator-Metal), MIP (Metal-Insulator-Poly) and MIM (Metal-Metal) Insulator-Metal) and other structures have been used.

Among them, the MIM structure has a low series resistance, so that a capacitor having a high Q (Quality Factor) value can be realized, and in particular, a low thermal budget, a low Vcc, and a small parasitics. It has a component (Parastic Resistance; Capacitance) and is used as a representative structure of an analog capacitor.

1 is a cross-sectional view of a conventional MIM capacitor.

In the conventional MIM capacitor, the etch stop film 11 and the hard mask film 21 are sequentially stacked on the metal wiring 10, and then a portion of the MIM capacitor is removed to form an area for forming a capacitor. The lower electrode 12 and the dielectric film 13 are sequentially stacked, and are formed in a trench type. The upper electrode 14 and the capping layer 15 having a predetermined size are sequentially deposited on the dielectric layer 13, and a via contact plug 16 is formed to be connected to the upper electrode 14. An etch stop layer 18 and a metal wiring 19 are formed on the upper portion 16.                         

In the conventional MIM capacitor having the above structure, the lower electrode 12 cannot prevent the diffusion of the metal material of the metal wiring 10 and is used only as the lower electrode.

 In addition, when the MIM capacitors are included in the memory device and the non-memory device, in order to use the thin film resistors together, a separate thin film resistor is required to be connected and separately connected, and thus the area consumption of the device is high and the integration degree is low. have.

An object of the present invention for solving the above problems, by forming the lower electrode longer than the metal wiring area to perform the metal diffusion prevention function of the lower electrode, there is no need to form a separate metal diffusion prevention film to simplify the process It is to improve the electromigration (EM) characteristics of metal wiring.

In addition, another object of the present invention is to improve the degree of integration of the device by forming a thin film resistor (thin film resistor) together in the manufacture of MMC capacitor.

The M capacitor according to the embodiment of the present invention for achieving the above object is formed by sequentially stacking a lower electrode, a dielectric film, and an upper electrode so as to be connected to a metal wiring formed of a metal material and the metal wiring. And a capacitor having a range of an electrode and the dielectric film wider than the metal wiring by a predetermined range, and a plurality of via contact plugs for connecting the capacitor with the second metal wiring.                     

 In addition, in the method of manufacturing an MMC capacitor according to an embodiment of the present invention, (a) forming an interlayer insulating film including a metal wiring, and sequentially depositing an etch stop film and a hard mask film on the upper portion, and then through an etching process Forming a region for forming a capacitor by exposing the metal wiring; and (b) sequentially depositing a conductive material for the lower electrode and a dielectric material for forming a dielectric film, and sequentially depositing a predetermined length than the metal wiring through an etching process. Forming the lower electrode and the dielectric film as long as possible, and (c) depositing a conductive material for the upper electrode on top of the dielectric film and forming an upper electrode of a predetermined size through a photolithography process. It is characterized by.

In addition, according to another embodiment of the present invention, a method of manufacturing an MCM capacitor may include: (a) forming an interlayer insulating film including a metal wiring, and sequentially depositing an etch stop film and a hard mask film thereon, and then performing an etching process. Forming a region for forming a capacitor by exposing the metal wiring; (b) sequentially depositing a conductive material for a lower electrode and a dielectric material for forming a dielectric film, and sequentially forming a lower electrode and a dielectric film through an etching process. And forming a region for forming the thin film register, (c) depositing a conductive material for the upper electrode on the entire surface, and forming an upper electrode of a predetermined size through a photolithography process to form the capacitor and the thin film resistor. Characterized in that it comprises a.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view of an MI capacitor according to an embodiment of the present invention.

In the M capacitor according to the embodiment of the present invention, the etch stop film 102 and the hard mask film 103 are sequentially stacked on the interlayer insulating film 101 including the metal wiring 100, but the metal wiring ( The lower electrode 106 and the dielectric film 107 are sequentially stacked on the upper portion 100 to form a trench type.

In this case, the lower electrode 106 in contact with the metal wiring 100 is formed to be longer than the horizontal length of the metal wiring 100 by a predetermined length, so that the lower electrode 106 is a region where the metal material of the metal wiring 100 is different from each other. It is to perform a function to sufficiently prevent the spread.

The upper electrode 114 and the capping layer 115 having a predetermined size are sequentially deposited on the dielectric layer 107, and a plurality of via contact plugs 118 are formed to be connected to the upper electrode 114. The metal wiring 121 is formed on the plug 118. The via contact plug 117 connected to the lower electrode 114 in the trench is formed to be connected to the upper metal wiring 120.

Meanwhile, the upper electrode 112 and the capping layer 113 having a predetermined size for forming a thin film resistor (TFR) on the etch stop layer 102 and the hard mask 103 in the region other than the trench are sequentially formed. Are deposited, and a plurality of via contact plugs 119 are formed to be connected to the upper electrode 112, and metal wirings 122 and 123 are formed to be connected to the plurality of via contact plugs 119, respectively.

As described above, the M capacitor according to the embodiment of the present invention can simplify the process by forming the lower electrode longer than the metal wiring region so that the lower electrode includes the metal diffusion prevention function, thereby forming a separate metal diffusion prevention film. In addition, the electromigration (EM) characteristics of the metal wiring can be improved.                     

In addition, the degree of integration may be improved by forming a mask to simultaneously fabricate an M capacitor and a thin film resistor.

Hereinafter, a method of manufacturing an MCM capacitor will be described with reference to FIGS. 3A to 3G.

First, as shown in FIG. 3A, an interlayer insulating film 101 including a metal wiring 100 is formed through a conventional damascene process, and an etch stop film 102 and a hard mask film (top) are formed thereon. After the 103 is sequentially deposited, the metal wiring 100 is exposed through an etching process. In this case, the etch stop layer 102 is formed using silicon nitride (Si ₃ N ₄ ), and the hard mask layer 103 is formed using silicon oxide (SiO ₂ ).

Here, the damascene process uses a photo-lithography technique to form a groove by etching the lower insulating film in a predetermined depth to form a wiring, and aluminum (Al), copper (Cu), or tungsten (W) in the groove. The conductive material, such as), is filled, and the conductive material other than the necessary wiring is removed by using techniques such as etching back or chemical mechanical polishing (CMP) to form the wiring in the shape of the groove formed at the beginning. It is a technique to do.

In particular, the dual damascene process is largely divided into a via first method, a trench first method, and a self aligned method. The via first method uses a photo-etched dielectric layer to etch vias. After the hole is formed first, the insulating layer is etched again to form a trench in the upper portion of the via hole. In contrast, the trench first method is a method of forming a trench after forming a trench first, and the self-aligning dual damascene method is a method in which via holes are simultaneously formed when the trench is etched when the via holes are aligned under the trench structure. .

As shown in FIG. 3B, the conductive material 104 and the dielectric material 105 for sequentially forming the lower electrode are sequentially deposited on the top of FIG. 3A. At this time, the conductive material 104 for forming the lower electrode is preferably deposited to a thickness of 50 ~ 100Å or more, the conductive material for the lower electrode in order to solve the alignment problem of the lower electrode during the photolithography process It is preferable to perform a key process before depositing.

As shown in FIG. 3C, a portion of the conductive material 104 and the dielectric material 105 is removed through the etching process, and the lower electrode 104 and the dielectric film 105 having a predetermined size are sequentially formed. In this case, the lower electrode 104 is formed to be longer than the horizontal length region of the metal wiring 100 to prevent diffusion of the metal material from the metal wiring 100.

As shown in FIG. 3D, the conductive material 108 for forming the upper electrode 114 and the capping layer 115 of FIG. 3E and the material 109 for forming the capping layer are sequentially sequentially formed on the upper portion of FIG. 3C. After deposition, the photoresist (PR) 110, 111 for patterning the upper electrode 114 and the thin film resistor is formed. In this case, the photoresist 110 for the M capacitor is formed in the trench, and the photoresist 111 for the thin film resistor is formed on the region without the lower electrode 106 and the dielectric film 107. Here, the capping layer 115 is formed using silicon nitride (Si ₃ N ₄ ).

As shown in FIG. 3E, an M capacitor and a thin film resistor in which the upper electrode 114 and the capping layer 115 patterned in a predetermined size are sequentially stacked according to the photoresist 110 and 111 of FIG. 3D. (TFR). In this case, the upper electrode 114 and the lower electrode 106 may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Is deposited.

Here, the upper electrodes 114 and 112 and the lower electrode 106 are aluminum (Al), tungsten (W), copper (Cu), tantalum nitride (TaN), tantalum (Ta), and titanium nitride (TiN). The dielectric film 107 and the capping layers 113 and 115 are formed using a material such as silicon nitride (SiN), silicon oxide nitride (SiON), silicon carbon (SiC), and silicon nitride carbon (SiNC). ) And high dielectric materials.

As shown in FIG. 3F, an interlayer insulating film 116 is deposited on the entire surface of FIG. 3E and a via hole (not shown) for forming a plurality of via contact plugs 117 to 119 is formed. After depositing, the upper electrode of the MM capacitor (MIM) by embedding in a via hole (not shown) with a metal material using electroplating and performing a chemical mechanical polishing (CMP) A plurality of via contact plugs 118 connected to the 114, a via contact plug 117 connected to the lower electrode 106 in the trench, and an upper electrode 112 of the thin film resistor TFR; A plurality of via contact plugs 119 are formed. Here, the electroplating method is a surface treatment method that not only increases the glossiness of the surface by electrically coating the substrate surface with another metal, but also increases the surface hardness and the corrosion resistance.

As shown in FIG. 3G, the metal wiring 120 connected to the via contact plug 117, the metal wiring 121 connected to the plurality of via contact plugs 118, and the plurality of via contact plugs are disposed on the upper portion of FIG. 3F. An interlayer insulating film 124 including metal wirings 122 and 123 respectively connected to 119 is formed.

Here, the metal wires 100 and 120 to 123 and the via contact plugs 117 to 119 are formed using metal materials such as copper (Cu) and aluminum (Al).

As described above, the present invention does not need to form a separate metal diffusion barrier by forming the lower electrode longer than the metal wiring region so that the lower electrode performs the metal diffusion prevention function, thereby simplifying the process and moving the electrons of the metal wiring. It is effective in improving (electromigration; EM) characteristics.

In addition, by forming a thin film resistor (thin film resistor) together in the manufacture of the M capacitor has the effect of improving the integration of the device.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (15)

A metal wire formed of a metal material; A capacitor formed by sequentially stacking a lower electrode, a dielectric film, and an upper electrode so as to be connected to the metal wiring, and having a range of the lower electrode and the dielectric film wider than the metal wiring by a predetermined range or more; And And a plurality of via contact plugs for connecting the capacitors to the second metal wires. The upper electrode is disposed in one region of the dielectric film, At least one of the plurality of via contact plugs is connected to the lower electrode, and at least the other is connected to the upper electrode. The method of claim 1, M capacitor characterized in that it further comprises a thin film resistor formed in parallel with the capacitor. The method of claim 1, wherein the upper electrode and the lower electrode is any one of aluminum (Al), tungsten (W), copper (Cu), tantalum nitride (TaN), tantalum (Ta), and titanium nitride (TiN). MM capacitor, characterized in that composed of one material. The method of claim 1, wherein the dielectric film is made of any one of silicon nitride (SiN), silicon oxide nitride (SiON), silicon carbon (SiC), silicon nitride carbon (SiNC), and a high dielectric material. IMM capacitor characterized by the above. (a) forming an interlayer insulating film including a metal wiring, sequentially depositing an etch stop film and a hard mask film thereon, and then forming an area to form a capacitor by exposing the metal wiring through an etching process; (b) sequentially depositing the conductive material for the lower electrode and the dielectric material for forming the dielectric film and sequentially forming the lower electrode and the dielectric film by a predetermined length longer than the metal wiring through an etching process; (c) depositing a conductive material for the upper electrode on top of the dielectric film and forming an upper electrode of a predetermined size through a photolithography process; (d) forming a plurality of via contact plugs at least one of which is connected to the upper electrode and at least one of which is connected to the lower electrode; And and (e) forming a plurality of upper metal wires connected to the plurality of via contact plugs. The upper electrode is an M capacitor manufacturing method disposed in one region of the dielectric film. delete 6. The method of claim 5, wherein a key process is performed to align the lower electrode conductive material and the metal wiring during deposition of the lower electrode conductive material in the step (b). Method of manufacturing the MCM capacitor. The method of claim 5, wherein the conductive material for the upper electrode and the conductive material for the lower electrode is aluminum (Al), tungsten (W), copper (Cu), tantalum nitride (TaN), tantalum (Ta), or titanium nit Method for manufacturing an M capacitor, characterized in that formed of any one of the ride (TiN). The method of claim 5, wherein the etch stop layer and the dielectric layer are any one of silicon nitride (SiN), silicon oxide nitride (SiON), silicon carbon (SiC), silicon nitride carbon (SiNC), and a high dielectric material. Method of manufacturing an IC capacitor, characterized in that formed of the material. (a) forming an interlayer insulating film including a metal wiring, sequentially depositing an etch stop film and a hard mask film thereon, and then forming an area to form a capacitor by exposing the metal wiring through an etching process; (b) sequentially depositing the conductive material for the lower electrode and the dielectric material for forming the dielectric film, sequentially forming the lower electrode and the dielectric film by a predetermined length longer than the metal wiring through an etching process, and forming a thin film resistor. Forming a region; (c) depositing the conductive material for the upper electrode on the entire surface and forming an upper electrode of a predetermined size through a photolithography process to form the capacitor and the thin film resistor; (d) forming a plurality of via contact plugs connected to the capacitor and the upper electrode of the thin film resistor; And and (e) forming a plurality of upper metal wires connected to the plurality of via contact plugs. The upper electrode is disposed in one region of the dielectric film, At least one of the plurality of via contact plugs connected to the capacitor is connected to the lower electrode, and at least the other is connected to the upper electrode. delete delete The method of claim 10, wherein a key process is performed to align the lower electrode conductive material and the metal wiring at the time of depositing the lower electrode conductive material in the step (b). Method of manufacturing the MCM capacitor. The method of claim 10, wherein the conductive material for the upper electrode and the conductive material for the lower electrode is aluminum (Al), tungsten (W), copper (Cu), tungsten silicon nitride (WSiNx), nickel chromium (NiCr), ferro Method for manufacturing an M capacitor, characterized in that formed of any one of silicon (FeSi), tantalum nitride (TaNx), tantalum (Ta), or titanium nitride (TiNx) series. The method of claim 10, wherein the etch stop layer and the dielectric layer are any one of silicon nitride (SiN), silicon oxide nitride (SiON), silicon carbon (SiC), silicon nitride carbon (SiNC), and a high dielectric material. Method of manufacturing an IC capacitor, characterized in that formed of the material.

Images