KR101096264B1 - Method of manufacturing semiconductor device having dual poly-gate of recessed gate structure - Google Patents

Abstract

A method of manufacturing a semiconductor device having a dual polygate having a recess gate structure according to the present invention includes forming a first recess and a second recess in a first region and a second region of a substrate, respectively; Forming a gate insulating film on the substrate on which the second recess is formed, a first polysilicon film filling the recess on the gate insulating film, and a second polysilicon film and a third poly sequentially disposed on the first polysilicon film A poly-type doped polygate including a silicon film, wherein the first polysilicon film has a first concentration to suppress the movement of the shim formed inside the first polysilicon film during the process of forming the first polysilicon film. The second polysilicon film is formed to have a second concentration lower than the first concentration, and the third polysilicon film is formed to have a third concentration higher than the first concentration. And selectively doping the p-type impurity to the polygate of the second region, and performing heat treatment to activate the n-type impurity in the first region and the p-type impurity in the second region. .

Dual Polygate, Recess Gate, Poly Seam, Counter Doped

Description

Method for manufacturing semiconductor device having dual poly-gate of recessed gate structure

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a dual polygate having a recess gate structure.

Recently, as the degree of integration of semiconductor devices increases, the channel length of transistors, which is a major component of semiconductor devices, is also getting shorter. Therefore, the short channel effect is a problem in the conventional planar transistor. The short channel effect causes severe punch-through between the source and drain of the transistor, which is recognized as a major cause of malfunction of transistor elements. In addition, the doping concentration of the substrate is increased, and the increased doping concentration causes an increase in the electric field and the junction leakage current, thereby ensuring sufficient data retention time in the case of a memory device such as DRAM. Provide difficulties. Recently, in order to suppress the short channel effect, a recess gate structure is applied to increase the effective channel length by forming a gate in the trench after forming the trench in the substrate. The recess gate structure includes a general structure in which the trench bottom surface is rounded and a bulb structure in which an extended sphere is disposed on the trench bottom surface. In either structure, the channel is formed along the trench profile, i.e., along the bottom and sidewalls of the trench, thus having a longer length than the line width of the recess gate.

However, in forming the recess gate structure, a poly seam may be generated in the polysilicon film filled with the trench in the process of filling the trench with the polysilicon film after forming the trench. Here, the poly seam means an empty space in which polysilicon is not filled in the process of filling a narrow trench. Furthermore, when the polysilicon film has a low impurity concentration in the polysilicon film, it tends to move closer to the gate insulating film through a subsequent thermal process. As a result, the write timing (tWR) characteristic of the DRAM is greatly degraded. Therefore, in this case, the poly seam was minimized by increasing the impurity concentration of the polysilicon film.

However, when the recess gate structure is applied to the dual poly gate, which has recently been expanded in scope, it is difficult to increase the impurity concentration of the polysilicon film. The dual polygate refers to a structure in which an n-type doped polysilicon film is used as a gate in an area where an n-type transistor is disposed, and a p-type doped polysilicon film is used as a gate in an area where a p-type transistor is disposed. . The reason for using such a dual polygate is that the channel formed in the buried structure is formed in the region where the p-type transistor is used when the n-doped polysilicon film is formed, whereas the poly-doped poly-gate is formed. This is because when the silicon film is used, a channel is formed with a surface structure.

In general, in order to use a p-type doped polysilicon film as a gate in a dual polygate, counter doping for converting an n-type polysilicon film formed in a region where a p-type transistor is to be placed into a p-type should be performed. . Therefore, when the doping concentration of the n-type impurity of the n-type polysilicon film is increased to suppress the movement of the poly shim, at least one of the doping concentration and the energy of the p-type impurity must be increased in order to achieve a desired counter doping. . In this case, however, p-type impurities, such as boron (B), may cause boron penetration through the gate insulating film, thereby deteriorating the operation performance and reliability of the device. Therefore, when the dual polygate of the recess gate structure is employed, the doping of the n-type impurity must be increased to suppress the movement of the poly shim, but in this case, the counter doping for forming the p-type polygate is not performed properly. have.

Recently, in order to solve this problem, a method of dividing the polysilicon film deposition process into two steps has been proposed. Specifically, after the polysilicon film is deposited by a predetermined thickness, heat treatment is performed to crystallize the deposited polysilicon film. A polysilicon film is then deposited to form a polygate, thereby making the energy state at the interface between the crystallized polysilicon film and the later deposited polysilicon film high. This high energy interface serves as a wall to block the movement of the poly shims. In this case, therefore, the poly shim can be prevented to some extent even without increasing the n-type impurity concentration. However, this method has to be performed separately from the polysilicon film deposition process, and the heat treatment for crystallization is performed in the meantime, the overall process step is increased, and as a result, the manufacturing cost is increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device having a dual polygate having a recess gate structure capable of smoothly counter-doping while suppressing movement of a poly shim without increasing process steps.

A method of manufacturing a semiconductor device having a dual polygate having a recess gate structure according to an exemplary embodiment of the present invention may include forming first and second recesses in a first region and a second region of a substrate, respectively, Forming a gate insulating film on the substrate on which the first recess and the second recess are formed, a first polysilicon film filling the recess on the gate insulating film, and a second polysilicon film sequentially disposed on the first polysilicon film And a third polysilicon film to form an n-type doped polygate, wherein the first polysilicon film is capable of suppressing the movement of the seam made inside the first polysilicon film in the process of forming the first polysilicon film. The second polysilicon film is formed to have a first concentration, the second polysilicon film is formed to have a second concentration lower than the first concentration, and the third polysilicon film has a third concentration higher than the first concentration. Forming a wafer, selectively doping a p-type impurity to the polygate in the second region, and performing a heat treatment to activate the n-type impurity in the first region and the p-type impurity in the second region. Include.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a dual polygate having a recess gate structure, the method including: forming a first trench and a second trench in a first region and a second region of a substrate, respectively; Forming a gate insulating film on the substrate on which the trench and the second trench are formed, a first polysilicon film filling the first trench and the second trench on the gate insulating film, and a second poly sequentially disposed on the first polysilicon film A silicon film, a third polysilicon film, and a fourth polysilicon film are formed, and an n-type doped polygate is formed, wherein the first polysilicon film is formed to have a first concentration to suppress the movement of the shim formed therein. The second polysilicon film is formed to have a second concentration lower than the first concentration, and the third polysilicon film is formed to have a third concentration higher than the first concentration, and a fourth The polysilicon film is formed by undoping undoped, selectively doping p-type impurities to the polygate of the second region, and performing heat treatment to perform n-type impurities and the second region of the first region. Activating the p-type impurity.

According to the present invention, the buried portion of the recess gate has a doping concentration sufficient to suppress the movement of the poly shim, and the upper portion of the trench of the recess gate has a low doping concentration to facilitate counter doping. On top of this, by having a high doping concentration so that the characteristics of the n-type polygate can be satisfactorily exhibited, the advantage of counter-doping the p-type impurity for forming the p-type polygate can be achieved while suppressing the movement of the poly shim. Is provided. In particular, since such a process is performed through one deposition process, the process step is not increased, and thus manufacturing costs can be reduced.

1 to 6 are views illustrating a method of manufacturing a semiconductor device having a dual polygate having a recess gate structure according to an embodiment of the present invention. First, referring to FIG. 1, an isolation layer 110 is formed on a substrate 100 having a first region 101 and a second region 102. Here, the first region 101 is a region where the n-type transistor is disposed and the second region 102 is a region where the p-type transistor is disposed. Therefore, an n-type doped polygate is formed in the first region 101, and a p-type polygate doped with a p-type is formed in the second region 102. The substrate 100 is a silicon (Si) substrate, and the device isolation layer 110 is formed in a trench form, but is not limited thereto. An active region is defined by the device isolation layer 110. Next, an ion implantation buffer layer 120 is formed on the active region of the substrate 100 defined by the device isolation layer 110. The ion implantation buffer layer 120 may be formed of a silicon oxide layer. Next, as indicated by arrows in the figure, impurity ions are implanted into the active region of the substrate 100. The impurity ion implantation is to adjust the threshold voltage in the active region of the substrate 100 and to form a well region and a channel region if necessary. After implanting the impurity ions, the ion implantation buffer layer 120 is removed.

Next, referring to FIG. 2, first trenches 131 and second trenches 132 are formed in the first region 101 and the second region 102 of the substrate 100, respectively. In the present example, the first trench 131 and the second trench 132 are formed as a bulb type, but the lower end of the trench may be formed as a general recess type having a curved shape. For example, in order to form the bulb-shaped first trenches 131 and the second trenches 132, etching is performed using a predetermined mask layer pattern to form a conventional trench, and then a protective film is formed on the trench sidewalls. The substrate 100 exposed by the trench in the state is etched isotropically (symmetric) to form an extended spherical portion. However, the bulb-shaped first trench 131 and the second trench 132 may be formed by other methods than those described above.

Next, referring to FIG. 3, a gate insulating layer 140 is formed on an active region of the substrate 100 on which the first trench 131 and the second trench 132 are formed. The gate insulating layer 140 may be formed of a silicon oxide layer, but is not limited thereto. Next, the first gate 131 and the second trench 132 are embedded to form a polygate 150 to have a predetermined thickness over the surface of the substrate 100. In the process of forming the polygate 150, the poly shim 160 may be formed in the first trench 131 and the second trench 132, in particular, an extended spherical portion.

As shown in FIG. 4, the polygate 150 includes a first polysilicon film 151, a second polysilicon film 152, a third polysilicon film 153, and a fourth polysilicon film 154. It is configured to include. The first polysilicon layer 151, the second polysilicon layer 152, and the third polysilicon layer 153 have different doping concentrations of n-type impurities, and in the case of the fourth polysilicon layer 154, the impurities are doped. It is undoped. In detail, the first polysilicon layer 151 has a first concentration to suppress movement of the poly shim 160 during subsequent heat treatment. In one example, the first concentration is between 3.5 × 10 ²⁰ and 4.5 × 10 ²⁰ atoms / cm 3. The first polysilicon layer 151 has a minimum thickness within a range in which all of the inside of the first trench 131 (or the second trench 132) can be filled. Although the drawing shows only the first trench 131 (or the second trench 132) as an ideal case, the first polysilicon film 151 may be formed of a substrate (except for the portion where the trench is located). 100) may be stacked on.

The second polysilicon film 152 has a second concentration lower than the first concentration, which is an n-type impurity concentration in the first polysilicon film 151. In one example, the second concentration is 1.0 × 10 ²⁰ to 2.0 × 10 ²⁰ atoms / cm 3. Since the second polysilicon layer 152 has a relatively low second concentration, counter doping may be smoothly performed when doping p-type impurities into the second region 102. The thickness of the second polysilicon film 152 depends on the thicknesses of the first polysilicon film 151, the third polysilicon film 153, and the fourth polysilicon film 154, but is generally the thickest. Has

The third polysilicon film 153 has a third concentration higher than the first concentration, which is the n-type impurity concentration in the first polysilicon film 151. In one example, the third concentration is 5.0 × 10 ²⁰ to 7.0 × 10 ²⁰ atoms / cm 3. The third polysilicon film 153 has a relatively high impurity doping concentration in order to maintain the n-type characteristics of the n-type polygate to be formed in the first region 101, and thus it is not necessary to form a thick layer. In one example, the third polysilicon film 153 is formed to a thickness of about 100 kPa to 300 kPa, preferably about 200 kPa.

The fourth polysilicon film 154 is disposed on the top, and is formed of an undoped polysilicon film that is not doped with impurities. Since the third polysilicon film 153 disposed below the fourth polysilicon film 154 is heavily doped, the third polysilicon film 153 is disposed when the third polysilicon film 153 is disposed on the uppermost portion. Phosphorus (P) doped at high concentrations in the out-diffusion (out-diffusion), which can act as a major cause of the defect (defect) made during the process. However, as in the present exemplary embodiment, the phosphorus P inside the third polysilicon layer 153 is disposed by disposing the fourth polysilicon layer 154 in the undoped state on the third polysilicon layer 153. ) Can be prevented from spreading to the outside. Therefore, the fourth polysilicon film 154 is formed to a thickness sufficient to prevent the phosphorus P in the third polysilicon film 153 from diffusing to the outside. In one example, the fourth polysilicon film 154 is formed to a thickness of approximately 50 kPa to 150 kPa, preferably 100 kPa.

Formation of the first polysilicon film 151, the second polysilicon film 152, and the third polysilicon film 153 and the fourth polysilicon film 154 without impurity doping with different concentrations may be performed. It can be done with only a single lamination process. Specifically, the substrate 100 having the first trench 131 and the second trench 132 and the gate insulating film 140 is formed into a polysilicon film deposition chamber, for example, a chemical vapor deposition (CVD) chamber. After the temperature and pressure of the chamber are appropriately set, the reaction gas for forming the polysilicon film and the impurity source gas for impurity doping are supplied into the chamber. In this process, the impurity source gas is formed in an amount such that doping is performed at a first concentration while the first polysilicon layer 151 is formed, that is, until the first trench 131 and the second trench 132 are buried. Supply. While the first polysilicon film 151 is deposited and the second polysilicon film 152 is deposited, the amount of the impurity source gas is reduced so that the doping concentration becomes the second concentration. Similarly, while the second polysilicon film 152 is deposited and the third polysilicon film 153 is deposited, the amount of the impurity source gas is increased so that the doping concentration becomes the third concentration. After the third polysilicon film 153 is deposited, the supply of the impurity source gas is interrupted to form the fourth polysilicon film 154 which is not doped with impurities. As such, by controlling only the supply amount of the impurity source gas, the first polysilicon film 151, the second polysilicon film 152, and the third polysilicon film 153 having different concentrations even in a single polysilicon film deposition step. ) And the fourth polysilicon film 154 without impurity doping may be formed.

Next, referring to FIG. 4, a mask film pattern 160 is formed to cover the polygate 150 of the first region 101 and expose the polygate 150 of the second region 102. The mask film pattern 160 is formed of a photoresist film, but is not limited thereto. After the mask film pattern 160 is formed, as shown by an arrow in the figure, the p-type impurity, for example, boron B, is doped. Boron (B) doping may be performed using a conventional ion implantation method, or may be performed using a plasma doping (PLAD) method. Boron (B) doping is performed to the extent that the polygate 150 of the second region 102 can be converted from n-type to p-type. As described with reference to FIG. 4, since the concentration of the thickest second polysilicon film 152 of the polysilicon films constituting the polygate 150 has a relatively low second concentration, the boron B is doped. Even without setting too many doses or high energy conditions, counter doping in the second region 102 can be performed smoothly, thereby obtaining a sufficient counter doping effect and at the same time suppressing the occurrence of boron (B) penetration. can do. Boron B doping is performed such that the concentration of boron B in the polygate 150 in the second region 102 is approximately 1.0 × 10 ¹⁷ atoms / cm 3 or less. As the boron (B) doping is selectively performed on the second region 102 as described above, phosphorus P, which is an n-type impurity, is contained in the polygate 150 of the first region 101. carrier, and the boron B, which is a p-type impurity, becomes a majority carrier in the polygate 150 of the second region 102. After the boron (B) doping is performed, the mask layer pattern 160 is removed.

Next, referring to FIG. 6, heat treatment for activation of phosphorus P and boron B doped in a polygate (150 in FIG. 5) is performed as indicated by arrows in the figure. The heat treatment may be performed using a rapid thermal processing (RTP) method, and in this case, the heat treatment may be performed for about 10 to 20 seconds at a temperature condition of 950 ° C to 1000 ° C and an O ₂ atmosphere. During this heat treatment, the doped phosphors P and boron B in the polygate 150 (see FIG. 5) are activated so that the polygate in the first region 101 becomes an n-type polygate 150n. The polygate in the second region 102 becomes a p-type polygate 150p. In addition, since the first polysilicon film 151 of FIG. 4 surrounding the poly shim 160 has a second concentration sufficient to suppress the movement of the poly shim 160 during the heat treatment, the poly shim ( It is possible to prevent the 160 from moving near the gate insulating layer 140.

Next, although not shown in the drawings, the gate barrier metal layer, the gate metal film, and the gate hard mask film are sequentially formed on the n-type polygate 150n and the p-type polygate 150p, and then gated by conventional patterning. Form a stack.

1 to 6 are views illustrating a method of manufacturing a semiconductor device having a dual polygate having a recess gate structure according to an embodiment of the present invention.

Claims (21)

Forming a first trench and a second trench in the first region and the second region of the substrate, respectively; Forming a gate insulating film on the substrate on which the first trench and the second trench are formed; A first polysilicon layer doped to an n-type of a first concentration while filling the first trench and the second trench on the gate insulating layer, and sequentially disposed on the first polysilicon layer to an n-type of a second concentration; Forming a polygate including a doped second polysilicon film and a third polysilicon film doped to an n-type at a third concentration, A second concentration of the second polysilicon film is lower than the first concentration, and a third concentration of the third polysilicon film is higher than the first concentration; Counter doping a p-type impurity with respect to the polygate of the second region to form n-type and p-type polygates in the first region and the second region, respectively; And And heat-treating the n-type impurity in the first region and the p-type impurity in the second region. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, The first trench and the second trench have a bulb type structure. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, And a first concentration of the first polysilicon film is 3.5 × 10 ²⁰ to 4.5 × 10 ²⁰ atoms / cm 3. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, And the first polysilicon layer is formed to fill the first trench and the second trench. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, And a second concentration of the second polysilicon film is 1.0 × 10 ²⁰ to 2.0 × 10 ²⁰ atoms / cm 3. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, And a third concentration of the third polysilicon film is 5.0 × 10 ²⁰ to 7.0 × 10 ²⁰ atoms / cm 3. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, Claim 8 was abandoned when the registration fee was paid. The method of claim 1, The heat treatment is a method of manufacturing a semiconductor device performed for 10 seconds to 20 seconds at a temperature condition of 950 ℃ to 1000 ℃ and O ₂ atmosphere conditions. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 1, Formation of the first polysilicon film, the second polysilicon film, and the third polysilicon film is performed in a single step of depositing the polysilicon film while varying the supply amount of the impurity source gas in the polysilicon film deposition chamber. Way. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 1, The counter-doping of the p-type impurity is performed such that the p-type impurity concentration in the polygate of the second region is 1.0 × 10 ¹⁷ atoms / cm 3 or less. Forming a first trench and a second trench in the first region and the second region of the substrate, respectively; Forming a gate insulating film on the substrate on which the first trench and the second trench are formed; A first polysilicon layer doped to an n-type of a first concentration while filling the first trench and the second trench on the gate insulating layer, and sequentially disposed on the first polysilicon layer to an n-type of a second concentration; Forming a polygate comprising a doped second polysilicon film, a third polysilicon film doped to an n-type at a third concentration, and an undoped undoped fourth polysilicon film, A second concentration of the second polysilicon film is lower than the first concentration, and a third concentration of the third polysilicon film is higher than the first concentration; Counter doping a p-type impurity with respect to the polygate of the second region to form n-type and p-type polygates in the first region and the second region, respectively; And And heat-treating the n-type impurity in the first region and the p-type impurity in the second region. Claim 12 was abandoned upon payment of a registration fee. The method of claim 11, The first trench and the second trench have a bulb type structure. Claim 13 was abandoned upon payment of a registration fee. And a first concentration of the first polysilicon film is 3.5 × 10 ²⁰ to 4.5 × 10 ²⁰ atoms / cm 3. Claim 14 was abandoned when the registration fee was paid. The method of claim 11, And the first polysilicon layer is formed to fill the first trench and the second trench. Claim 15 was abandoned upon payment of a registration fee. The method of claim 11, And a second concentration of the second polysilicon film is 1.0 × 10 ²⁰ to 2.0 × 10 ²⁰ atoms / cm 3. Claim 16 was abandoned upon payment of a setup registration fee. The method of claim 11, And a third concentration of the third polysilicon film is 5.0 × 10 ²⁰ to 7.0 × 10 ²⁰ atoms / cm 3. Claim 17 has been abandoned due to the setting registration fee. The method of claim 11, And a thickness of the third polysilicon film is 100 kPa to 300 kPa. Claim 18 was abandoned upon payment of a set-up fee. The method of claim 11, And a fourth polysilicon film having a thickness of 50 kPa to 150 kPa. Claim 19 was abandoned upon payment of a registration fee. The method of claim 11, The heat treatment is a method of manufacturing a semiconductor device performed for 10 seconds to 20 seconds at a temperature condition of 950 ℃ to 1000 ℃ and O ₂ atmosphere conditions. Claim 20 was abandoned upon payment of a registration fee. The method of claim 11, Formation of the first polysilicon film, the second polysilicon film, the third polysilicon film, and the fourth polysilicon film is a single step of depositing the polysilicon film while varying the supply amount of the impurity source gas in the polysilicon film deposition chamber. Method of manufacturing a semiconductor device to be carried out. Claim 21 has been abandoned due to the setting registration fee. The method of claim 11, The counter-doping of the p-type impurity is performed such that the p-type impurity concentration in the polygate of the second region is 1.0 × 10 ¹⁷ atoms / cm 3 or less.

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