KR101095198B1 - Power Amplification Circuit - Google Patents

Abstract

The present invention relates to a power amplifier circuit, comprising: an amplifier for amplifying an input signal; A capacitance compensation unit connected in parallel with the amplifier to compensate for input capacitance; And an output unit which prevents breakdown of the amplification unit and outputs a signal amplified by the amplifying unit, and may improve linear characteristics, implement high output, and improve amplification efficiency.

Linearity, high power, high efficiency

Description

Power Amplification Circuit

The present invention relates to a power amplifier circuit.

The mobile communication terminal includes a power amplifier to amplify the power of a received signal or a transmitted signal.

In this case, the power amplifier generally amplifies the input signal using a power amplifier circuit composed of a transistor and a resistor.

In this power amplification circuit, a drain terminal of a transistor is connected to a resistor and an output terminal, a gate terminal is connected to an input terminal, and a source terminal is connected to ground.

However, such a conventional power amplifier circuit has a low linearity characteristic under the influence of the third harmonic when providing a low input voltage, and when a high input voltage is provided, the conventional power amplifier circuit is applied to higher order harmonics such as the fifth and seventh orders. Due to the additional generation of IMD (Intermodulation Distortion) component is a problem that the linearity characteristics are degraded.

The present invention devised to solve the above problems is an object of the present invention to improve the linear characteristics, and to provide a power amplifier circuit capable of satisfying high output and high efficiency in a wide band.

In order to achieve the above object, the power amplifier circuit according to an embodiment of the present invention includes an amplifier for amplifying an input signal; A capacitance compensation unit connected in parallel with the amplifier to compensate for input capacitance; And an output unit which prevents breakdown of the amplifier and outputs a signal amplified by the amplifier.

In the present invention, the amplification unit, the drain terminal is commonly connected to the output portion, the source terminals are commonly connected to the ground, the gate terminal is commonly connected to the input terminal to the input terminal to input an input signal input to the gate terminal N first transistors for amplifying to a level; N first capacitors respectively connected between the gate terminals of the N first transistors and the input terminal to block a DC component of the input signal; And N first bias units respectively providing gate biases to gate terminals of the N first transistors.

In the present invention, the N first transistors are formed to have the same line width.

In the present invention, the N first transistors are formed to have different line widths.

Further, in the present invention, the N first biasing units are connected between N capacitors and gate terminals of the N first transistors on one side thereof to prevent the input signal from going out, and on the other side of the N first bias units. N first bias resistors each connected to N first bias power supplies providing a one gate bias.

Further, in the present invention, the N first bias units provide the same gate bias to the gate terminals of the N first transistors.

The N first bias units may provide different gate biases to gate terminals of the N first transistors.

Further, in the present invention, the N first transistors have the same transconductance according to the gate biases provided from the N first bias units.

Further, in the present invention, the N first transistors have different transconductances according to gate biases provided from the N first bias units.

Further, in the present invention, the N first transistors are configured as NMOSFETs.

In the present invention, the capacitance compensator is configured to compensate for the input capacitance changed according to the transconductance characteristics of the N first transistors and the first bias provided to the gate terminals of the N first transistors, respectively. A second transistor connected in parallel with the N first transistors to form a CMOS structure with one transistor; A second capacitor connected between the gate terminal and the input terminal of the second transistor to block a DC component among the input signal components provided to the gate terminal of the second transistor at the input terminal; A third capacitor connected between the common terminal of the source terminals of the N first transistors and the source terminal of the second transistor to block a direct current component of a power source provided to the source terminal of the second transistor; And a second bias unit configured to provide a gate bias to the gate terminal of the second transistor.

In the present invention, the second transistor is characterized in that it is composed of a PMOSFET.

In the present invention, the drain terminal of the second transistor is connected to a driving power source or in a floating state.

In the present invention, the second capacitor and the third capacitor have the same capacitance as that of the first capacitor.

In addition, in the present invention, the second bias unit is connected between one side of the second capacitor and the gate terminals of the second transistor to prevent the input signal input through the input terminal to the outside, the other side of the second gate bias And a second bias resistor connected to a second bias power source providing a.

Further, in the present invention, the first bias portion and the second bias portion adjusts the gate bias according to an operation mode to simultaneously provide the gate bias to the gate terminals of the N first transistors and the gate terminals of the second transistor. It features.

Further, in the present invention, the first biasing portion and the second biasing portion simultaneously control the gate biases which are downwardly adjusted than the gate biases of the intermediate frequency mode in the high frequency mode to the gate terminals of the N first transistors and the gate terminals of the second transistors. In the low frequency mode, the gate bias adjusted upwardly than the intermediate frequency mode is simultaneously provided to the gate terminals of the N first transistors and the gate terminals of the second transistor.

The output unit may include a transistor having a drain terminal connected to a driving power source and an output terminal in common, and a source terminal connected to the amplifying unit to form a cascode structure with the amplifier; And a bias unit configured to provide a gate bias to the gate terminal of the transistor.

In the present invention, the transistor is characterized by consisting of NMOSFET.

Prior to this, the terms or words used in this specification and claims are not to be interpreted in a conventional, dictionary sense, and the inventors will appropriately define the concept of terms in order to best explain their invention in the best way possible. It should be interpreted as meaning and concept corresponding to the technical idea of the present invention based on the principle that it can.

According to the present invention, it is possible to effectively reduce the amount of change in input capacitance contributing to the nonlinear characteristics by connecting the PMOSFET with the NMOSFET and the CMOS structure, thereby improving the linear characteristics of the power amplifier circuit, and reducing the transconductance of N NMOSFETs connected in parallel. The nonlinear characteristics of the transconductance can be reduced more effectively by differently forming or increasing or decreasing the gate biases provided to the gate terminals of the N NMOSFETs, thereby improving the linear characteristics of the power amplifier circuit.

The power amplification circuit according to the embodiment of the present invention maintains the linear characteristics of the power amplification circuit because the gate biases of the N NFETs connected in parallel and the gate biases of the PMOSFETs are simultaneously adjusted when switching from one band to the other. Since the NMOSFET amplifying the input signal is formed in a stack structure, smooth switching is possible even when a large signal is input, so that the high output characteristics of the power amplifier circuit can be realized, and the gate bias is adjusted for each operation mode, As a result, different gate biases are provided to the gate terminals of the NMOSFET and the PMOSFET, thereby improving the amplification efficiency of the power amplifier circuit.

The objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and preferred embodiments in conjunction with the accompanying drawings. In the present specification, when adding reference numerals to the components of each drawing, it should be noted that the same components as possible, even if displayed on the other drawings have the same number as possible. In addition, in describing the present invention, if it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing a power amplification circuit according to an embodiment of the present invention.

As shown in FIG. 1, the power amplification circuit according to an embodiment of the present invention includes an amplifying unit 10 for amplifying an input signal RF_in and the amplifying unit for compensating for capacitance of the amplifying unit 10. A capacitance compensator 20 connected in parallel with the unit 10 and an output unit 30 which prevents breakdown of the amplifier 10 and outputs a signal amplified by the amplifier 10. ).

The amplifier 10 amplifies the input signal RF_in input through the input terminal RF_in to a predetermined level.

The amplifier 10 includes N first transistors Mcs1, ..., Mcsn, N first capacitors C1, ..., Cn, and N first bias units Vcs1, ... , Vcsn).

N first transistors Mcs1, ..., Mcsn are connected to an output unit 30 by connecting drain terminals in common to amplify the input signal RF_in provided to a gate terminal to a predetermined level. Terminals are commonly connected to ground GND, and gate terminals are respectively connected to the input terminal RF_in through N first capacitors C1, ..., Cn.

The N first transistors Mcs1, ..., Mcsn connected in parallel as described above may be formed to have the same line width or may have different line widths.

That is, when the N first transistors Mcs1 to Mcsn are formed to have the same line width, the N first transistors Mcs1 to Mcsn have the same transconductance. When the N first transistors Mcs1 to Mcsn are formed to have different line widths, the N first transistors Mcs1 to Mcsn have different transconductances.

The N first transistors Mcs1 to Mcsn may not only have different transconductances even if they have the same line width, but may have the same transconductance even if they have different line widths.

That is, although the N first transistors Mcs1,..., Mcsn are formed to have the same line width, the N first transistors Mcs1,... The N first transistors Mcs1, Mcsn may have different transconductances when different gate biases are provided to the gate terminals of... Mcsn.

In addition, although the N first transistors Mcs1 to Mcsn are formed to have different line widths, the N first transistors Mcs1 to N first bias units Vcs1 to Vcsn may be formed. ..., may have the same transconductance by the bias provided to the gate terminals of Mcsn).

Accordingly, the N first transistors Mcs1, ..., Mcsn may operate only in one of the saturation region and the sub-threshold region, or may operate in both the saturation region and the sub-threshold region.

These N first transistors Mcs1, ..., Mcsn are composed of NMOSFETs as shown in FIG.

The N first capacitors C1, ..., Cn are connected between the input terminal RF_in and the gate terminals of the N first transistors Mcs1, ..., Mcsn, respectively, so that the N first capacitors C1, ..., Cn are connected to each other. DC-blocking of only the DC component among the input signal RF_in components provided to the gate terminals of the first transistors Mcs1, ..., Mcsn.

These N first capacitors C1, ..., Cn have the same capacitance.

The N first bias units Vcs1 to Vcsn serve to provide a gate bias to the gate terminals of the N first transistors Mcs1 to Mcsn, and the input terminal RF_in. N first bias resistors Rcs1,..., And Rcsn which prevent the RF input signal inputted through the device from going out.

In this case, the N first bias resistors Rcs1, ..., Rcsn have one side of the N capacitors C1, ..., Cn and the N first transistors Mcs1, ..., Mcsn. Respectively connected between the gate terminals, and the other side thereof is respectively connected to N first bias power supplies that provide N first gate biases.

The N first bias units Vcs1 to Vcsn adjust the gate biases to correspond to the operation mode of the power amplifier circuit according to the embodiment of the present invention to adjust the N first transistors Mcs1 to ..., Mcsn) to the gate terminal.

That is, when the power amplifier circuit according to the embodiment of the present invention is to operate in the high frequency mode, the N first bias units Vcs1, ..., Vcsn are in the middle frequency mode. ), The gate bias of the N first transistors (Mcs1, ..., Mcsn) is adjusted to be lower than the bias provided to the gate terminals of the N first transistors (Mcs1, ..., Mcsn). In the case of each of the plurality of N transistors, the upper limit of the bias voltage is higher than the bias provided to the gate terminals of the N first transistors Mcs1, ..., Mcsn in the intermediate frequency mode. Gate bias is provided to the gate terminals of the N first transistors Mcs1, ..., Mcsn, respectively.

In this case, the N first bias units Vcs1 to Vcsn provide gate biases having the same size to gate terminals of the N first transistors Mcs1 to Mcsn, or have different sizes. Provide a gate bias.

As a result, the N first transistors Mcs1, ..., Mcsn have different transconductances or have the same transconductance according to the magnitude of the bias provided to the gate terminal.

The N first bias units Vcs1 to Vcsn simultaneously adjust the bias sizes and provide them to the gate terminals of the N first transistors Mcs1 to Mcsn.

The capacitance compensator 20 is provided to the transconductance characteristics of the N first transistors Mcs1 to Mcsn and the gate terminals of the N first transistors Mcs1 to Mcsn, respectively. Parallel with the N first transistors Mcs1, Mcsn to form a CMOS structure with the N first transistors Mcs1, Mcsn to compensate for the input capacitance that varies with bias Of the second transistor Mp connected to each other, the second capacitor C21 connected between the gate terminal of the second transistor Mp and the input terminal RF_in, and the N first transistors Mcs1, ..., Mcsn And a third capacitor C31 connected between the common terminal of the source terminals and the source terminal of the second transistor Mp, and a second bias unit Vmp that provides a gate bias to the gate terminal of the second transistor Mp. do.

In the capacitance compensator 20, the second transistor Mp is configured as a PMOSFET, and the drain terminal of the second transistor Mp is connected to a driving power source or in a floating state, and a second capacitor C21 and the third capacitor C31 have the same capacitance as the first capacitors C1, ..., Cn.

In this case, the second capacitor C21 blocks only a DC component among the input signal RF_in components provided to the gate terminal of the second transistor Mp at the input terminal RF_in, and the third capacitor C31. The second block cuts the DC component of the power supply (for example, the ground power supply GND) provided to the source terminal of the second transistor Mp.

The second bias unit Vmp serves to provide a gate bias to the gate terminal of the second transistor Mp and prevents the RF input signal input through the input terminal RF_in from going out. It includes a bias resistor (Rmp).

In this case, one side of the second bias resistor Rmp is connected between the second terminal C21 and the gate terminals of the second transistor Mp, and the other side of the second bias resistor Rmp is connected to a second bias power supply that provides a second gate bias. Connected.

The second bias unit Vmp may adjust the gate bias to correspond to an operation mode of the power amplifier circuit according to the embodiment of the present invention, such as the N first bias units Vcs1 to Vcsn. It is provided to the gate terminal of two transistors Mp.

That is, when the second bias unit Vmp is to operate the power amplifier circuit in the high frequency mode according to the embodiment of the present invention, the second bias unit Vmp is connected to the gate terminal of the second transistor Mp in the middle frequency mode. The gate bias of the second transistor Mp is adjusted downward to the gate terminal of the second transistor Mp, and when operated in a low frequency mode, the gate bias of the gate transistor of the second transistor Mp is provided in an intermediate frequency mode. The gate bias adjusted upward rather than the biased bias voltage is provided to the gate terminal of the second transistor Mp.

The second biasing unit Vmp simultaneously adjusts the bias size with the N first biasing units Vcs1 to Vcsn, and adjusts the gate bias adjusted according to the operation mode of the power amplifier circuit. The N first bias units Vcs1 to Vcsn are provided to the gate terminal of the second transistor Mp at the same time.

That is, the second bias unit Vmp downwards the gate bias provided by the first bias units Vcs1 to Vcsn to the gate terminals of the N first transistors Mcs1 to Mcsn. When adjusting, the gate bias provided to the gate terminal of the second transistor Mp is adjusted downward, and the first bias units Vcs1, ..., Vcsn are N first transistors Mcs1, ..., When the gate bias provided to the gate terminal of Mcsn) is adjusted upward, the gate bias provided to the gate terminal of the second transistor Mp is adjusted upward.

As a result, even in the multi-band power amplifier circuit according to an embodiment of the present invention can maintain the linear characteristics.

The output unit 30 is connected to form the cascode structure with the amplifier 10 to provide an isolation characteristic between the input terminal RF_in and the output terminal RF_out and provide the amplifier 10. The breakdown of the N first transistors Mcs1, ..., Mcsn constituting each other is prevented, and the signal amplified by the amplifier 10 is output.

The output unit 30 has a drain terminal connected to the driving power supply VDD and the output terminal RF_out in common, a gate terminal connected to the third bias unit Vcg, and a source terminal connected to the N first transistors ( And a third transistor (Mcg) commonly connected to the drain terminals of Mcs1, ..., Mcsn, and the third transistor (Mcg) is composed of an NMOSFET.

In general, the linear characteristics of the power amplifier are input capacitance according to the transconductance characteristics and gate bias conditions of the active elements (in the present invention, the first transistors (Mcs1, ..., Mcsn) and the second transistor (Mp) of the CMOS structure) Not only are they greatly affected by the components, but the first transistors (Mcs1, ..., Mcsn), which are common source transistors to which the input signal is input, are caused by non-linear increase and decrease of the transconductance component.

However, since the power amplifier circuit according to the embodiment of the present invention connects the second transistor Mp composed of the PMOSFET and the amplifier 10 composed of the NMOSFET in a CMOS structure, the input capacitance contributes to the nonlinear characteristic as shown in FIG. 2. Since the amount of change is effectively reduced as well as the total capacitance, it is possible to improve the linear characteristics of the power amplification circuit.

In addition, the power amplification circuit according to an embodiment of the present invention may form different transconductances of the N first transistors Mcs1, ..., Mcsn connected in parallel, or N first transistors Mcs1, ..., By differently increasing and decreasing the gate bias provided to the gate terminal of Mcsn), the nonlinear characteristics of the transconductance can be reduced more effectively, thereby improving the linear characteristics of the power amplifier circuit.

In addition, the power amplification circuit according to an embodiment of the present invention is the gate bias and the second transistor Mp of the N first transistors Mcs1, ..., Mcsn connected in parallel when switching from one band to the other band. Since the gate bias of is controlled at the same time, it is possible to maintain the linear characteristics of the power amplifier circuit.

In the power amplifier circuit according to the embodiment of the present invention, the amplifier 10 amplifies the input signal, that is, the first transistors Mcs1, ..., Mcsn are formed in a stack structure (ie, in parallel) instead. Even when a large signal is input, smooth switching is possible, thereby realizing the high output characteristics of the power amplifier circuit.

In addition, the power amplifier circuit according to the embodiment of the present invention adjusts the gate bias for each operation mode, and different gate bias according to each mode, the first transistor (Mcs1, ..., Mcsn) and the second transistor Since it is provided to the gate terminal of (Mp), it is possible to improve the amplification efficiency of the power amplifier circuit.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art that various modifications of the present invention without departing from the spirit and scope of the invention described in the claims below And can be changed.

1 is a view showing a power amplification circuit according to an embodiment of the present invention.

2 is a diagram illustrating a change in input capacitance according to a gate-source voltage.

<Description of the symbols for the main parts of the drawings>

10: amplification unit 20: capacitance compensation unit

30: amplification unit

Claims (19)

delete An amplifier for amplifying an input signal; A capacitance compensation unit connected in parallel with the amplifier to compensate for input capacitance; And An output unit which prevents breakdown of the amplifier and outputs a signal amplified by the amplifier, The amplification unit, N terminals for amplifying an input signal inputted to the gate terminal with a drain terminal commonly connected to the output part, a source terminal commonly connected to the ground, and a gate terminal connected to the input terminal in common at an input terminal to a predetermined level 1 transistor; N first capacitors respectively connected between the gate terminals of the N first transistors and the input terminal to block a DC component of the input signal; And And N first bias parts respectively providing gate biases to gate terminals of the N first transistors. The method according to claim 2, And the N first transistors are formed to have the same line width. The method according to claim 2, And the N first transistors are formed to have different line widths. The method according to claim 2, One side of the N first bias parts may be connected between the N capacitors and the gate terminals of the N first transistors to prevent the input signal from going out, and the other side of the N first bias parts may provide N first gate biases. And N first bias resistors respectively connected to the N first bias power supplies. The method according to claim 2, And the N first bias parts provide the same gate bias to the gate terminals of the N first transistors. The method according to claim 2, And the N first bias parts provide different gate biases to gate terminals of the N first transistors. The method according to claim 2, And the N first transistors have the same transconductance according to the gate biases provided from the N first bias units. The method according to claim 2, And the N first transistors have different transconductances according to gate biases provided from the N first bias units. The method according to claim 2, And said N first transistors comprise NMOSFETs. The method according to claim 2, The capacitance compensation unit, A CMOS structure is formed with the N first transistors to compensate for the input capacitance which is changed according to the transconductance characteristics of the N first transistors and the first bias provided to the gate terminals of the N first transistors, respectively. A second transistor coupled in parallel with the N first transistors; A second capacitor connected between the gate terminal and the input terminal of the second transistor to block a DC component among the input signal components provided to the gate terminal of the second transistor at the input terminal, A third capacitor connected between the common terminal of the source terminals of the N first transistors and the source terminal of the second transistor to block a direct current component of a power source provided to the source terminal of the second transistor; And And a second bias unit configured to provide a gate bias to the gate terminal of the second transistor. The method of claim 11, And said second transistor comprises a PMOSFET. The method of claim 11, And the drain terminal of the second transistor is connected to a driving power source or in a floating state. The method of claim 11, And the second capacitor and the third capacitor have the same capacitance as the first capacitor. The method of claim 11, The second bias unit is connected to one side between the second capacitor and the gate terminals of the second transistor to prevent the input signal input through the input terminal to the outside, the other side is provided with a second gate bias And a second bias resistor coupled to the bias power supply. The method of claim 11, Wherein the first biasing unit and the second biasing unit adjust the gate bias according to an operation mode to simultaneously provide the gate bias to the gate terminals of the N first transistors and the gate terminals of the second transistors. Circuit. The method of claim 11, In the high frequency mode, the first bias part and the second bias part simultaneously provide a gate bias which is controlled to be lower than the gate bias of the intermediate frequency mode to the gate terminals of the N first transistors and the gate terminals of the second transistor, and in a low frequency mode. The power amplifying circuit is characterized in that to simultaneously provide a gate bias adjusted up than the intermediate frequency mode to the gate terminals of the N first transistor and the gate terminals of the second transistor at the same time. An amplifier for amplifying an input signal; A capacitance compensation unit connected in parallel with the amplifier to compensate for input capacitance; And An output unit which prevents breakdown of the amplifier and outputs a signal amplified by the amplifier, The output unit, A transistor having a drain terminal connected to a driving power source and an output terminal in common to form a cascode structure with the amplifier, and a source terminal connected to the amplifier; And And a bias unit for providing a gate bias to the gate terminal of the transistor. 19. The method of claim 18, And the transistor comprises an NMOSFET.

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