KR101095044B1 - Method for seperating mask layout - Google Patents

Abstract

PURPOSE: A method for separating a mask layout is provided to increase DOF(Depth of Focus), EL(Energy Latitude), and MEF(Mask Error Factor) process margins, thereby enhancing the properties and reliability of a device. CONSTITUTION: A design pattern layout is divided into first and second backup mask layouts(S100). The first backup mask layout is combined with an under-sized second backup mask layout to determine a first mask layout(S110). The second backup mask layout is combined with an under-sized first backup mask layout to determine a second mask layout(S120). Stitching, OPC(Optical Proximity Correction), and MRC(Mask Rule Check) are performed on the first and second mask layouts. The first and second mask layouts are verified(S140).

Description

How to separate mask layouts {METHOD FOR SEPERATING MASK LAYOUT}

The present invention relates to a mask layout separation method. More specifically, the present invention relates to a mask layout separation method for applying in a double patterning technology (DPT) process.

As the degree of integration of semiconductor devices increases, it is required to form finer patterns in photolithography processes. The photolithography process is a process for forming a circuit pattern on a semiconductor wafer and consists of processes of coating, exposing and developing photoresist. Such photolithography processes require high resolution and optimal depth of focus (DOF) as the integration density of semiconductor devices increases.

However, as the pattern becomes smaller and the size of the pattern becomes smaller and approaches the limit of the optical resolution, the deformation of the pattern may occur due to diffraction and interference of light caused by surrounding patterns. As described above, the influence from adjacent peripheral patterns during exposure is called an optical proximity effect (OPE). Therefore, in order to prevent such an optical proximity effect, an optical proximity correction (OPC) method of compensating for optical proximity by adjusting a width of a pattern or adding an auxiliary pattern is used.

1 illustrates a mask layout separation method for optical proximity correction according to the prior art, and FIGS. 2A and 2B illustrate a mask layout manufactured according to the flowchart of FIG. 1. Referring to FIGS. 1, 2A, and 2B, a first mask layout and a second mask layout manufactured to perform the DPT process will be described below.

First, a step of separating the design pattern layout (10 in FIG. 2A) into the first mask layout (30 in FIG. 2B (iii)) and the second mask layout (50 in FIG. 2B (ii)) is performed (S10). Separating the design pattern layout into each mask layout proceeds based on the pitch of the patterns to be assigned to each mask layout.

For example, when the first pattern 10a, the second pattern 10b, the third pattern 10c, and the fourth pattern 10d are included in the design pattern layout 10 as illustrated in FIGS. 2A and 2B. The first mask layout 30 includes a first pattern 10a and a third pattern 10c, and the second mask layout 40 includes a second pattern 10b and a fourth pattern 10d. Are separated.

Next, stitching, an optical proximity effect correction process, and a mask rule checking process are performed on the first mask layout (30 in FIG. 2B (i)) and the second mask layout (50 in FIG. 2B (ii)), respectively. (S20). Thereafter, a step of verifying the first mask layout (30 in FIG. 2B (iii)) and the second mask layout (50 in FIG. 2B (ii)) in which the optical proximity effect correction process is performed is performed (S30).

Then, the pattern image to be implemented on the wafer is simulated by combining the verified first mask layout (30 in FIG. 2B (iii)) and the second mask layout (50 in FIG. 2B (ii)). Next, the first mask layout (30 in FIG. 2B (iii)) and the second mask layout (50 in FIG. 2B (ii)) are determined by determining whether the intended pattern is correctly implemented in the design pattern layout through simulation. do.

In the above-mentioned prior art, in the step of dividing the design pattern layout into the respective mask layouts, portions having pitches less than or equal to the resolution are divided and separated into simply the first mask layout and the second mask layout. In this case, both of the first mask layout and the second mask layout have a problem in that the photo process margin is weak and the resolution is lowered. In addition, there is a problem that the etching process margin is also weak because the etching bias is not uniform.

SUMMARY OF THE INVENTION The present invention is to solve the above-described problems, and after dividing the design pattern layout into a first preliminary mask layout and a second preliminary mask layout, the undersized pattern of each preliminary mask layout is a dummy of another mask layout. By using a pattern or assist pattern, an object of the present invention is to provide a mask layout separation method that can improve DOF, EL, and MEF margins, and uniformly etch bias to improve device characteristics and reliability.

In order to achieve the above object, the present invention provides a method of separating a design pattern layout into a first preliminary mask layout and a second preliminary mask layout, and a first preliminary mask layout and an undersized second preliminary mask layout. Combining to form a first mask layout, and combining the second preliminary mask layout and the undersized first preliminary mask layout to form a second mask layout.

Furthermore, the design pattern layout may include a plurality of patterns having different sizes, and the design pattern layout may include a first pattern and a second pattern.

Here, the first preliminary mask layout includes a first pattern, and the second preliminary mask layout includes a second pattern. In the step of forming a first mask layout, the first mask layout includes a first pattern of the first preliminary mask layout and an undersized second pattern of the second preliminary mask layout. In the mask layout, the first pattern of the first preliminary mask layout is a main pattern, and the undersized second pattern of the second preliminary mask layout is an auxiliary pattern.

In the forming of the second mask layout, the second mask layout may include an undersized first pattern of the first preliminary mask layout and a second pattern of the second preliminary mask layout. In the second mask layout, the undersized first pattern of the first preliminary mask layout is an auxiliary pattern, and the second pattern of the second preliminary mask layout is a main pattern.

In this case, the main pattern of the first mask layout and the auxiliary pattern of the second mask layout overlap each other, and the main pattern of the second mask layout and the auxiliary pattern of the first mask layout overlap each other. do.

In addition, after the forming of the second mask layout, the optical proximity correction effect may be performed on the first mask layout and the second mask layout, and the method may further include verifying the first mask layout and the second mask layout. The verifying of the first mask layout and the second mask layout may include performing a simulation process using the first mask layout and the second mask layout to implement a pattern to be formed on a wafer. It is characterized by.

The mask layout separation method of the present invention has the following effects.

First, the margin of focus (DOF), energy latitude (EL), and mask error factor (MEF) process margins are improved, resulting in improved device characteristics and reliability.

Second, the etching bias uniformity is improved to provide an effect of improving the characteristics and reliability of the device.

1 is a flow chart illustrating a mask layout separation method according to the prior art.
2A and 2B are layout views illustrating a mask layout separation method according to the prior art.
3 is a flowchart illustrating a mask layout separation method according to the present invention.
4A to 4C are layout diagrams showing a mask layout separation method according to the present invention;

Hereinafter, an embodiment of a mask layout separation method according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a flowchart illustrating a mask layout separation method according to the present invention, and FIGS. 4A to 4C are layout diagrams illustrating a mask layout separation method according to the flowchart of FIG. 3.

Referring to FIGS. 3 and 4A to 4C, a mask layout separation method for a DPT process is as follows. First, a coloring process of separating the design pattern layout 100 into a first preliminary mask layout (110 of FIG. 4B) and a second preliminary mask layout (120 of FIG. 4B) is performed (S100). In this case, the coloring process is performed by applying a predetermined rule base, and the patterns included in the design pattern layout are colored with different colors so as to know in advance the pattern to be separated into each mask layout. Here, the coloring process is proceeded by a specific algorithm, based on the pitch of the patterns to be assigned to each mask layout.

For example, when the design pattern layout 100 including the first pattern 100a, the second pattern 100b, the third pattern 100c, and the fourth pattern 100d having different sizes is provided as shown in FIG. 4A. Based on the pitch of the patterns, the first preliminary mask layout 110 and the second preliminary mask layout 120 are separated as shown in FIG. 4B.

In this case, as shown in FIG. 4A, when the sizes of the first pattern 100a and the fourth pattern 100d are the same, and the sizes of the second pattern 100b and the third pattern 100c are the same, the sizes are different. The first preliminary mask layout 110 and the second preliminary mask layout 120 each including two types of patterns are separated. That is, the first preliminary mask layout 110 is separated to include the first pattern 100a and the third pattern 100c, and the second preliminary mask layout 120 includes the second pattern 100b and the fourth pattern ( 100d) are separated to include.

Next, the first mask layout 130 is determined by combining the first preliminary mask layout 110 and the undersized second preliminary mask layout 120 (S110). In this case, the undersized second preliminary mask layout 120 means reducing the size of patterns included in the second preliminary mask layout 120.

Referring to FIG. 4C, the first preliminary mask layout 110 is used as a reference, and the undersized second preliminary mask layout 120 is combined to form the first mask layout 130. That is, the first mask layout 130 includes the first pattern 100a and the third pattern 100c of the first preliminary mask layout 110, and the second pattern 100b of the second preliminary mask layout 120. ) And the fourth pattern 100d are undersized. Here, the first mask layout 130 uses the first pattern 100a and the third pattern 100c of the first preliminary mask layout 110 as the main pattern 130a, and the undersized second preliminary mask layout ( The second pattern 100b and the fourth pattern 100d of 120 are referred to as auxiliary patterns 130b. In this case, the auxiliary pattern 130b may be used as a dummy pattern or an assist pattern.

In addition, referring to FIG. 4C (ii), the second preliminary mask layout 120 is combined with the undersized first preliminary mask layout 110 as opposed to FIG. 4C (iii). 2 mask layout 140. That is, the second mask layout 140 includes the second pattern 100b and the fourth pattern 100d of the second preliminary mask layout 120, and the first pattern 100a of the first preliminary mask layout 110. ) And the third pattern 100c are undersized. Here, the second mask layout 140 uses the second pattern 100b and the fourth pattern 100d of the second preliminary mask layout 120 as the main pattern 140a, and the undersized first preliminary mask layout ( The first pattern 100a and the third pattern 100c of 110 are referred to as auxiliary patterns 140b. In this case, the auxiliary pattern 140b may be used as a dummy pattern or an assist pattern.

Next, stitching, optical proximity correction, and mask rule check (MRC) are performed on the first mask layout 130 and the second mask layout 140 formed as shown in FIG. 4C. (S130).

Here, stitching is a process necessary to prevent formation of a separate pattern even when a double exposure is performed by performing optical proximity correction on a portion where two patterns overlap when a pattern is divided into two patterns. to be.

In addition, the optical proximity effect correction is a process of correcting the layout of the target pattern in consideration of the optical proximity effect accompanying exposure or an etching bias accompanying the post-exposure etching process. The mask rule check is a process of verifying an optimization operation of the mask layout.

Next, the first mask layout and the second mask layout to which stitching, optical proximity correction and mask rule check (MRC) are applied are verified (S140). In this case, the verifying of the first mask layout and the second mask layout to which the optical proximity effect correction is applied may be performed on a wafer by performing a simulation process using the first mask layout and the second mask layout to which the optical proximity effect correction is applied. You can proceed by implementing the pattern.

In this case, the auxiliary patterns included in the first mask layout and the second mask layout may be used as dummy patterns or assist patterns. When used as an assist pattern, it is not formed as a pattern and thus does not affect the formation of the target pattern. On the other hand, when used as a dummy pattern is formed into a pattern. However, since the dummy pattern is an undersized pattern included in the exposure mask used for the subsequent secondary exposure, the dummy pattern does not affect the formation of the target pattern during the double exposure process. An exposure mask can be manufactured using the first mask layout and the second mask layout thus formed.

As described above, by dividing the design pattern layout into a first preliminary mask layout and a second preliminary mask layout, the undersized pattern of each preliminary mask layout is used by using dummy patterns or assist patterns of different mask layouts, so that DOF, EL In addition, the MEF margin can be improved and the etching bias can be made uniform to improve device characteristics and reliability.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims. Of the present invention.

100: design pattern layout 100a: first pattern
100b: second pattern 100c: third pattern
100d: fourth pattern 110: first preliminary mask layout
120: second preliminary mask layout 130: first mask layout
130a, 140a: main pattern 130b, 140b: auxiliary pattern
140: second mask layout

Claims (13)

Separating the design pattern layout into a first preliminary mask layout and a second preliminary mask layout;
Forming a first mask layout by combining the first preliminary mask layout and the undersized second preliminary mask layout, wherein a pattern included in the second preliminary mask layout is used as an auxiliary pattern; And
Forming a second mask layout by combining the second preliminary mask layout with the undersized first preliminary mask layout, wherein a pattern included in the first preliminary mask layout is used as an auxiliary pattern
Mask layout separation method comprising a. Claim 2 has been abandoned due to the setting registration fee. The method according to claim 1,
And the design pattern layout includes a plurality of patterns having different sizes. Claim 3 was abandoned when the setup registration fee was paid. The method according to claim 1,
And the design pattern layout comprises a first pattern and a second pattern. Claim 4 was abandoned when the registration fee was paid. The method according to claim 3,
And the first preliminary mask layout comprises the first pattern. Claim 5 was abandoned upon payment of a set-up fee. The method according to claim 3,
And the second preliminary mask layout comprises the second pattern. Claim 6 was abandoned when the registration fee was paid. The method according to claim 3,
In the step of forming the first mask layout,
And the first mask layout comprises an undersized second pattern of the first pattern of the first preliminary mask layout and the second preliminary mask layout. Claim 7 was abandoned upon payment of a set-up fee. The method according to claim 3,
In the first mask layout,
And wherein the first pattern of the first preliminary mask layout is a main pattern and the undersized second pattern of the second preliminary mask layout is an auxiliary pattern. Claim 8 was abandoned when the registration fee was paid. The method according to claim 3,
In the forming of the second mask layout,
And the second mask layout comprises an undersized first pattern of the first preliminary mask layout and a second pattern of the second preliminary mask layout. Claim 9 was abandoned upon payment of a set-up fee. The method according to claim 3,
In the second mask layout,
The undersized first pattern of the first preliminary mask layout is an auxiliary pattern, and the second pattern of the second preliminary mask layout is a main pattern. Claim 10 was abandoned upon payment of a setup registration fee. The method according to claim 7 or 9,
And a main pattern of the first mask layout and an auxiliary pattern of the second mask layout overlap each other. Claim 11 was abandoned upon payment of a setup registration fee. The method according to claim 7 or 9,
And a main pattern of the second mask layout and an auxiliary pattern of the first mask layout overlap each other. Claim 12 was abandoned upon payment of a registration fee. The method according to claim 1,
After the forming of the second mask layout,
Performing an optical proximity correction effect on the first mask layout and the second mask layout; And
Verifying by comparing the design pattern layout with the first mask layout and the second mask layout
Mask layout separation method characterized in that it further comprises. Claim 13 was abandoned upon payment of a registration fee. The method of claim 12,
Verifying by comparing the design pattern layout with the first mask layout and the second mask layout
And performing a simulation process using the first mask layout and the second mask layout to implement a pattern to be formed on a wafer.

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