KR101093784B1 - 리플레이 메커니즘을 구비한 로드 저장 유닛 - Google Patents

리플레이 메커니즘을 구비한 로드 저장 유닛 Download PDF

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KR101093784B1
KR101093784B1 KR1020057010852A KR20057010852A KR101093784B1 KR 101093784 B1 KR101093784 B1 KR 101093784B1 KR 1020057010852 A KR1020057010852 A KR 1020057010852A KR 20057010852 A KR20057010852 A KR 20057010852A KR 101093784 B1 KR101093784 B1 KR 101093784B1
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South Korea
Prior art keywords
storage unit
load storage
load
address
operations
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KR1020057010852A
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Korean (ko)
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KR20060021281A (ko
Inventor
마이클 에이. 필리포
제임스 케이. 피켓
벤자민 티. 샌더
라마 에스. 고팔
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Investigating Or Analysing Biological Materials (AREA)
KR1020057010852A 2003-06-10 2004-06-02 리플레이 메커니즘을 구비한 로드 저장 유닛 Expired - Lifetime KR101093784B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/458,457 2003-06-10
US10/458,457 US7165167B2 (en) 2003-06-10 2003-06-10 Load store unit with replay mechanism
PCT/US2004/017096 WO2004111839A1 (en) 2003-06-10 2004-06-02 Load store unit with replay mechanism

Publications (2)

Publication Number Publication Date
KR20060021281A KR20060021281A (ko) 2006-03-07
KR101093784B1 true KR101093784B1 (ko) 2011-12-19

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ID=33510583

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Application Number Title Priority Date Filing Date
KR1020057010852A Expired - Lifetime KR101093784B1 (ko) 2003-06-10 2004-06-02 리플레이 메커니즘을 구비한 로드 저장 유닛

Country Status (8)

Country Link
US (1) US7165167B2 (enExample)
EP (1) EP1644823B1 (enExample)
JP (1) JP5091481B2 (enExample)
KR (1) KR101093784B1 (enExample)
CN (1) CN100367196C (enExample)
DE (1) DE602004010265T2 (enExample)
TW (1) TWI352311B (enExample)
WO (1) WO2004111839A1 (enExample)

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US20050228971A1 (en) * 2004-04-08 2005-10-13 Samra Nicholas G Buffer virtualization
US7415597B2 (en) * 2004-09-08 2008-08-19 Advanced Micro Devices, Inc. Processor with dependence mechanism to predict whether a load is dependent on older store
US20100070730A1 (en) * 2008-09-17 2010-03-18 Sebastian Pop Minimizing memory access conflicts of process communication channels
US9996348B2 (en) * 2012-06-14 2018-06-12 Apple Inc. Zero cycle load
CN103744800B (zh) * 2013-12-30 2016-09-14 龙芯中科技术有限公司 面向重放机制的缓存操作方法及装置
US11068271B2 (en) 2014-07-28 2021-07-20 Apple Inc. Zero cycle move using free list counts
WO2016097791A1 (en) * 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Apparatus and method for programmable load replay preclusion
US9645827B2 (en) * 2014-12-14 2017-05-09 Via Alliance Semiconductor Co., Ltd. Mechanism to preclude load replays dependent on page walks in an out-of-order processor
US10387320B2 (en) * 2017-05-12 2019-08-20 Samsung Electronics Co., Ltd. Integrated confirmation queues
US10606603B1 (en) * 2019-04-08 2020-03-31 Ye Tao Methods and apparatus for facilitating a memory mis-speculation recovery
US11200062B2 (en) 2019-08-26 2021-12-14 Apple Inc. History file for previous register mapping storage and last reference indication
US10983801B2 (en) * 2019-09-06 2021-04-20 Apple Inc. Load/store ordering violation management
US11416254B2 (en) 2019-12-05 2022-08-16 Apple Inc. Zero cycle load bypass in a decode group
US11615043B2 (en) 2020-01-02 2023-03-28 Texas Instruments Incorporated Systems, methods, and apparatus to enable data aggregation and adaptation in hardware acceleration subsystems
US11360773B2 (en) 2020-06-22 2022-06-14 Microsoft Technology Licensing, Llc Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching
US11074077B1 (en) * 2020-06-25 2021-07-27 Microsoft Technology Licensing, Llc Reusing executed, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-execution
US11175917B1 (en) 2020-09-11 2021-11-16 Apple Inc. Buffer for replayed loads in parallel with reservation station for rapid rescheduling
US11983538B2 (en) * 2022-04-18 2024-05-14 Cadence Design Systems, Inc. Load-store unit dual tags and replays

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030088760A1 (en) 1999-12-30 2003-05-08 Chowdhury Muntaquim F. Method and apparatus for maintaining processor ordering

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US5581719A (en) * 1992-11-12 1996-12-03 Digital Equipment Corporation Multiple block line prediction
US5828868A (en) * 1996-11-13 1998-10-27 Intel Corporation Processor having execution core sections operating at different clock rates
US6385715B1 (en) * 1996-11-13 2002-05-07 Intel Corporation Multi-threading for a processor utilizing a replay queue
US5966544A (en) * 1996-11-13 1999-10-12 Intel Corporation Data speculatable processor having reply architecture
US6163839A (en) * 1998-09-30 2000-12-19 Intel Corporation Non-stalling circular counterflow pipeline processor with reorder buffer
CN1210649C (zh) 2000-01-03 2005-07-13 先进微装置公司 能够发送及重新发送附属链接的排程器、包括该排程器的处理器以及排程方法
US6651161B1 (en) * 2000-01-03 2003-11-18 Advanced Micro Devices, Inc. Store load forward predictor untraining
DE10085438B4 (de) * 2000-02-14 2006-01-05 Intel Corporation, Santa Clara Prozessor mit Wiederholarchitektur mit schnellen und langsamen Wiederholpfaden
US6877086B1 (en) 2000-11-02 2005-04-05 Intel Corporation Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter
JP3729064B2 (ja) * 2000-11-29 2005-12-21 日本電気株式会社 データ依存関係検出装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030088760A1 (en) 1999-12-30 2003-05-08 Chowdhury Muntaquim F. Method and apparatus for maintaining processor ordering

Also Published As

Publication number Publication date
US7165167B2 (en) 2007-01-16
EP1644823B1 (en) 2007-11-21
JP5091481B2 (ja) 2012-12-05
EP1644823A1 (en) 2006-04-12
US20040255101A1 (en) 2004-12-16
TW200508964A (en) 2005-03-01
WO2004111839A1 (en) 2004-12-23
DE602004010265T2 (de) 2009-05-07
JP2007503661A (ja) 2007-02-22
CN1806226A (zh) 2006-07-19
CN100367196C (zh) 2008-02-06
TWI352311B (en) 2011-11-11
DE602004010265D1 (de) 2008-01-03
KR20060021281A (ko) 2006-03-07

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