CN100367196C - 具有重放机制的微处理器、计算机系统以及方法 - Google Patents

具有重放机制的微处理器、计算机系统以及方法 Download PDF

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Publication number
CN100367196C
CN100367196C CNB2004800162265A CN200480016226A CN100367196C CN 100367196 C CN100367196 C CN 100367196C CN B2004800162265 A CNB2004800162265 A CN B2004800162265A CN 200480016226 A CN200480016226 A CN 200480016226A CN 100367196 C CN100367196 C CN 100367196C
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China
Prior art keywords
store unit
data
load store
internal memory
address
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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CNB2004800162265A
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English (en)
Chinese (zh)
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CN1806226A (zh
Inventor
M·A·菲利波
J·K·皮克特
B·T·桑德尔
R·S·戈帕尔
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication date
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Publication of CN1806226A publication Critical patent/CN1806226A/zh
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Publication of CN100367196C publication Critical patent/CN100367196C/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Investigating Or Analysing Biological Materials (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CNB2004800162265A 2003-06-10 2004-06-02 具有重放机制的微处理器、计算机系统以及方法 Expired - Lifetime CN100367196C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/458,457 2003-06-10
US10/458,457 US7165167B2 (en) 2003-06-10 2003-06-10 Load store unit with replay mechanism

Publications (2)

Publication Number Publication Date
CN1806226A CN1806226A (zh) 2006-07-19
CN100367196C true CN100367196C (zh) 2008-02-06

Family

ID=33510583

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004800162265A Expired - Lifetime CN100367196C (zh) 2003-06-10 2004-06-02 具有重放机制的微处理器、计算机系统以及方法

Country Status (8)

Country Link
US (1) US7165167B2 (enExample)
EP (1) EP1644823B1 (enExample)
JP (1) JP5091481B2 (enExample)
KR (1) KR101093784B1 (enExample)
CN (1) CN100367196C (enExample)
DE (1) DE602004010265T2 (enExample)
TW (1) TWI352311B (enExample)
WO (1) WO2004111839A1 (enExample)

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US20050228971A1 (en) * 2004-04-08 2005-10-13 Samra Nicholas G Buffer virtualization
US7415597B2 (en) * 2004-09-08 2008-08-19 Advanced Micro Devices, Inc. Processor with dependence mechanism to predict whether a load is dependent on older store
US20100070730A1 (en) * 2008-09-17 2010-03-18 Sebastian Pop Minimizing memory access conflicts of process communication channels
US9996348B2 (en) * 2012-06-14 2018-06-12 Apple Inc. Zero cycle load
CN103744800B (zh) * 2013-12-30 2016-09-14 龙芯中科技术有限公司 面向重放机制的缓存操作方法及装置
US11068271B2 (en) 2014-07-28 2021-07-20 Apple Inc. Zero cycle move using free list counts
WO2016097791A1 (en) * 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Apparatus and method for programmable load replay preclusion
US9645827B2 (en) * 2014-12-14 2017-05-09 Via Alliance Semiconductor Co., Ltd. Mechanism to preclude load replays dependent on page walks in an out-of-order processor
US10387320B2 (en) * 2017-05-12 2019-08-20 Samsung Electronics Co., Ltd. Integrated confirmation queues
US10606603B1 (en) * 2019-04-08 2020-03-31 Ye Tao Methods and apparatus for facilitating a memory mis-speculation recovery
US11200062B2 (en) 2019-08-26 2021-12-14 Apple Inc. History file for previous register mapping storage and last reference indication
US10983801B2 (en) * 2019-09-06 2021-04-20 Apple Inc. Load/store ordering violation management
US11416254B2 (en) 2019-12-05 2022-08-16 Apple Inc. Zero cycle load bypass in a decode group
US11615043B2 (en) 2020-01-02 2023-03-28 Texas Instruments Incorporated Systems, methods, and apparatus to enable data aggregation and adaptation in hardware acceleration subsystems
US11360773B2 (en) 2020-06-22 2022-06-14 Microsoft Technology Licensing, Llc Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching
US11074077B1 (en) * 2020-06-25 2021-07-27 Microsoft Technology Licensing, Llc Reusing executed, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-execution
US11175917B1 (en) 2020-09-11 2021-11-16 Apple Inc. Buffer for replayed loads in parallel with reservation station for rapid rescheduling
US11983538B2 (en) * 2022-04-18 2024-05-14 Cadence Design Systems, Inc. Load-store unit dual tags and replays

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5828868A (en) * 1996-11-13 1998-10-27 Intel Corporation Processor having execution core sections operating at different clock rates
US5966544A (en) * 1996-11-13 1999-10-12 Intel Corporation Data speculatable processor having reply architecture
WO2001050253A1 (en) * 2000-01-03 2001-07-12 Advanced Micro Devices, Inc. Scheduler capable of issuing and reissuing dependency chains
WO2001061480A1 (en) * 2000-02-14 2001-08-23 Intel Corporation Processor having replay architecture with fast and slow replay paths
US20020091914A1 (en) * 1996-11-13 2002-07-11 Merchant Amit A. Multi-threading techniques for a processor utilizing a replay queue

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5581719A (en) * 1992-11-12 1996-12-03 Digital Equipment Corporation Multiple block line prediction
US6163839A (en) * 1998-09-30 2000-12-19 Intel Corporation Non-stalling circular counterflow pipeline processor with reorder buffer
US6484254B1 (en) * 1999-12-30 2002-11-19 Intel Corporation Method, apparatus, and system for maintaining processor ordering by checking load addresses of unretired load instructions against snooping store addresses
US6651161B1 (en) * 2000-01-03 2003-11-18 Advanced Micro Devices, Inc. Store load forward predictor untraining
US6877086B1 (en) 2000-11-02 2005-04-05 Intel Corporation Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter
JP3729064B2 (ja) * 2000-11-29 2005-12-21 日本電気株式会社 データ依存関係検出装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5828868A (en) * 1996-11-13 1998-10-27 Intel Corporation Processor having execution core sections operating at different clock rates
US5966544A (en) * 1996-11-13 1999-10-12 Intel Corporation Data speculatable processor having reply architecture
US20020091914A1 (en) * 1996-11-13 2002-07-11 Merchant Amit A. Multi-threading techniques for a processor utilizing a replay queue
WO2001050253A1 (en) * 2000-01-03 2001-07-12 Advanced Micro Devices, Inc. Scheduler capable of issuing and reissuing dependency chains
WO2001061480A1 (en) * 2000-02-14 2001-08-23 Intel Corporation Processor having replay architecture with fast and slow replay paths

Also Published As

Publication number Publication date
US7165167B2 (en) 2007-01-16
EP1644823B1 (en) 2007-11-21
JP5091481B2 (ja) 2012-12-05
EP1644823A1 (en) 2006-04-12
US20040255101A1 (en) 2004-12-16
TW200508964A (en) 2005-03-01
KR101093784B1 (ko) 2011-12-19
WO2004111839A1 (en) 2004-12-23
DE602004010265T2 (de) 2009-05-07
JP2007503661A (ja) 2007-02-22
CN1806226A (zh) 2006-07-19
TWI352311B (en) 2011-11-11
DE602004010265D1 (de) 2008-01-03
KR20060021281A (ko) 2006-03-07

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