KR101087508B1 - Method of forming copper wiring in semiconductor device - Google Patents
Method of forming copper wiring in semiconductor device Download PDFInfo
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- KR101087508B1 KR101087508B1 KR1020030049049A KR20030049049A KR101087508B1 KR 101087508 B1 KR101087508 B1 KR 101087508B1 KR 1020030049049 A KR1020030049049 A KR 1020030049049A KR 20030049049 A KR20030049049 A KR 20030049049A KR 101087508 B1 KR101087508 B1 KR 101087508B1
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- 238000000034 method Methods 0.000 title claims abstract description 37
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 30
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 30
- 239000010949 copper Substances 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000010410 layer Substances 0.000 claims abstract description 48
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 18
- 239000001257 hydrogen Substances 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 10
- 238000007517 polishing process Methods 0.000 claims abstract description 10
- 239000000126 substance Substances 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- -1 hydrogen compound Chemical class 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000002356 single layer Substances 0.000 abstract description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 230000007261 regionalization Effects 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 4
- 230000002209 hydrophobic effect Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 230000000593 degrading effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 다마신 공정을 적용한 반도체 소자의 구리배선 형성방법에 관한 것으로, 다마신 패턴이 형성될 단층 또는 다층 구조의 저유전 층간 절연막을 형성하되, 캡핑층으로 FSG 물질을 증착하여 형성하고, FSG 캡핑층을 갖는 층간 절연막에 다마신 패턴 형성 공정, 구리층 매립 공정 및 화학적 기계적 연마 공정으로 구리배선을 형성하고, 연마 공정에 의해 잔류된 FSG 캡핑층을 수소(H) 분위기에서 열처리하여 표면에 HF를 형성시켜 제거하므로, 캡핑층이 없는 저유전 층간 절연막에 구리배선을 형성할 수 있어 소자의 성능을 향상시킬 수 있다.
The present invention relates to a copper wiring forming method of a semiconductor device to which the damascene process is applied, and to form a single-layer or multi-layer low dielectric interlayer insulating film on which a damascene pattern is to be formed, by depositing an FSG material with a capping layer, and forming an FSG. In the interlayer insulating film having the capping layer, copper wiring is formed by a damascene pattern formation process, a copper layer embedding process, and a chemical mechanical polishing process, and the remaining FSG capping layer is heat-treated in a hydrogen (H) atmosphere by the polishing process to HF on the surface. By forming and removing, the copper wiring can be formed on the low dielectric interlayer insulating film without a capping layer, thereby improving the performance of the device.
구리 배선, 저유전 절연막, FSG 캡핑층Copper Wiring, Low Dielectric Insulation, FSG Capping Layer
Description
도 1a 내지 1d는 본 발명의 실시예에 따른 반도체 소자의 구리배선 형성 방법을 설명하기 위한 소자의 단면도.
1A to 1D are cross-sectional views of a device for explaining a method of forming a copper wiring of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 기판 12: 층간 절연막11: substrate 12: interlayer insulating film
13: 캡핑층 14: 다마신 패턴13: capping layer 14: damascene pattern
15: 구리배선
15: copper wiring
본 발명은 다마신 공정을 적용한 반도체 소자의 구리배선 형성방법에 관한 것으로, 특히 저유전 절연막의 표면 결함 없이 저유전 절연막의 유전상수 값 보다 큰 캡핑층을 제거하여 유효 유전상수 값(effective k value)을 저하시킬 수 있는 반도체 소자의 구리배선 형성방법에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a copper wiring forming method of a semiconductor device to which the damascene process is applied. In particular, an effective k value is obtained by removing a capping layer larger than the dielectric constant value of a low dielectric insulating film without surface defects of the low dielectric insulating film. The present invention relates to a method for forming a copper wiring of a semiconductor device capable of lowering the amount of metal.
일반적으로, 반도체 산업이 초대규모 집적 회로(Ultra -Large Scale Integration; ULSI)로 옮겨가면서 소자의 지오메트리(geometry)가 서브-하프-마이크로(sub-half-micron) 영역으로 계속 줄어드는 반면, 성능 향상 및 신뢰도 측면에서 회로 밀도(circuit density)는 증가하고 있다. 이러한 요구에 부응하여, 반도체 소자의 금속 배선을 형성함에 있어서 구리는 알루미늄에 비해 녹는점이 높아 전기이동도(electro-migration; EM)에 대한 저항이 커서 소자의 신뢰성을 향상시킬 수 있고, 비저항이 낮아 신호전달 속도를 증가시킬 수 있어, 집적 회로(integration circuit)에 유용한 상호연결 재료(interconnection material)로 사용되고 있다.In general, as the semiconductor industry moves to Ultra-Large Scale Integration (ULSI), the geometry of the device continues to shrink to the sub-half-micron area, while improving performance and In terms of reliability, circuit density is increasing. In response to these demands, copper has a higher melting point than aluminum in forming metal wirings of semiconductor devices, and thus has high resistance to electro-migration (EM), thereby improving reliability of the device and having low specific resistance. The speed of signal transmission can be increased, making it a useful interconnection material for integration circuits.
금속 배선의 재료로 구리를 채용하면서, 반도체 소자의 구리 배선 형성 공정에 다마신 기법이 널리 적용되고 있으며, 구리배선과 이웃하는 구리배선과의 캐패시턴스(capacitance)의 상승을 방지하기 위하여, 다마신 패턴이 형성될 층간 절연막을 유전상수 값이 낮은 절연물(low-k dielectric)로 형성한다.While adopting copper as a material for metal wiring, the damascene technique is widely applied to the copper wiring formation process of semiconductor devices, and the damascene pattern is used to prevent an increase in capacitance between the copper wiring and the neighboring copper wiring. The interlayer insulating film to be formed is formed of an insulator having a low dielectric constant value.
그런데, 저유전 절연물은 소수성의(hydrophobic) 특성으로 인하여 화학적 기계적 연마 공정 후에 웨이퍼 표면에 결함(defect)이 발생되어 소자의 특성을 저하시켰다. 이를 해결하기 위하여 친수성의(hydrophilic) 산화물로 캡핑층을 형성하여 화학적 기계적 연마 공정 후에도 저유전 절연층이 노출되지 않게 하고 있다.However, low dielectric insulators have a hydrophobic characteristic, which causes defects on the surface of the wafer after chemical mechanical polishing, thereby degrading device characteristics. To solve this problem, a capping layer is formed of a hydrophilic oxide so that the low dielectric insulating layer is not exposed even after the chemical mechanical polishing process.
그러나, 이 방법은 캡핑층의 유전상수 값이 저유전 절연막의 유전상수 값보다 높아 최종 유효 유전상수 값을 증가시키는 결과를 초래하여 배선간 캐패시턴스 의 상승으로 소자의 성능을 저하시키는 문제가 있다. 화학적 기계적 연마 공정 후에 캡핑층을 제거하면 이 문제를 해결할 수 있지만, 소수성 특성을 갖는 저유전 절연막을 세정하는 세정액(cleaning solution)이 아직 개발되지 않아 캡핑층의 사용은 계속 될 수밖에 없는 실정이다.
However, this method has a problem that the value of the dielectric constant of the capping layer is higher than the value of the dielectric constant of the low dielectric insulating film, resulting in an increase in the final effective dielectric constant value, thereby degrading the performance of the device due to an increase in the capacitance between wirings. Removing the capping layer after the chemical mechanical polishing process can solve this problem, but since a cleaning solution for cleaning the low dielectric insulating film having hydrophobic properties has not yet been developed, the use of the capping layer has to be continued.
따라서, 본 발명은 저유전 절연막의 표면 결함 없이 저유전 절연막의 유전상수 값 보다 큰 캡핑층을 제거하여 유효 유전상수 값을 저하시킬 수 있는 반도체 소자의 구리배선 형성방법을 제공함에 그 목적이 있다.
Accordingly, an object of the present invention is to provide a method for forming a copper wiring of a semiconductor device capable of lowering an effective dielectric constant value by removing a capping layer larger than the dielectric constant value of the low dielectric insulating film without surface defects of the low dielectric insulating film.
이러한 목적을 달성하기 위한 본 발명의 실시예에 따른 반도체 소자의 구리배선 형성방법은 기판 상에 저유전 상수 값을 갖는 층간 절연막을 형성하는 단계; 상기 저유전 층간 절연막 상에 FSG 캡핑층을 형성하는 단계; 상기 FSG 캡핑층이 형성된 상기 층간 절연막을 다마신 공정으로 일부분 식각하여 다마신 패턴을 형성하는 단계; 상기 다마신 패턴이 충분히 매립되도록 구리층을 형성한 후, 화학적 기계적 연마 공정을 상기 FSG 캡핑층이 일정 두께 남을 때까지 실시하여 구리배선을 형성하는 단계; 및 수소 분위기에서 열처리하여 상기 FSG 캡핑층을 HF로 형성하여 제거하고, 이로 인하여 캡핑층이 없는 층간 절연막으로 되는 단계를 포함한다.According to an aspect of the present invention, there is provided a method of forming a copper wiring of a semiconductor device, the method including: forming an interlayer insulating film having a low dielectric constant on a substrate; Forming an FSG capping layer on the low dielectric interlayer insulating film; Forming a damascene pattern by partially etching the interlayer insulating layer on which the FSG capping layer is formed by a damascene process; Forming a copper layer to sufficiently fill the damascene pattern, and then performing a chemical mechanical polishing process until the FSG capping layer has a predetermined thickness to form a copper wiring; And heat treating in a hydrogen atmosphere to form and remove the FSG capping layer by HF, thereby forming an interlayer insulating film having no capping layer.
상기에서, 상기 캡핑층은 FSG 물질을 500 ~ 700 Å의 두께로 증착하여 형성 한다.In the above, the capping layer is formed by depositing the FSG material to a thickness of 500 ~ 700 Å.
상기 화학적 기계적 연마 공정은 상기 FSG 캡핑층이 30 ~ 100 Å의 두께로 남아있도록 실시한다.The chemical mechanical polishing process is performed such that the FSG capping layer remains at a thickness of 30 to 100 mm 3.
상기 수소 분위기 열처리는 N2나 Ar 불활성 가스가 약 0.1 내지 20 % 미만 함유된 수소 화합물을 이용하여 급속 열 공정 방식으로 200 ~ 400 ℃의 온도에서 3 ~ 30 초간 실시한다.The hydrogen atmosphere heat treatment is carried out for 3 to 30 seconds at a temperature of 200 ~ 400 ℃ in a rapid thermal process method using a hydrogen compound containing N 2 or less than 0.1% Ar inert gas.
상기 FSG 캡핑층은 상기 수소 분위기 열처리 동안 H이온과 불완전 F기가 반응하여 HF를 형성하여 제거된다.
The FSG capping layer is removed by forming HF by reacting H ions with an incomplete F group during the hydrogen atmosphere heat treatment.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명함으로써, 본 발명을 상세하게 설명한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예는 본 발명의 개시가 완전하도록 하며, 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, and to those skilled in the art the scope of the invention It is provided for complete information.
도 1a 내지 1d는 본 발명의 실시예에 따른 반도체 소자의 구리배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1D are cross-sectional views of devices for describing a method of forming copper wirings in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 소정의 결과물이 형성된 기판(11) 상에 저유전 상수 값을 갖는 층간 절연막(12)을 형성한다. 저유전 층간 절연막(12) 상에 캡핑층(13)을 형 성한다.Referring to FIG. 1A, an
상기에서, 층간 절연막(12)은 후속 공정으로 다마신 패턴이 형성되는 층으로 다마신 기법에 따라 단층 또는 다층 구조로 형성한다. 층간 절연막(12)은 배선과 배선 사이의 기생 캐패시터로 인한 문제를 해결하기 위해 저유전율을 갖는 물질로 형성하는데, 예를 들어, 유전 상수 값이 1.5 내지 4.5 대역의 SiO2 계열에 H, F, C, CH3 등이 부분적으로 결합되어 있는 물질이나, C-H를 기본 구조로 하는 SiLKTM제품, FlareTM제품 등의 유기 물질(organic material)이나, 이들 물질의 유전 상수 값을 낮추기 위해 이들 물질의 기공도(porosity)를 증가시킨 다공성(porous) 물질로 형성한다.In the above, the
캡핑층(13)은 FSG(Fluorinated Silicate Glass) 물질을 500 ~ 700 Å의 두께로 증착하여 형성한다.The
도 1b를 참조하면, 상부층으로 FSG 캡핑층(13)이 형성된 층간 절연막(12)을 다마신 공정으로 일부분 식각하여 다마신 패턴(14)을 형성한다.Referring to FIG. 1B, a
도 1c를 참조하면, 다마신 패턴(14)이 충분히 매립되도록 구리층을 형성한 후, 화학적 기계적 연마 공정을 FSG 캡핑층(13)이 얇게 예를 들어 100 Å 미만의 두께, 바람직하게는 30 ~ 100 Å의 두께로 남아있도록 실시하여 다마신 패턴(14) 내에 구리배선(15)을 형성한다. FSG 캡핑층(13)이 얇게 남아있는 상태에서 수소 분위기로 열처리(anneal)하고, 이로 인하여, 도 1d에 도시된 바와 같이, FSG 캡핑층(13)이 제거된다. 이후, 캡핑층(13)이 없는 저유전 층간 절연막(12) 상태로 통상의 후속 공정을 진행하게 된다.Referring to FIG. 1C, after the copper layer is formed so that the
상기에서, 수소 분위기 열처리는 순수 수소(pure H)보다는 N2나 Ar 등의 불활성 가스가 약 0.1 내지 20 % 미만 함유된 수소 화합물을 이용하여 급속 열 공정(RTP) 방식으로 200 ~ 400 ℃의 온도에서 3 ~ 30 초간 실시한다. 수소 분위기 열처리는 퍼니스(furnace) 방식으로 실시하여도 무방하다. 수소 분위기 열처리 동안 H이온이 FSG 캡핑층(13)의 불완전 F기(화학적 기계적 연마 공정으로 불완전 F기가 생성됨) 반응하며, 이로 인하여 표면에서 FSG 캡핑층(13)은 HF로 형성되면서 제거된다. HF 상태로 제거되므로 소수성 특성의 저유전 층간 절연막(12)의 표면에는 기존과 같은 결함(defect)이 발생되지 않는다. 한편, 수소 분위기 열처리 동안 구리배선(15)이 열처리되면서 안정된 구조로 된다.In the above, the hydrogen atmosphere heat treatment temperature is 200 ~ 400 ℃ in a rapid thermal process (RTP) method using a hydrogen compound containing less than about 0.1 to 20% of inert gas such as N 2 or Ar rather than pure hydrogen (pure H) In 3-30 seconds. The hydrogen atmosphere heat treatment may be performed by a furnace method. During the hydrogen atmosphere heat treatment, the H ions react with the incomplete F group of the FSG capping layer 13 (incomplete F groups are generated by the chemical mechanical polishing process), thereby removing the
상술한 바와 같이, 본 발명은 캡핑층이 없는 저유전 층간 절연막에 구리배선을 형성할 수 있어, 기존보다 유효 유전상수 값이 감소되어 배선간 캐패시턴스의 저하로 소자의 성능을 향상시킬 수 있으며, 화학적 기계적 연마 공정 후에 수소 분위기에서 열처리함에 따라 별도의 열처리 없이 구리배선이 안정화되는 이점이 있다. As described above, the present invention can form a copper wiring in the low dielectric interlayer insulating film without a capping layer, the effective dielectric constant value is reduced compared to the existing, it is possible to improve the performance of the device by lowering the capacitance between wiring, chemical As a heat treatment in a hydrogen atmosphere after the mechanical polishing process there is an advantage that the copper wiring is stabilized without a separate heat treatment.
Claims (5)
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| JP2000058642A (en) | 1998-08-07 | 2000-02-25 | Toshiba Corp | Manufacture of semiconductor device |
| JP2001358105A (en) | 2000-06-12 | 2001-12-26 | Mitsubishi Electric Corp | Forming method of embedded wiring, cmp device, and semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2000058642A (en) | 1998-08-07 | 2000-02-25 | Toshiba Corp | Manufacture of semiconductor device |
| JP2001358105A (en) | 2000-06-12 | 2001-12-26 | Mitsubishi Electric Corp | Forming method of embedded wiring, cmp device, and semiconductor device and manufacturing method thereof |
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