KR101081824B1 - Method of manufacturing printed circuit board formed micro-fined wiring pattern with high etching factor - Google Patents

Abstract

PURPOSE: A method for manufacturing a printed circuit board including a minute wiring pattern with a high etching factor is provided to remove the residual stress of a copper layer by applying tension. CONSTITUTION: A first copper layer is formed on the upper side of an insulation substrate(S210). The first copper layer is processed(S220). The processed first copper layer is dried(S230). A via hole is formed in an insulation substrate by using a drill process(S240). A second copper layer is formed on the surface of the first copper layer and the via hole by using an electroless copper plating process(S250). The residual stress of the second copper layer is removed by applying tension to the second copper layer(S260). The second copper layer is homogenized. A minute wiring pattern is formed by etching the first copper layer and the second copper layer(S270).

Description

METHODS OF MANUFACTURING PRINTED CIRCUIT BOARD FORMED MICRO-FINED WIRING PATTERN WITH HIGH ETCHING FACTOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a printed circuit board, and more particularly, in manufacturing a printed circuit board having a copper foil layer-based wiring pattern, the homogenization of copper foil layers and offsetting residual stress. By forming a fine wiring pattern having a high etching factor through the through, it relates to a printed circuit board manufacturing method that can realize high density and improved production yield of the printed circuit board to be manufactured.

As the performance of high-density components such as semiconductors and thin-film devices or recording medium-related components such as magnetic recording heads has improved dramatically, printed circuit boards included in electronic products are required to have a corresponding performance.

In response to such demands, researches on high density, high speed, and miniaturization have been actively conducted in the field of printed circuit board manufacture. In particular, many studies have been conducted to form wiring patterns on the printed circuit board as fine as possible.

As a method of forming a wiring pattern on a printed circuit board, a semi-additive method is typically used. The semiadditive process is a patterning method in which a chemical copper plating layer, which is a seed layer, is selectively etched with respect to an electric copper plating layer, which is a wiring part.

However, such a semi-additive process has a problem in that the pattern is not formed normally due to a significant drop in the etching factor when forming the fine wiring pattern in the process of manufacturing a printed circuit board.

Here, the etching factor is a measure of the perpendicularity of the wiring pattern shape on the basis of the longitudinal section, and the larger the etching factor, the closer the pattern is formed to the wiring shape closer to the right angle.

1A and 1B are planar photographs showing fine wiring patterns formed on a general printed circuit board.

Referring to FIG. 1A, it can be seen that the planar shape of the fine patterns does not become a rectangular shape, but is patterned in a shape close to a circle. In addition, FIG. 1B is an enlarged view of FIG. 1 at a high magnification, and the sidewalls of the fine patterns are not formed vertically, but are formed to be inclined, and the etching factor is significantly decreased.

As such, when the sidewall is inclined, there is a high risk of interference with the neighboring pattern, thereby preventing the implementation of high density microcircuits.

An object of the present invention is to form a fine wiring pattern having a high etching factor by simultaneously performing homogenization of the copper foil layer and offsetting of residual stress. Through this, an object of the present invention is to provide a manufacturing method of a printed circuit board which contributes to high density and can contribute to production yield and quality improvement.

A printed circuit board manufacturing method according to an embodiment of the present invention for achieving the above object comprises the steps of (a) forming a first copper foil layer on the insulating substrate using an electrolytic copper plating process; (b) canceling residual stress of the first copper foil layer by heat-treating the first copper foil layer while applying tensile force to the first copper foil layer; (c) removing moisture contained in the first copper foil layer through a drying process; (d) forming a via hole in the insulating substrate using a drill process; (e) forming a second copper foil layer on the surface of the first copper foil layer and inside of the via hole by using an electroless copper plating process; (f) heat-treating the second copper foil layer while applying a tensile force to the second copper foil layer to offset the residual stress of the second copper foil layer; And (g) etching the second copper foil layer and the first copper foil layer to form a fine wiring pattern.

In the method of manufacturing a printed circuit board according to the present invention, the particles constituting the copper foil layer may be homogenized through heat treatment, and the residual stress of the copper foil layer, which is inhibited from forming a fine wiring pattern, may be canceled by applying a tensile force. Through this, the second copper foil layer and the first copper foil layer for forming a fine wiring pattern may have a high etching factor (high etching factor) during the etching process.

Therefore, the method of manufacturing a printed circuit board according to the present invention can manufacture a printed circuit board on which a high-density fine wiring pattern is formed without additional cost, and can contribute to improving performance characteristics of the manufactured printed circuit board.

1A and 1B are planar photographs illustrating fine wiring patterns according to the related art.
2 is a flow chart showing an embodiment of a method for manufacturing a printed circuit board according to the present invention.
3 is a graph showing the change of the residual stress of the copper foil layer according to the heat treatment.
4 shows the etching factor of the wiring pattern when the copper foil layer was heat-treated at 100 ° C.
5A to 5G are photographs illustrating longitudinal cross-sections of wiring patterns formed after etching when heat treated at 100 ° C.
6 is a graph showing the change of the residual stress of the copper foil layer according to the tensile force.
7a and 7b are photographs showing the fine wiring patterns formed by the printed circuit manufacturing method according to the present invention.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments make the disclosure of the present invention complete, and those skilled in the art to which the present invention pertains. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, a printed circuit board manufacturing method according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a flow chart showing an embodiment of a method for manufacturing a printed circuit board according to the present invention.

2, the first copper foil layer forming step (S210), the first copper foil layer processing step (S220), the first copper foil layer drying step (S230), the via hole forming step (S240), the second copper foil layer forming step (S250), a second copper foil layer processing step (S260), and a fine wiring pattern forming step (S270).

First copper foil layer formation

In the first copper foil layer forming step (S210), a first copper foil layer is formed on the insulating substrate. The first copper foil layer formed on the insulating substrate may be formed using an electrolytic copper plating process.

In this case, the copper plating solution used in the electrolytic copper plating process may use an acidic copper plating solution having a copper (Cu) concentration of 1.0 to 1.8 mol / L, a sulfuric acid concentration of 0.4 to 0.6 mol / L, and a chlorine concentration of 5 to 50 ppm. If the copper (Cu) concentration is less than 1.0 mol / L, it is difficult to form the first copper foil layer having a microstructure. On the contrary, when the concentration of Cu exceeds 1.8 mol / L, a problem may occur in which the particle size in the first copper foil layer formed is increased.

In addition, the copper plating liquid may be one that has been activated carbon treatment for more than 1/2 of the total volume of the copper plating liquid. When using an activated carbon treated copper plating solution, the first copper foil layer may be formed at a uniform and high speed.

The first copper foil layer formed by the electrolytic copper plating process may be formed to a thickness of about 3 ~ 18㎛.

Copper foil layer treatment

In the first copper foil layer processing step (S220), the first copper foil layer is heat-treated while applying a tensile force to the first copper foil layer formed on the insulating substrate to cancel the residual stress of the first copper foil layer.

In the copper foil layer, the compressive residual stress of about -60 MPa is generated by external energy generated during the mass production process. This compressive residual stress acts as a barrier in the formation of the fine wiring pattern.

Therefore, the compressive residual stress is preferably removed before the formation of the fine wiring pattern, which can be removed by applying a tensile force opposite to the heat treatment and the compressive residual stress, and most preferably, the heat treatment and the tensile force are simultaneously performed.

Heat treatment of the first copper foil layer can be carried out at a temperature of 100 ℃ to 250 ℃, it can be carried out 1 to 10 times. At the same time, the tensile force applied to the first copper foil layer may be 100 MPa to 180 MPa. After the first copper foil layer treatment, only the residual stress of -10 MPa to 10 MPa may be present in the first copper foil layer.

The above items will be described in detail based on experimental data below.

3 is a graph showing the change of the residual stress of the copper foil layer according to the heat treatment.

Referring to Figure 3, it can be seen that the residual stress tends to be offset by the heat treatment conditions of 100 ℃, 150 ℃, 200 ℃ and 250 ℃. However, except when the heat treatment temperature is 250 ℃ can be seen that the effect of the residual stress offset is not large when the heat treatment time exceeds 2 hours.

Therefore, it is preferable to perform heat treatment for 10 minutes to 2 hours in the temperature range of 100 ~ 250 ℃ as a method of canceling the residual stress of the copper foil layer according to the present invention. In particular, when the heat treatment for 1 hour at 250 ℃ as shown in the graph of Figure 3, the residual stress can be removed to a level of -10MPa.

In the above case, only heat treatment is taken into consideration, and there is an insufficiency in removing residual stress. When the tensile force is applied simultaneously with the heat treatment to the copper foil layer, the residual stress of the copper foil layer can be effectively removed within a faster time.

4 illustrates the etching factor of the wiring pattern shown in FIGS. 5A to 6G when the copper foil layer is heat-treated at 100 ° C.

5A to 5G are photographs illustrating longitudinal cross-sections of wiring patterns formed after etching when heat treated at 100 ° C. 5A shows a case in which the heat treatment is not performed, FIG. 5B shows a heat treatment for 1 hour, FIG. 5C shows a heat treatment for 2 hours, FIG. 5D shows a heat treatment for 3 hours, and FIG. 5E shows a heat treatment for 4 hours. 5F shows a case where the heat treatment is performed for 5 hours, and FIG. 5G shows a case where the heat treatment is performed for 6 hours.

The values shown in FIG. 4 reflect the average values of the etching factors of the wiring patterns shown in FIGS. 5A to 5G.

At this time, the etching factor is determined by the following equation.

Here, W1 is the upper width of the fine wiring pattern, W2 is the lower width of the fine wiring pattern, and H is the height of the fine wiring pattern.

A shown in Figs. 5A to 5G represents (W2-W1) / 2 in the above formula. Therefore, as the value of a decreases, the etching factor increases.

Meanwhile, referring to FIG. 4, when the copper foil layer was not heat-treated, the etching factor was only about 0.9, but when the copper foil layer was heat-treated at 100 ° C., the etching factor gradually increased, and the maximum was about 1.6 at the time of heat treatment for 2 hours. You can see that it rises. When the heat treatment is performed for 2 hours or more, the etching factor decreases again due to the residual stress increase. However, when the tensile force acts at the same time, the effect of canceling the residual stress becomes larger, so that the reduction of the etching factor can be prevented to some extent. .

In the above, an example in which residual stress is mainly removed by heat treatment is shown, but the residual stress may be greatly reduced by applying the following tensile force.

Figure 6 shows the residual stress change of the copper foil layer according to the tensile force.

To this end, it shows the results of measuring the residual stress while applying a tensile strength (Tensile Strength) to 0 ~ 300MPa to the copper foil layer. Compressive Residual Stress exists in the copper foil layer when the residual stress has a negative value, and Tensile Residual Stress exists in the copper foil layer when the residual stress has a positive value. It can be seen as.

Referring to FIG. 6, it was confirmed that as the tensile force is applied to the copper foil layer having the first -60 MPa compressive residual stress, the compressive residual stress can be increased to a tensile residual stress of 50 MPa.

On the other hand, in the case of an etching factor, it can be seen that gradually increasing up to 3 when a tensile force of about 150 MPa is applied, and when a larger tensile force is applied, the etching factor decreases again as the tensile residual stress increases.

6, it can be seen that the etching factor is higher as the residual stress approaches '0' regardless of the compressive residual stress and the tensile residual stress. In FIG. 6, when the residual stress is -10 MPa to 10 MPa, the etching factor is the highest, and thus, the residual stress in this case is most preferable. In addition, it can be seen that the etching factor is excellent when approximately 2.0 or more, and according to FIG. 6, the maximum value of the etching factor was 3 in this experiment.

This can be achieved when the tensile force is about 100 MPa to 180 MPa. When the tensile force is less than 100 MPa and when the tensile strength is greater than 180 MPa, the compressive residual stress or the tensile residual stress becomes large, thereby making it impossible to implement a high etching factor.

However, this is not considering the heat treatment, it can be achieved with a smaller tensile force when the heat treatment is added with the application of the tensile force.

Therefore, in consideration of the residual stress offset effect due to the heat treatment shown in Figure 3 and the residual stress offset effect due to the application of the tensile force shown in Figure 6, the fine formed during the manufacturing process of the printed circuit board manufactured by the manufacturing method according to the present invention The wiring pattern may have a high etching factor of about 2.0 to 3.0, which can be easily obtained through the first copper foil layer treatment including the heat treatment and the application of the tensile force, and the second copper foil layer treatment described later.

Whether the treatment of the first copper foil layer, that is, the removal of the residual stress, is properly performed is measured by partially etching the first copper foil layer to determine whether an etching factor of a fine pattern falls within a range of 2.0 to 3.0, or by monitoring residual stress. It can be seen that, if a final suitability decision is made, proceed to the next step, and if it is not suitable, the heat treatment and the tensile force application can be performed again.

Drying the First Copper Foil Layer and Forming Via Holes

In the first copper foil layer drying step (S230), water contained in the first copper foil layer formed by the electrolytic copper plating process is removed through a drying process.

In the via hole forming step S240, via holes are formed in the insulating substrate by using a drill process, so that wiring patterns formed on both surfaces of the insulating substrate may be energized with each other in a subsequent process.

In this case, before the via hole is formed or after the via hole is formed, the first copper foil layer may be partially etched to form a separate fine wiring pattern.

2nd copper foil layer formation and 2nd copper foil layer process

In the second copper foil layer forming step (S250), a second copper foil layer is formed in the via hole for the surface and the energization of the first copper foil layer by using an electroless copper plating process. Formation of a 2nd copper foil layer can use an electroless copper plating process.

In the second copper foil layer treatment step (S260), the second copper foil layer is heat-treated to homogenize the second copper foil layer while applying a tensile force to the second copper foil layer to cancel the residual stress of the second copper foil layer. Since the process of the second copper foil layer is the same as the process S220 of the first copper foil layer described above, a detailed description thereof will be omitted.

Fine wiring pattern formation

In the fine wiring pattern forming step (S270), the second copper foil layer and the first copper foil layer are etched to form a fine wiring pattern.

At this time, in the present invention, since the residual stress of the first copper foil layer and the second copper foil layer is canceled before etching, the wiring pattern formed by etching may have a high etching factor of 2.0 or higher, and the subsequent process may be stably performed. Can be.

7A and 7B are planar photographs showing fine wiring patterns formed by a printed circuit manufacturing method according to the present invention.

Referring to FIGS. 7A and 7B, the sidewalls of each pattern are formed to be perpendicular to each other, and thus, the fine pattern shape having a rectangular shape having almost no difference in width between the bottom surface and the top surface of the wiring pattern is clearly seen. In this case it can have a very high etching factor.

Since the high etching factor has less interference between adjacent patterns, it is easier to implement high-density wiring patterns and improve the yield and performance of printed circuit boards.

As described above, the method of manufacturing a printed circuit board according to the present invention can remove residual stress through a treatment in which heat treatment and tensile force are applied simultaneously after forming the first copper foil layer and the second copper foil layer, and as a result, a high etching factor Can be implemented.

Therefore, according to the method of manufacturing a printed circuit board according to the present invention, it is possible to form a printed circuit board including a high-density microcircuit without additional process equipment investment or additional cost due to process change, thereby improving performance characteristics of the final product and selecting a wide range of materials. It can provide the ramifications of design diversification.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments and can be manufactured in various forms, and having ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

S210: forming the first copper foil layer S220: treating the first copper foil layer
S230: drying the first copper foil layer S240: via hole formation
S250: forming the second copper foil layer S260: treating the second copper foil layer
S270: fine wiring pattern formation

Claims (8)

(a) forming a first copper foil layer on the insulating substrate using an electrolytic copper plating process;
(b) canceling residual stress of the first copper foil layer by heat-treating the first copper foil layer while applying tensile force to the first copper foil layer;
(c) removing moisture contained in the first copper foil layer through a drying process;
(d) forming a via hole in the insulating substrate using a drill process;
(e) forming a second copper foil layer on the surface of the first copper foil layer and inside of the via hole by using an electroless copper plating process;
(f) heat-treating the second copper foil layer while applying a tensile force to the second copper foil layer to offset the residual stress of the second copper foil layer; And
(g) etching the second copper foil layer and the first copper foil layer to form a wiring pattern.
The method of claim 1,
In the step (b), a tensile force is applied to the first copper foil layer so that the residual stress of the first copper foil layer is -10 MPa to 10 MPa,
In the step (f), a tensile force is applied to the second copper foil layer so that the residual stress of the second copper foil layer is -10 MPa to 10 MPa.
The method of claim 2,
In the steps (b) and (f), the heat treatment is carried out at a temperature of 100 ℃ to 250 ℃ characterized in that the printed circuit board manufacturing method.
The method of claim 3,
The steps (b) and (f) are performed 1 to 10 times.
The method of claim 2,
In the step (b), a tensile force of 100 MPa ~ 180 MPa is applied to the first copper foil layer,
In the step (f), a tensile force of 100 MPa to 180 MPa is applied to the second copper foil layer.
The method of claim 1,
The step (a)
A copper (Cu) concentration of 1.0 to 1.8 mol / L, sulfuric acid concentration of 0.4 to 0.6 mol / L and chlorine concentration of 5 to 50 ppm using an acidic copper plating solution, characterized in that the printed circuit board manufacturing method.
The method of claim 6,
The acidic copper plating solution is a method of manufacturing a printed circuit board, characterized in that the activated carbon treatment for more than 1/2 of the total volume.
The method of claim 1,
The wiring pattern formed by the step (g) is a method of manufacturing a printed circuit board, characterized in that the etching factor (Etching Factor) is determined by the following formula (2.0 ~ 3.0).

Where W1 is the upper width of the wiring pattern, W2 is the lower width of the wiring pattern, and H is the height of the wiring pattern.

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