KR101076431B1 - Liquid crystal display device and method of driving the same - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a driving method thereof, comprising: a liquid crystal panel; A driver for supplying data and scan signals necessary for displaying an image of the liquid crystal panel; A timing controller for controlling the driver; A first control circuit having at least one register and controlling the video signal by referring to the data of the register; And a second control circuit which generates data in the register and senses a change in power of the first control circuit.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF DRIVING THE SAME}             

1 is a block diagram showing a conventional liquid crystal display device.

2 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a view showing a data transfer method between a register of a microcontroller unit and a scaler when power is supplied to the printed circuit board shown in FIG.

4 is a diagram illustrating that power supplied to a data printed circuit board shown in FIG. 2 is momentarily cut off;

FIG. 5 is a diagram illustrating a data transfer method between a register of a microcontroller unit and a scaler when power supplied to a data printed circuit board shown in FIG. 2 is cut off.

<Explanation of symbols for the main parts of the drawings>

2, 52: upper substrate 4, 54: lower substrate

6, 56: liquid crystal panel 8, 58: data PCB

10, 60: data TCP 12, 62: data drive                 

14, 64: timing control unit 16, 66: system

18, 68: gate PCB 20, 70: gate TCP

22, 72: gate drive 24, 74: data line

26, 76: gate line 28, 78: scaler

30, 80: MCU 32, 82: cable

84: Register 86: Databus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof for detecting an on-off state of a power supply to restore an image when the power supply is turned off.

A conventional liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in an active matrix, and a driving circuit for driving the liquid crystal panel.

The liquid crystal display device displays an image responsive to the video signals R, G, and B and the system 16 for generating the synchronization signals H and V and the driving clock CLK, as shown in FIG. Data Carrier Packages (TCPs) 10 on which a liquid crystal panel 6 and a data drive integrated circuit (D-IC) 12 for driving the data lines 24 of the liquid crystal panel 6 are mounted. And gate TCPs 20 mounted with gate D-ICs 22 for driving the gate lines 26 of the liquid crystal panel 6, data D-ICs 12 and gate D-ICs. The timing control part 14 for controlling the drive of 22 is provided.

The liquid crystal panel 6 includes a liquid crystal layer (not shown) formed between the upper substrate 2 and the lower substrate 4, and a spacer for maintaining a constant gap between the upper substrate 2 and the lower substrate 4. (Not shown). The common substrate, the color filter, the black matrix, and the like are formed on the upper substrate 2 of the liquid crystal panel 6. In addition, the lower substrate 4 of the liquid crystal panel 6 includes a thin film transistor (TFT) formed at each intersection of the gate lines 26 and the data lines 24. The connected liquid crystal cell is provided. The gate electrode of the TFT is connected to any one of the gate lines 26 in the horizontal line unit, and the source electrode is connected to any one of the data lines 24 in the vertical line unit. This TFT supplies the pixel signal from the data line 24 to the liquid crystal cell in response to the scan signal from the gate line 26. The liquid crystal cell includes a pixel electrode connected to the drain electrode of the TFT, and a common electrode facing the pixel electrode and the liquid crystal layer therebetween. In the liquid crystal cell, an array state of liquid crystal having dielectric anisotropy varies according to a horizontal electric field formed by a voltage difference between a pixel signal supplied to a pixel electrode and a charged pixel signal, thereby realizing gradation. .

The timing controller 14 receives the synchronization signals H and V and the driving clock CLK from the MCU 30 to control gate driving signals GSP, GSC, and GOE for controlling the driving of the gate D-ICs 22. Signal) and data control signals (SSP, SSC, SOE, POL signal, etc.) for controlling the driving of the data D-ICs 12 are generated. In addition, the timing controller 14 aligns the video signals R, G, and B supplied from the system 16 to the plurality of data D-ICs 12 in alignment with the driving of the liquid crystal panel 6. .

The timing controller 14 is mounted on a data printed circuit board 8 (hereinafter referred to as "PCB"). The data PCB 8 is connected to the system 16 via a cable 32. On the data PCB 8, various signal wires for supplying various control signals and video signals from the timing controller 14 to each of the data D-ICs 12 and the gate D-ICs 22 are formed. .

Each of the gate D-ICs 22 is mounted on each of the gate TCP 20. The gate D-IC 22 mounted on the gate TCP 20 is electrically connected to the gate pads of the liquid crystal panel 6 through the gate TCP 20. The gate D-ICs 22 sequentially drive the gate lines 26 of the liquid crystal panel 6 in units of one horizontal period (1H). At this time, the gate TCP 20 is connected to the gate PCB 18. The gate PCB 18 supplies the gate control signals supplied from the timing controller 1 to the gate D-ICs 22 through the gate TCP 20 via the data PCB 8.

Each of the data D-ICs 12 is mounted on each of the data TCP 10. The data D-IC 12 mounted on the data TCP 10 is electrically connected to the data pads of the liquid crystal panel 6 via the data TCP 10. The data D-ICs 12 convert digital pixel data into analog pixel signals and supply them to the data lines 24 of the liquid crystal panel 6 in units of one vertical period (1V).                         

The system 16 converts an image signal input from the outside into a video signal R, G, B suitable for the liquid crystal panel 6, and also includes a synchronization signal H, V and a driving clock CLK included in the image signal. ) Will be detected. The system 16 controls the scaler 28 and the scaler 28 for converting an image signal input from the outside into video signals R, G, and B suitable for the liquid crystal panel 6. Micro Controller Unit (hereinafter referred to as "MCU") 30 is provided.

The scaler 28 converts an image signal input from the outside into video signals R, G, and B corresponding to the resolution and image quality of the liquid crystal panel 6 according to the control signal CS supplied from the MCU 30. Play a role. In other words, the scaler 28 converts an image signal input from the outside into video signals R, G, and B suitable for the size of the liquid crystal panel 6 according to the control signal CS supplied from the MCU 30. In addition, the resolution of the video signals R, G, and B is converted to match the size of the liquid crystal panel 6. In addition, the scaler 28 converts an image signal input from the outside into a video signal R, G, B corresponding to the image quality of the liquid crystal panel 6 according to the control signal CS supplied from the MCU 30. do. The converted video signals R, G, and B are supplied to the timing controller 14 through the cable 32.

The MCU 30 generates a control signal CS for controlling driving of the scaler 28 by using an image signal input from the outside when power is applied to the system 16 mounted thereon, and the image signal. The synchronization signals H and V and the driving clock CLK are detected from the timing controller 14 and supplied to the timing controller 14. In this case, the control signal CS generated from the MCU 30 is supplied to the scaler 28, and the scaler 28 converts an image signal input from the outside according to the control signal CS supplied from the MCU 30. To the timing controller 14 via the cable 32.

In the liquid crystal display having such a configuration, power for driving the data PCB 8 and the gate PCB 18 is supplied from the outside through the system 16 or from the outside independently of the system 16 power. In other words, power for driving the data PCB 8 and the gate PCB 18 is directly supplied from the outside to the data PCB 8 in a large liquid crystal display such as an LCD monitor or an LCD TV. In a small liquid crystal display such as the above, it is supplied to the data PCB 8 and the gate PCB 18 through the system 16. Therefore, when power is supplied from the outside, the liquid crystal panel 6 displays an image corresponding to the video signals R, G, and B.

Such a liquid crystal display device has a power supply applied to the data PCB 8 when the liquid crystal display device is moved by a user while the power is applied to the liquid crystal display device or when the vehicle is started in a vehicle equipped with the liquid crystal display device. The state of shaking is momentarily blocked.

However, since the state of the power supplied to the system 16 and the data PCB 8 cannot be confirmed in such a conventional liquid crystal display device, the power supply after the power supply to the system 16 and the data PCB 8 is momentarily cut off. If this is recovered, there is a problem that the image displayed when the power is cut off cannot be restored.

The present invention provides a liquid crystal display device and a driving method thereof capable of detecting an on-off state of a power supply and restoring an image displayed when the power is off.

The liquid crystal display device of the present invention comprises a liquid crystal panel; A driver for supplying data and scan signals necessary for displaying an image of the liquid crystal panel; A timing controller for controlling the driver; A first control circuit having at least one register and controlling the video signal by referring to the data of the register; And a second control circuit which generates data in the register and senses a change in power of the first control circuit.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a first printed circuit board on which the timing controller and the first control circuit are mounted, a second printed circuit board on which the second control circuit is mounted, and the second printed circuit. And a cable for supplying power and the image signal to the first printed circuit board via the board.

The second control circuit includes a data bus for transmitting serial data to be written to the register and receiving data written to the register.

The second control circuit compares the data written in the register with the data sensed in the data bus to determine whether the first control circuit is powered.

The second control circuit recognizes the first control circuit in an on state when the data written in the register and the data sensed in the data bus are the same, and the data written in the register and data sensed in the data bus. If different, the first control circuit is recognized as the off state.

The driving method of the liquid crystal display device includes a liquid crystal panel, a driving unit for supplying data and scan signals necessary for displaying an image of the liquid crystal panel, and a timing controller for controlling the driving unit. Generating data; Storing the register data in a register in a control circuit; Comparing the data stored in the register with the data sensed in the data bus of the register and detecting a change in power of the control circuit according to the comparison result.

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Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 to 5.                     

Referring to FIG. 2, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel 56 displaying an image corresponding to video signals R, G, and B, and data lines of the liquid crystal panel 56. The data TCPs 60 mounted with the data D-IC 62 for driving 74 and the gate D-IC 72 for driving the gate lines 76 of the liquid crystal panel 56 are mounted. The resolution and image quality of the liquid crystal panel 56 and the timing controller 64 for controlling the driving of the gate TCPs 70, the data D-ICs 62, and the gate D-ICs 72. The system includes a scaler 78 for converting the video signals R, G, and B into conformity thereto, and an MCU 80 for controlling the scaler 78.

The liquid crystal panel 56 includes a liquid crystal layer (not shown) formed between the upper substrate 52 and the lower substrate 54, and a spacer for maintaining a constant gap between the upper substrate 52 and the lower substrate 54. (Not shown). The upper substrate 52 of the liquid crystal panel 56 includes a common electrode, a color filter, a black matrix, and the like. In addition, the lower substrate 54 of the liquid crystal panel 56 includes a thin film transistor (TFT) formed at each intersection of the gate lines 76 and the data lines 74, and a TFT. The connected liquid crystal cell is provided. The gate electrode of the TFT is connected to any one of the gate lines 76 in the horizontal line unit, and the source electrode is connected to any one of the data lines 74 in the vertical line unit. This TFT supplies the pixel signal from the data line 74 to the liquid crystal cell in response to the scan signal from the gate line 76. The liquid crystal cell includes a pixel electrode connected to the drain electrode of the TFT, and a common electrode facing the pixel electrode and the liquid crystal layer therebetween. In the liquid crystal cell, the arrangement state of the liquid crystal having dielectric anisotropy varies according to the horizontal electric field formed by the voltage difference between the pixel signal supplied to the pixel electrode and the charged pixel signal, thereby adjusting the light transmittance. do.

The timing controller 64 receives the synchronization signals H and V and the driving clock CLK from the MCU 80 to control the gate control signals GSP, GSC, and GOE for controlling the driving of the gate D-ICs 72. Signal) and data control signals (SSP, SSC, SOE, POL signal, etc.) for controlling the driving of the data D-ICs 62. In addition, the timing controller 64 aligns the video signals R, G, and B supplied from the scaler 78 to the plurality of data D-ICs 62 in alignment with the driving of the liquid crystal panel 56. .

The timing controller 64 is mounted on the data PCB 58. The data PCB 58 is connected to the system 66 via a cable 82. On the data PCB 58, various signal wires for supplying various control signals and video signals from the timing controller 64 to the data D-ICs 62 and the gate D-ICs 72 are formed. .

Each of the gate D-ICs 72 is mounted on each of the gate TCP 70. The gate D-IC 72 mounted on the gate TCP 70 is electrically connected to the gate pads of the liquid crystal panel 56 through the gate TCP 70. The gate D-ICs 72 sequentially drive the gate lines 76 of the liquid crystal panel 56 in units of one horizontal period (1H). At this time, the gate TCP 70 is connected to the gate PCB 68. The gate PCB 68 supplies gate control signals supplied from the timing controller 64 to the gate D-ICs 72 through the gate TCP 70 via the data PCB 58.

Each of the data D-ICs 62 is mounted on each of the data TCP 60. The data D-IC 62 mounted on the data TCP 60 is electrically connected to the data pads of the liquid crystal panel 56 through the data TCP 60. The data D-ICs 62 convert digital pixel data into an analog pixel signal and supply the same to the data lines 74 of the liquid crystal panel 56 in units of one vertical period (1V).

The scaler 78 has a plurality of registers 84, and the image signal input from the outside according to the control signal CS supplied from the MCU 80 through the cable 82 and the resolution of the liquid crystal panel 56 The video signal is converted into video signals R, G, and B corresponding to the image quality, and supplied to the timing controller 64. In other words, the scaler 78 converts an image signal input from the outside into video signals R, G, and B suitable for the size of the liquid crystal panel 56 according to the control signal CS supplied from the MCU 80. In addition, the resolution of the video signals R, G, and B is converted to match the size of the liquid crystal panel 56 and supplied to the timing controller 64. In addition, the scaler 78 converts an image signal input from the outside into video signals R, G, and B corresponding to the image quality of the liquid crystal panel 56 according to the control signal CS supplied from the MCU 80. Supply to timing control unit 64. Such a scaler 78 is used TW8801.

The MCU 80 is installed inside the system 66 to generate a control signal CS for controlling the driving of the scaler 78 by using an image signal input from the outside, and the synchronization signals H and V from the image signal. ) And the driving clock CLK are supplied to the timing controller 64. In this case, the control signal CS generated from the MCU 80 is supplied to the scaler 78 through the cable 82. In addition, the MCU 80 detects a power supply state of the data PCB 58 according to the state of the control signal CS supplied to the scaler 78, and according to the power state of the detected data PCB 58, the liquid crystal panel ( The image displayed on 56 is controlled.

The control method of an image displayed on the liquid crystal panel 56 according to the power state of the data PCB 58 in the liquid crystal display device will be described with reference to FIGS. 3 to 5 as follows. In this case, it is assumed that normal power is applied to the system 66 in which the MCU 80 is embedded.

First, as shown in FIG. 3, the MCU 80 includes a plurality of registers mounted inside the scaler 78 through a data bus 86 such as I ² C to detect a power state of the data PCB 58. The serial data SDATA (WR) value is written to one of the registers 84, and the serial data SDATA (RD) value stored in the register 84 is read. At this time, the serial data (SDATA) value to be written to the register 84 is the default value (Default value) set when the data PCB 58 is reset (Reset) or a plurality of registers mounted in the scaler 78 The unused 0xff value and the serial data SDATA to be written should not be values that cause errors in the liquid crystal display. Here, the serial data SDATA (WR) value written in the register 84 and the serial data SDATA (RD) value stored in the register 84 are controlled by the MCU 80 to control the scaler 78. CS).

When the power supply Vp is normally applied to the data PCB 58, that is, during the t1 period when a voltage higher than the driving voltage is supplied to the data PCB 58, the MCU 80 is mounted in the scaler 78. After writing the serial data SDATA (WR) value in any one of the registers 84, at least one register 84 whose value does not change again is selected. At this time, the MCU 80 reads the serial data SDATA (RD) value stored in the selected register 84. The MCU 80 performs a serial data SDATA (WR) value set in the selected register 84 periodically and repeatedly through the data bus 86 during a period in which the power Vp is normally applied to the data PCB 58. The serial data SDATA (RD) of the selected register 84 is read. At this time, the MCU 80 reads the serial data SDATA (RD) value identical to the serial data SDATA (WR) value written to the register 84. As a result, the MCU 80 recognizes that the data PCB 58 is in an ON state, that is, normally operating. Accordingly, the image according to the video signal input from the outside is displayed on the liquid crystal panel 56.

When the power supply Vp applied to the data PCB 58 is momentarily interrupted, that is, during the t2 period when a voltage lower than the driving voltage is supplied to the data PCB 58, the MCU 80 registers via the data bus 86. The serial data (SDATA (WR)) value written to (84) and the different serial data (SDATA (RD)) values are read. In other words, when the power supply Vp applied to the data PCB 58 is momentarily interrupted, the data bus 86 between the resistor 84 and the MCU 80 mounted inside the scaler 78 is shorted. As a result, a high impedance state is established between the register 84 and the MCU 80. Accordingly, the MCU 80 recognizes the value supplied from the register 84, that is, the serial data SDATA (RD) value read by the MCU 80 as 0xff, as shown in FIG. 58 is recognized as OFF, that is, not normally operated, and a control signal CS is generated to maintain register values at the time when the data PCB 58 is OFF. At this time, the registers 84 of the scaler 78 maintain the video signals R, G, and B at the moment when the power supply Vp is momentarily cut off. When the power supplied to the data PCB 58 is cut off momentarily, the image is not displayed on the liquid crystal panel 56.

The MCU 80 writes to the register 84 in a period in which the power supply Vp is reset to the data PCB 58, that is, in a period t3 where the power supply Vp is temporarily interrupted and supplied above the driving voltage. The serial data SDATA (RD) value identical to the serial data SDATA (WR) value is read. As a result, the MCU 80 recognizes that the normal power Vp is supplied to the data PCB 58 and the video signal R at the time t2 at which the power Vp supplied to the data PCB 58 is momentarily cut off. The driving of the scaler 78 is controlled to supply, G, B to the liquid crystal panel 56. Accordingly, the liquid crystal panel 56 restores the state of the screen before the power supply Vp of the data PCB 58 is cut off.

In the above, when the power of the system 66 in which the MCU 80 is mounted is normally supplied, that is, only the case in which the power state of the system is ON is described in Table 1, but the system 66 and the data PCB 58 are described. When the power supplied to the display panel is changed, as shown in Table 1, the state of the liquid crystal panel 56 is changed.

System power state Power state of data PCB LCD Panel Operation Status
ON ON Normal operation ON → OFF OFF OFF → ON Reset → ON OFF OFF ON → OFF ON Keep current output OFF → ON ON Reset → ON
OFF ON → OFF OFF OFF → ON OFF OFF OFF

Table 1 shows the operation state of the liquid crystal panel according to the power state of the system in which the MCU is mounted and the power state of the data PCB on which the scaler is mounted.

In Table 1, the ON state of the power state of the system 66 and the power state of the data PCB 58 means that normal power is applied to the system 66 and the data PCB 58, and the ON → OFF state is shown in FIG. This means that the normal operation section t1 is changed from an abnormal operation section t2 among the power states of the illustrated data PCB 58. On the contrary, the OFF → ON state means that the power supply state of the data PCB 58 shown in FIG. 4 changes from an abnormal operation section t2 to a normal operation section t3.

In the liquid crystal display having such a configuration, a power source for driving the system 66 and a power source for driving the data PCB 58 and the gate PCB 68 are supplied from the outside. The power for driving the data PCB 58 and the gate PCB 68 among the power supplies is directly supplied to the data PCB 58 from the outside in a large liquid crystal display such as an LCD monitor or an LCD TV. In a small liquid crystal display such as a PDA, the data is supplied to the data PCB 58 and the gate PCB 68 through the system 66 and the cable 82. Therefore, when power is supplied from the outside, the liquid crystal panel 56 displays an image corresponding to the video signals R, G, and B.                     

As described above, the LCD and the driving method thereof according to an exemplary embodiment of the present invention provide a register 84 in which the MCU 80 is mounted inside the scaler 78 without the addition of a peripheral circuit for detecting a power state of the data PCB 58. By comparing the serial data (SDATA (WR)) value written to the value with the serial data (SDATA (RD)) value read from the register 84, the state of the power applied to the data PCB 58 can be known. Accordingly, the MCU 80 can always monitor the power state of the data PCB 58.

In addition, the liquid crystal display according to an exemplary embodiment of the present invention and a driving method thereof include video signals R, G, which are displayed on the liquid crystal panel 56 when the power Vp supplied to the data PCB 58 is momentarily cut off. If the normal power supply Vp is supplied to the data PCB 58 by holding B), the video signals R, G, and B at the time when the power supply Vp is cut off are supplied to the data PCB 58. The state of the screen can be restored.

As described above, according to the liquid crystal display and the driving method thereof according to the present invention, the power state of the data printed circuit board using the program logic of the microcontroller unit without the addition of a peripheral circuit for detecting the power state of the data printed circuit board. You can check. In addition, when the power supplied to the data printed circuit board is momentarily cut off, the video signal displayed on the liquid crystal panel is maintained so that the power is supplied by supplying a video signal when the power is cut off when the power is normally supplied to the data printed circuit board. You can restore the state of the screen at the time when it was blocked.                     

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (7)

A liquid crystal panel; A driver for supplying data and scan signals necessary for displaying an image of the liquid crystal panel; A timing controller for controlling the driver; A first control circuit having at least one register and controlling the video signal by referring to the data of the register; And a second control circuit which generates data of the register and senses a change in power of the first control circuit. The method of claim 1, A first printed circuit board on which the timing controller and the first control circuit are mounted; A second printed circuit board on which the second control circuit is mounted; And a cable for supplying power and the image signal to the first printed circuit board via the second printed circuit board. The method of claim 1, And the second control circuit includes a data bus for transmitting serial data to be written to the register and receiving data written to the register. The method of claim 3, wherein And the second control circuit compares data written in the register with data sensed in the data bus to determine whether the first control circuit is powered. The method of claim 4, wherein The second control circuit recognizes the first control circuit in an on state when the data written in the register and the data sensed in the data bus are the same, and the data written in the register and data sensed in the data bus. And the first control circuit is recognized as an off state if different. A method of driving a liquid crystal display device having a liquid crystal panel, a driver for supplying data and scan signals necessary for displaying an image of the liquid crystal panel, and a timing controller for controlling the driver. Generating register data; Storing the register data in a register in a control circuit; And comparing the data stored in the register with the data sensed in the data bus of the register and detecting a change in power of the control circuit according to the comparison result. The method of claim 6, Detecting a change in power of the control circuit, if the data written in the register and the data sensed in the data bus are the same, the control circuit is recognized as on, and the data written in the register and the data bus And driving the control circuit to an off state when the sensed data is different.

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