KR101074409B1 - Flat panel device and method for fabricating the same - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a flat panel display device suitable for improving productivity by reducing the number of masks and a method of manufacturing the same. The flat panel display device for achieving the above object includes a flat panel display in which a cell region and a pad region are defined on a substrate. An element, comprising: an active layer formed in one region of the cell region; A gate line formed with a gate electrode on the substrate including the active layer, and a storage electrode formed across the active layer in parallel with the gate line; A source region and a drain region formed in the active layer on both sides of the gate electrode except for the lower portion of the storage electrode; An interlayer insulating layer formed on the substrate and having first and second contact holes in the source and drain regions; A data line crossing the gate line to define a pixel area; A pixel electrode formed in the pixel region; A source electrode contacted to the source region through the first contact hole, a drain electrode electrode contacted to the drain region through the second contact hole and having a side surface directly contacting the side surface of the pixel electrode; A protective film formed on an entire surface of the substrate including the pixel electrode, and formed between the first storage capacitor region and the storage electrode / interlayer insulating film / drain electrode formed between the storage electrode / interlayer insulating film / pixel electrode. And a storage capacitor having a second storage capacitor region.

LCD, AM-OLED, Mask, Storage

Description

Flat panel display device and manufacturing method thereof {FLAT PANEL DEVICE AND METHOD FOR FABRICATING THE SAME}

1 is a circuit diagram of a flat panel display device having a general AMOLED

2 is a schematic cross-sectional view of a general organic light emitting device

3 is a plan view of a flat panel display device according to the related art

4 is a cross-sectional view taken along line II ′ of FIG. 3.

5A to 5H are cross-sectional views of a flat panel display device according to the related art.

6 is a plan view of a flat panel display device according to another conventional technology

7 is a cross-sectional view taken along line II-II ′ of FIG. 6.

8A to 8H are cross-sectional views of a flat panel display device according to another conventional technology.

9 is a plan view of a flat panel display device according to a first exemplary embodiment of the present invention.

FIG. 10 is a cross-sectional view taken along line III-III ′ of FIG. 9;

11A to 11F are cross-sectional views of a flat panel display device according to a first exemplary embodiment of the present invention.

12 is a plan view of a flat panel display device according to a second exemplary embodiment of the present invention.

FIG. 13 is a cross-sectional view taken along line IV-IV ′ of FIG. 12.

14A to 14F are cross-sectional views of a flat panel display device according to a second exemplary embodiment of the present invention.

15 and 16 illustrate another structure of the pad region.

Explanation of symbols on the main parts of the drawings

100: insulating substrate 101: buffer insulating film

102: active layer 102a, 102b: source, drain region

103: gate insulating film 104: gate line

104a: gate electrode 104b: storage electrode

104c: first conductive layer 105: interlayer insulating film

106a and 106b: first and second contact holes

106c and 106d: First and second pad contact holes 107a: Pixel electrode

107b and 107c Pad electrodes 108a and 108b Source and drain electrodes

108c: second conductive layer 109: protective film

110: bank area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device, and more particularly, to a flat panel display device capable of improving productivity by reducing the number of masks and a manufacturing method thereof.

In general, the liquid crystal display device is in the spotlight as a portable display device because it is relatively light / thin / short / small compared to other display devices, a typical Note Book PC (Note Book) PC.

Such a liquid crystal display is largely divided into upper and lower substrates and a liquid crystal layer injected between the upper and lower substrates.

The lower substrate may include a plurality of gate lines arranged in one direction at regular intervals on a glass substrate, and data lines arranged at regular intervals in a direction perpendicular to the gate lines to define a pixel area in a matrix form. And a plurality of pixel electrodes formed in each pixel area, and formed in each pixel area of a portion where the gate line and the data line cross each other, thereby converting the data signal of the data line according to the signal of the gate line. A plurality of thin film transistors to be applied to the electrode are arranged.

The upper glass substrate includes a black matrix layer for preventing light from being irradiated to portions other than the pixel region of the lower substrate, a color filter layer for expressing color in each pixel region between the black matrix layers, and the color. A common electrode or the like formed on the entire surface of the substrate including the filter layer is arranged. The liquid crystal layer is injected between the upper and lower substrates thus formed.

As described above, in the liquid crystal display, when each pixel is arranged in a matrix form and a signal is applied to one gate line, a data signal is applied to a pixel corresponding to the line.

However, the liquid crystal injected between the upper and lower substrates causes deterioration of characteristics when a DC voltage is applied for a long time. In order to prevent this, the liquid crystal is periodically changed to be driven, and this is called a polarity inversion driving method.

Such polarity inversion driving methods include frame inversion, line inversion, column inversion, and dot inversion driving methods.

First, the frame inversion is a method of applying the polarity of the data voltage applied to the liquid crystal with respect to the common electrode voltage in the unit of frame.

That is, if a data voltage of positive polarity is applied to an even frame, a data voltage of negative polarity is applied to an odd frame. However, such a frame inversion driving method has an advantage of low current consumption during switching, but is sensitive to flicker caused by asymmetry of transmittance between positive and negative polarity, and crosstalk due to inter-data interference ( It is very vulnerable to crosstalk.

In addition, the line inversion driving method is a polarity inversion driving method which is generally used for low resolution (VGA, SVGA), and applies a data voltage so that the polarity of the pixel is changed in units of horizontal lines. That is, if a positive polarity is applied to an odd line and a negative polarity data voltage is applied to an even line, a negative data voltage is applied to an odd line and an even number is applied to an odd line. A positive data voltage is applied to the line. In such a line inversion driving method, since data voltages of opposite polarities are applied between adjacent lines, the flicker phenomenon of the lines is reduced by spatial averaging, and the voltage of opposite polarities is decreased in the vertical direction. Coupling between data is canceled out so that vertical crosstalk is small compared to frame inversion. However, in the horizontal direction, voltages of the same polarity are distributed to generate horizontal crosstalk, and the number of switching repetitions is increased compared to frame inversion, thereby increasing current consumption.

The column inversion driving method is a driving method in which polarities of data voltages to be applied are the same in the vertical direction and opposite polarities in the horizontal direction. As in the line inversion driving method, the flicker phenomenon is smaller than the frame inversion and the horizontal crosstalk is smaller than the frame inversion by the spatial averaging method. However, a high voltage column drive IC must be used because a data voltage of opposite polarity between adjacent lines must be applied in a vertical direction with respect to the common electrode voltage.

Finally, the dot inversion driving method is a polarity inversion driving method that realizes the best image quality at present, and is applied to high resolutions (XGA, SXGA, UXGA), and the polarities of data voltages between adjacent pixels are reversed in all directions. Therefore, the flicker phenomenon can be minimized by the spatial averaging method, but it has the disadvantage of using a high voltage column drive IC and having a large current consumption.

In addition to the liquid crystal display (LCD) as well as the flat panel display device, there is also an Active Matrix Organic Light Emitting Device (AM-OLED), which will be described below. .

1 is a circuit configuration diagram of a flat panel display device having a typical AM-OLED, and FIG. 2 is a diagram schematically illustrating a cross-sectional structure of a general organic light emitting device.

As shown in FIG. 1, a typical AM-OLED includes a data driving circuit 20, a scan line driving circuit 22, a plurality of scan lines S1, S2,..., Sm, and data lines D1 and D2. The organic EL display panel 24 includes a switching PMOS transistor P1, a capacitor C2, a current driving PMOS transistor P2, and an organic EL (OEL) between each of the ..., Dn. .

The gate of the PMOS transistor P1 is connected to the scan line and the source is connected to the data line. One side of the capacitor C2 is connected to the drain of the PMOS transistor P1, and the other side thereof is connected to the voltage Vdd. The gate of the PMOS transistor P2 is connected to the drain of the PMOS transistor P1. The anode of the organic EL (OEL) is connected to the drain of the PMOS transistor P2, and the cathode is connected to the ground voltage.

In the AM-OLED having the above configuration, the organic EL is formed with an anode electrode 2 formed on the glass substrate 1 in a transparent electrode pattern, as shown in FIG. The light emitting layer 4 and the electron injection layer 5 are stacked, and a cathode electrode 6 composed of a metal electrode is formed on the electron injection layer 5.

When a driving voltage is applied to the anode electrode 2 and the cathode electrode 6, the holes in the hole injection layer 3 and the electrons in the electron injection layer 5 proceed toward the light emitting layer 4 to excite the light emitting layer 4. This causes the light emitting layer 4 to emit visible light. Thus, an image or an image is displayed by the visible light generated from the light emitting layer 4.

Hereinafter, a flat panel display device, that is, a liquid crystal display (LCD) and an AM-OLED, which is driven by a line inversion driving method, will be described.

Referring to the accompanying drawings, a conventional flat panel display device and a manufacturing method thereof will be described.

First, the configuration of the flat panel display device according to the prior art will be described.

3 is a plan view of a flat panel display device according to the prior art, and FIG. 4 is a structural cross-sectional view taken along line II ′ of FIG. 3.

The flat panel display device according to the prior art is for a liquid crystal display device (LCD) for line inversion driving.

As shown in FIGS. 3 and 4, a buffer layer 31 is formed on an insulating substrate 30, an active layer 32 patterned on the buffer layer 31, and an insulation including an active layer 32. A gate insulating film 34 is formed on the substrate 30, the gate line 35 is arranged in one direction in one region of the gate insulating film 34, and the gate electrode 35a is disposed on one side of the gate line 35. Is protruded, the storage electrode 35b is arranged in a direction parallel to the gate line 35 so as to cross the active layer 32, and the P-type is formed in the active layer 32 on both sides of the gate electrode 35a. The insulating substrate 32 includes a source region 32a and a drain region 32b into which impurity ions are implanted, and first and second contact holes 37a and 37b in the source region 32a and the drain region 32b, respectively. 30, an interlayer insulating film 36 is formed on the top, and the source contacted to the source region 32a through the first contact hole 37a. A data line 38 is arranged to extend the switch electrode 38a and the source electrode 38a so as to define a pixel area orthogonal to the gate line 35, and drain through the second contact hole 37b. There is a drain electrode 38b patterned in a predetermined shape so as to contact the region 32b, and the passivation layer 39 is formed on the entire surface of the insulating substrate 30 so as to have a third contact hole 40a in one region of the drain electrode 38b. Is formed and a pixel electrode 41 is formed in one region of the pixel region so as to contact the drain electrode 38b through the third contact hole 40a, and includes an insulating substrate including the pixel electrode 41a. A photosensitive organic film 42 is formed on the entire surface of 30.

The interlayer insulating film 36 is formed of a silicon nitride film (SiNx) and has a thickness of approximately 7000 Å.

The p-type impurity is doped in the active layer 32 below the storage electrode 35b to reduce the resistance of the active layer 32.

As a result, the storage capacitor is formed between the region / gate insulating film 34 / storage electrode 35b doped in the active layer (" A " region).

In addition, as shown in FIG. 4, the pad region for applying signals to the gate line 35 and the data line 38 in the liquid crystal panel is formed on the insulating substrate 30 and the buffer insulating film 31 and the gate insulating film ( 34 and the interlayer insulating layer 36 are stacked, and a first conductive layer 37c is patterned in one region of the interlayer insulating layer 36, and a pad contact hole is formed in one region of the first conductive layer 37c. A protective film 39 having a 40b formed thereon, a pad electrode 41a is formed on the pad contact hole 40b and a protective film 39 adjacent thereto, and the photosensitive organic layer is formed so that the pad electrode 41a is opened. The film 42 is formed.

The pad region described above is configured to be connected to the inside of the liquid crystal panel through the pad electrode 41a and the first conductive layer 37c.

The first conductive layer 37c is formed of the same material on the same layer as the source / drain electrodes 38a and 38b, and the pad electrode 41a is formed of the same material on the same layer as the pixel electrode 41.

The pad region may be used as either a gate pad or a data pad for applying a signal to a gate line or a data line of the liquid crystal panel.

Next, a method of manufacturing a flat panel display device according to the prior art having the above configuration will be described.

5A to 5H are cross-sectional views of a flat panel display device according to the related art.

First, as shown in 5a, a buffer layer 31 is formed on an insulating substrate 30 such as glass in which an active region is defined.

The polysilicon layer is deposited on the buffer layer 31 by chemical vapor deposition, and then the polysilicon layer is pattern-etched using a first mask for forming an active region to form the active layer 32.

In this case, the active layer 32 may be formed by crystallization by irradiating a laser beam or the like after depositing amorphous silicon.

At this time, no active layer is formed in the pad region.

As shown in FIG. 5B, after the photoresist film 33 is applied onto the buffer layer 31 including the active layer 32, one region of the active layer 32 is exposed through an exposure and development process using a second mask. The photosensitive film 33 is selectively patterned so as to be effective.                         

Thereafter, impurity ions are implanted into the patterned active layer 32 and doped. In this case, the region doped with impurities is an active layer portion corresponding to a lower portion of the region where the storage electrode is to be formed later, and the second mask is a doping mask for forming the storage capacitor.

After the ion implantation process, the photoresist layer 33 is removed.

Next, as shown in FIG. 5C, a gate insulating film 34 is deposited on the insulating substrate 30 including the active layer 32, and a gate forming material such as aluminum or molybdenum is sputtered on the gate insulating film 34. To form.

Subsequently, the gate forming material is etched by using a third mask for forming a gate, the gate line 35a having one direction, the gate electrode 35a protruding from one side of the gate line 35, and the gate line. The storage electrode 35b is formed in a direction parallel to the 35.

As a result, the storage capacitor is formed between the doped active layer 32 / the gate insulating layer 34 / the storage electrode 35b.

The gate electrode 35a is formed to protrude from one side and cross a predetermined portion of the active layer 32.

At this time, only the gate insulating film 34 is deposited in the pad region.

Next, the P-type impurity ions are implanted using the gate electrode 35a and the storage electrode 35b as ion blocking masks, so that the source region 32a and the drain region 32b are formed in the active layer 32 on both sides of the gate electrode 35a. ).

Thereafter, as shown in FIG. 5D, an interlayer insulating film 36 is deposited on the gate insulating film 34 including the gate line 35. At this time, the interlayer insulating film 36 forms a silicon nitride film with a thickness of approximately 7000 Å.

Next, first and second contact holes 37a and 37b are formed in the source / drain regions 32a and 32b using the fourth mask, respectively.

At this time, only the interlayer insulating film 36 is formed in the pad region.

Subsequently, as illustrated in FIG. 5E, after depositing a metal layer on the entire surface including the first and second contact holes 37a and 37b, the first and second contact holes 37a and 37b are formed using a fifth mask. And a source electrode 38a and a drain electrode 38b are formed on the interlayer insulating layer 36 adjacent thereto, and are integrally formed with the source electrode 38a and intersect the gate line 35 to define a pixel region. The data line 38 (see Fig. 3) is formed.

In this case, the first conductive layer 37c is formed in one region of the pad region.

Subsequently, as shown in FIG. 5F, after the protective film 39 is deposited on the entire surface including the source / drain electrodes 38a and 38b, the protective film 39 is exposed to expose the drain electrode 38b using a sixth mask. Is etched to form a third contact hole 40a.

In this case, a pad contact hole 40b is formed in one region of the first conductive layer 37c in the pad region.

Next, as illustrated in FIG. 5G, a transparent conductive material is deposited on the entire surface of the insulating substrate 30 including the third contact hole 40a, and then the pixel electrode 41 is formed in the pixel region using the seventh mask. do.

In this case, the pad electrode 41a is formed on the pad contact hole 40b and the passivation layer 39 adjacent thereto.

Next, as shown in FIG. 5H, a photosensitive organic film 42 is coated on the insulating substrate 30 including the pixel electrode 41 and the pad electrode 41a.

Subsequently, the photosensitive organic layer 42 is etched using the eighth mask so that the pad electrode 41a of the pad region is exposed to form the pad open region 43.

Next, a flat panel display element according to another conventional technology and a manufacturing method thereof will be described.

6 is a plan view of a flat panel display device according to another conventional technology, and FIG. 7 is a structural cross-sectional view taken along line II-II 'of FIG. 6, and FIGS. 8A to 8H illustrate a process of a flat panel display device according to another conventional technology. It is a cross section.

The flat panel display device according to another conventional technology is for an active matrix organic light emitting device (AM-OLED), as shown in FIGS. 6 and 7, the flat panel display according to the prior art Since the bank region 44 for forming the organic light emitting diode is formed on the flat portion of the pixel electrode 41 in the device, the description thereof will be omitted.

In addition, the manufacturing method of the flat panel display device according to another conventional technology having the above configuration is the same as the manufacturing method of the conventional flat panel display device up to FIGS. When forming, since the bank region 44 is formed so that the flat portion of the pixel electrode 41 of the cell region is exposed, the description thereof will be omitted below.                         

The bank area is an area for forming an organic light emitting device.

In this case, a photo-etched organic film 42 such as polyimide or photoacryl is used as the material to be etched to form the bank region. If the dry-etched organic film is used instead of the photosensitive organic film, the pixel electrode may be used. There is a problem of being damaged and uneven, and there is a fear that the light emission life of the AM-OLED is reduced.

Although not shown in the drawing, when the bank region 44 is formed in the cell region, the photosensitive organic layer 42 of the pad region may be formed so that only one region of the pad electrode 41a is opened, You can also remove it.

The above-described conventional flat panel display element and its manufacturing method have the following problems.

When manufacturing line inversion LCDs and AMOLEDs, a process of separately doping an active layer using a storage doping mask is required to form a storage capacitor between the doped active layer / gate insulating layer / storage electrode. This increases the number of masks.

That is, since a mask for forming a storage capacitor is required separately, there is a limit in increasing productivity by reducing the number of masks.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a flat panel display device suitable for improving productivity by reducing the number of masks and a manufacturing method thereof.

According to an aspect of the present invention, there is provided a flat panel display device comprising: an active layer formed in one region of the cell region; A gate line formed with a gate electrode on the substrate including the active layer, and a storage electrode formed across the active layer in parallel with the gate line; A source region and a drain region formed in the active layer on both sides of the gate electrode except for the lower portion of the storage electrode; An interlayer insulating layer formed on the substrate and having first and second contact holes in the source and drain regions; A data line crossing the gate line to define a pixel area; A pixel electrode formed in the pixel region; A source electrode contacted to the source region through the first contact hole, a drain electrode contacted to the drain region through the second contact hole and having a side surface directly contacting the side surface of the pixel electrode; A protective film formed on the entire surface of the substrate including the pixel electrode, and a first storage capacitor region formed between the storage electrode / the interlayer insulating film / the pixel electrode and a second electrode formed between the storage electrode / the interlayer insulating film / drain electrode. And a storage capacitor having a storage capacitor region.

According to another aspect of the present invention, there is provided a flat panel display device comprising: an active layer formed in one region of the cell region, the flat panel display device having a cell region and a pad region defined on a substrate; A gate line formed with a gate electrode on the substrate including the active layer, and a storage electrode formed across the active layer in parallel with the gate line; A source region and a drain region formed in the active layer on both sides of the gate electrode except for the lower portion of the storage electrode; An interlayer insulating layer formed on the substrate and having first and second contact holes in the source and drain regions; A data line crossing the gate line to define a pixel area; A pixel electrode formed in the pixel region; A source electrode contacted to the source region through the first contact hole, a drain electrode contacted to the drain region through the second contact hole and having a side surface directly contacting the side surface of the pixel electrode; A passivation layer in which a bank region is formed to expose a flat portion of the pixel electrode; An organic light emitting element formed in the bank region above the pixel electrode, and a first storage capacitor region formed between the storage electrode / interlayer insulating film / pixel electrode and the storage electrode / interlayer insulating film / drain electrode And a storage capacitor having a second storage capacitor region.

The interlayer insulating film is formed of a silicon nitride film (SiNx) having a thickness of approximately 2000 ~ 3000Å.

In the flat panel display device, a storage capacitor is formed between the storage electrode, the interlayer insulating film, the pixel electrode, and the storage electrode, the interlayer insulating film, and the drain electrode.

The protective layer is formed of an acrylic (acryl) -based organic compound, BCB (Benzo Cyclo Butene) or PFCB.

In the pad region of the flat panel display device, the interlayer formed with the gate insulating film formed on the substrate, the first conductive layer formed on one region of the gate insulating film, and the first pad contact hole formed in the first conductive layer. And an insulating film, a pad electrode formed on the interlayer insulating film including the first pad contact hole, and the passivation film having a pad open area formed around the edge of the pad electrode.

According to an aspect of the present invention, there is provided a method of manufacturing a flat panel display device having a cell area and a pad area defined on a substrate. Forming an active layer in the region; Forming a gate line including a gate electrode on the substrate including the active layer and a storage electrode to cross the active layer in a direction parallel to the gate line by using a second mask, and forming a first conductive layer in the pad region. A second step of forming a layer; Forming a source region and a drain region in the active layer on both sides of the gate electrode except for the lower portion of the storage electrode; A fourth step of forming an interlayer insulating film using a third mask so as to have first and second contact holes in the source and drain regions and a first pad contact hole on the first conductive layer of the pad region; Forming a pixel electrode in the pixel region using a fourth mask and forming a pad electrode in the pad region; A data line crossing the gate line using a fifth mask to define a pixel region, a source electrode contacted to the source region through the first contact hole, and a drain region through the second contact hole; A sixth step of forming a drain electrode to be in contact with a side surface of the pixel electrode; Forming a pad open region in the pad region using a sixth mask, and forming a passivation layer on the entire surface of the cell region including the pixel electrode; and between the storage electrode, the interlayer insulating layer, and the pixel electrode. And a storage capacitor having a first storage capacitor region formed at the second storage capacitor region and a second storage capacitor region formed between the storage electrode, the interlayer insulating layer, and the drain electrode.

The protective film is formed of an inorganic insulating material such as silicon nitride (SiNx), or an acrylic (acryl) organic compound, BCB (Benzo Cyclo Butene) or PFCB.

According to another aspect of the present invention, there is provided a method of manufacturing a flat panel display device in which a cell region and a pad region are defined on a substrate, wherein an active layer is formed in one region of the cell region using a first mask. A first step of making; Forming a gate line including a gate electrode on the substrate including the active layer and a storage electrode to cross the active layer in a direction parallel to the gate line by using a second mask, and forming a first conductive layer in the pad region. A second step of forming a layer; Forming a source region and a drain region in the active layer on both sides of the gate electrode except for the lower portion of the storage electrode; A fourth step of forming an interlayer insulating film using a third mask so as to have first and second contact holes in the source and drain regions and a first pad contact hole on the first conductive layer of the pad region; Forming a pixel electrode in the pixel region using a fourth mask and forming a pad electrode in the pad region; A data line crossing the gate line using a fifth mask to define a pixel region, a source electrode contacted to the source region through the first contact hole, and a drain region through the second contact hole; A sixth step of forming a drain electrode to be in contact with a side surface of the pixel electrode; A seventh step of forming a pad open region in the pad region using a sixth mask and forming a protective film on the entire surface of the substrate to have a bank region in a flat portion of the pixel electrode; And an eighth step of forming an organic light emitting diode in the bank region above the pixel electrode, wherein the first storage capacitor region and the storage electrode / interlayer insulating layer are formed between the storage electrode / interlayer insulating film / pixel electrode. And a storage capacitor having a second storage capacitor region formed between the drain electrodes.

The protective film is formed of an acrylic (acryl) organic compound, BCB (Benzo Cyclo Butene) or PFCB.

Hereinafter, a flat panel display device and a manufacturing method thereof according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings.                     

First embodiment

First, the configuration of the flat panel display device according to the first embodiment of the present invention will be described.

9 is a plan view of a flat panel display device according to a first exemplary embodiment of the present invention, and FIG. 10 is a structural cross-sectional view taken along line III-III ′ of FIG. 9. 15 and 16 are diagrams illustrating another structure of the pad region.

A first embodiment of the present invention relates to a P-type Low Temperature Poly Silicon (LTPS) liquid crystal display (LCD) suitable for application to line inversion driving.

9 and 10, a buffer layer 101 is formed on an insulating substrate 100, an active layer 102 patterned on the buffer layer 101, and an insulation including an active layer 102. The gate insulating film 103 is formed on the substrate 100, the gate line 104 is arranged in one direction in one region of the gate insulating film 103, and the gate electrode 104a is disposed on one side of the gate line 104. Is protruded, the storage electrode 104b is arranged in a direction parallel to the gate line 104 so as to cross the active layer 102, and the P-type is formed in the active layer 102 on both sides of the gate electrode 104a. The insulating substrate 102 includes a source region 102a and a drain region 102b into which impurity ions are implanted, and a first and second contact holes 106a and 106b in the source region 102a and the drain region 102b, respectively. An interlayer insulating film 105 is formed on the upper portion of the substrate 100 except for the first and second contact holes 106a and 106b. A pixel electrode 107a is formed in one region of the reverse side, and extends from the source electrode 108a and the source electrode 108a contacted to the source region 102a through the first contact hole 106a. The data line 108 is arranged to define the pixel region orthogonal to the gate line 104, and contacts the drain region 102b through the second contact hole 106b, and one side thereof directly contacts the pixel electrode 107a. There is a drain electrode 108b patterned to be in contact with a predetermined shape, and a passivation layer 109 is formed on an entire surface of the insulating substrate 100 including the source / drain electrodes 108a and 108b and the pixel electrode 107a.

The interlayer insulating film 105 is formed of a silicon nitride film (SiNx), and has a thickness of about 2000 to 3000 mW.

Thus, the storage capacitor of the present invention is formed between the storage electrode 104b / interlayer insulating film 105 / pixel electrode 107a or the storage electrode 104b / interlayer insulating film 105 / drain electrode 108b. B ″ region) As described above, since the storage capacitor is formed, the active layer 102 under the storage electrode 104b is not doped.

The pixel electrode 107a may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). It consists of.

The protective layer 109 is formed to protect the device, and may be formed of an inorganic insulating material such as silicon nitride (SiNx) or an organic insulating material such as acryl-based organic compound, Benzo Cyclo Butene (BCB), or PFCB. do.

Although not shown in the drawing, one region of the pixel electrode 107a may be opened flat.

In addition, the pad region for applying signals to the gate line 104 and the data line 108 in the liquid crystal panel has shown two forms that can be implemented in FIG. 10, and other forms that can be implemented in FIGS. Indicated.

First, as shown in FIG. 10, a buffer insulating film 101 and a gate insulating film 103 are stacked on an insulating substrate 100, and a first conductive layer 104c is formed in one region of the gate insulating film 103. The interlayer insulating film 105 is patterned and the first and second pad contact holes 106c and 106d are formed in one region of the first conductive layer 104c, and the first pad contact hole 106c is formed. And a pad electrode 107b formed on the interlayer insulating film 105 adjacent thereto, and the second conductive layer 108c extending in one direction on the interlayer insulating film 105 including the second pad contact hole 106c. There is a protective film 109 in which the pad electrode 107b is opened in the first pad contact hole 106c so that the pad electrode 107b is exposed.

The pad region described above is configured to be connected to the inside of the liquid crystal panel through the pad electrode 107b, the first conductive layer 104c, and the second conductive layer 108c. That is, the signal is applied to the inside of the liquid crystal panel through the second conductive layer 108c.

In addition to the above configuration, the pad region does not constitute the second conductive layer 108c, but directly forms the first conductive layer 104d connected to the pad electrode 107c into the liquid crystal panel to be connected to the gate line and the data line. You can also

The first conductive layers 104c and 104d are formed of the same material on the same layer as the gate electrode 104a, and the pad electrodes 107b and 107c are formed of the same material on the same layer as the pixel electrode 107a. The second conductive layer 108c is formed of the same material on the same layer as the source / drain electrodes 108a and 108b.                     

In this case, the pad open area is formed such that both inclined sides of the pad electrodes 107b and 107c are exposed. The pad open area is formed in the pad electrode 155 and 166 as shown in FIGS. 15 and 16. The protective layers 157 and 167 may surround both sides of the picture.

The structure in which the first conductive layer is directly applied to the liquid crystal panel is stronger than the structure in which a signal is applied to the inside of the liquid crystal panel through the second conductive layer.

Each pad area may be used as either a gate pad or a data pad for applying a signal to a gate line or a data line of the liquid crystal panel.

Next, a manufacturing method of the flat panel display device according to the first embodiment of the present invention having the above configuration will be described.

11A to 11F are cross-sectional views of a flat panel display device according to a first exemplary embodiment of the present invention.

First, as shown in 11a, a buffer layer 101 is formed on an insulating substrate 100 such as glass in which an active region is defined.

The polysilicon layer is deposited on the buffer layer 101 by chemical vapor deposition, and then the polysilicon layer is pattern-etched using the first mask for forming the active region to form the active layer 102.

In this case, the active layer 102 may be formed by crystallizing by irradiating a laser beam or the like after depositing amorphous silicon.                     

The buffer layer 101 serves to prevent impurities from the insulating substrate 100 from diffusing into the active region and ultimately blocks heat during laser crystallization.

At this time, no active layer is formed in the pad region.

As shown in FIG. 11B, a gate insulating film 103 is deposited on the buffer layer 101 including the active layer 102, and a gate forming material such as aluminum or molybdenum is sputtered on the gate insulating film 103. do.

Subsequently, the gate forming material is etched by using a second mask for forming a gate, and the gate electrode 104a protruding from one side of the gate line 104 and the gate line 104 having one direction, and the gate line The storage electrode 104b is formed in a direction parallel to the 104.

In this case, the gate electrode 104a protrudes from one side portion and is formed to cross a predetermined portion of the active layer 102.

In this case, the first conductive layers 104c and 104d are formed in the pad region.

Next, P-type impurity ions are implanted using the gate electrode 104a and the storage electrode 104b as ion blocking masks, so that the source region 102a and the drain region 102b are formed in the active layer 102 on both sides of the gate electrode 104a. ).

Thereafter, as shown in FIG. 11C, an interlayer insulating film 105 is deposited on the gate insulating film 103 including the gate line 104.

Next, first and second contact holes 106a and 106b are formed in the source / drain regions 102a and 102b using the third mask, respectively.

In this case, first and second pad contact holes 106c and 106d are formed in the pad area.

Subsequently, as illustrated in FIG. 11D, after the transparent conductive material is deposited on the entire surface of the insulating substrate 100, the pixel electrode 107a is formed in the pixel region using the fourth mask.

The transparent conductive material may include indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). use.

In this case, pad electrodes 107b and 107c are formed in the pad region on the first pad contact hole 106c and the interlayer insulating layer 105 adjacent thereto.

Next, as shown in FIG. 11E, after depositing a metal layer on the entire surface including the first and second contact holes 106a and 106b, the first and second contact holes 106a and 106b are formed using a fifth mask. And a source electrode 108a and a drain electrode 108b are formed on the interlayer insulating layer 105 adjacent thereto, and are integrally formed with the source electrode 108a and intersect the gate line 104 to define a pixel region. The data line 108 (see Fig. 9) is formed.

In this case, the drain electrode 108b is in direct contact with the pixel electrode 107a at one lower side.

As described above, the storage capacitor is disposed between the storage electrode 104b / interlayer insulating film 105 / pixel electrode 107a or the storage electrode 104b / interlayer insulating film 105 / drain electrode 108b. Is formed.

In this case, a second conductive layer 108c is formed on the second pad contact hole 106d and the interlayer insulating layer 105 adjacent thereto.                     

Next, as shown in FIG. 11F, a protective film 109 is deposited on the entire surface of the substrate 100 including the source / drain electrodes 108a and 108b.

Thereafter, the pad region is etched using the sixth mask to etch the passivation layer 109 so that the inclined sides of the pad electrode 107b are exposed.

In the pad opening process, the protective layer 109 may not be etched in the cell region so that the pixel electrode 107a is exposed.

The passivation layer 109 may be formed of an inorganic insulating material such as silicon nitride (SiNx) or an organic insulating material such as an acryl-based organic compound, Benzo Cyclo Butene (BCB), or PFCB.

In the above-described process, the pad region is formed so that both inclined side surfaces of the pad electrodes 107b and 107c are exposed. As shown in FIGS. 157 and 167 may be formed to be wrapped.

In addition, the structure in which the first conductive layer is directly applied to the inside of the liquid crystal panel is stronger than the structure in which the signal is applied to the inside of the liquid crystal panel through the second conductive layer in the pad region.

Second embodiment

First, the configuration of the flat panel display device according to the second embodiment of the present invention will be described.

12 is a plan view of a flat panel display device according to a second exemplary embodiment of the present invention, and FIG. 13 is a cross-sectional view taken along line IV-IV ′ of FIG. 12.                     

15 and 16 illustrate another structure of the pad region.

A second embodiment of the present invention relates to an active matrix organic light emitting device (AM-OLED) for applying line inversion driving.

12 and 13, a buffer layer 101 is formed on an insulating substrate 100, an active layer 102 patterned on the buffer layer 101, and an insulation including an active layer 102. The gate insulating film 103 is formed on the substrate 100, the gate line 104 is arranged in one direction in one region of the gate insulating film 103, and the gate electrode 104a is disposed on one side of the gate line 104. Is protruded, the storage electrode 104b is arranged in a direction parallel to the gate line 104 so as to cross the active layer 102, and the P-type is formed in the active layer 102 on both sides of the gate electrode 104a. The insulating substrate 102 includes a source region 102a and a drain region 102b into which impurity ions are implanted, and a first and second contact holes 106a and 106b in the source region 102a and the drain region 102b, respectively. An interlayer insulating film 105 is formed on the upper portion of the substrate 100 except for the first and second contact holes 106a and 106b. A pixel electrode 107a is formed in one region of the region, and extends from the source electrode 108a and the source electrode 108a contacted to the source region 102a through the first contact hole 106a. The data line 108 is arranged to define the pixel region orthogonal to the gate line 104, and contacts the drain region 102b through the second contact hole 106b, and one side thereof directly contacts the pixel electrode 107a. There is a drain electrode 108b patterned in a predetermined shape to be in contact, and a protective film 109 is formed on the entire surface of the insulating substrate 100 including the source / drain electrodes 108a and 108b and the pixel electrode 107a. A bank region 110 is formed so that one region of the pixel electrode 107a is flat. The bank region 110 is a region for forming an organic EL element later.

The interlayer insulating film 105 is formed of a silicon nitride film (SiNx), and has a thickness of approximately 2000 to 3000 Å.

Thus, the storage capacitor of the present invention is formed between the storage electrode 104b / interlayer insulating film 105 / pixel electrode 107a or the storage electrode 104b / interlayer insulating film 105 / drain electrode 108b. B ″ region) As described above, since the storage capacitor is formed, the active layer 102 under the storage electrode 104b is not doped.

The pixel electrode 107a may be formed of indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). It consists of.

The passivation layer 109 is formed of an organic insulating material such as an acryl-based organic compound, BCB (Benzo Cyclo Butene), or PFCB.

In the above, the bank region 110 should be formed on the flat portion of the pixel electrode 107a, since the flat anode electrode should be ensured when the organic EL element is formed later.

As shown in FIG. 2, the organic EL device has a general structure, and an anode electrode 2 is formed of a transparent electrode pattern, and a hole injection layer 3, a light emitting layer 4, and an electron injection layer are formed thereon. (5) is laminated, and a cathode electrode 6 composed of a metal electrode is formed on the electron injection layer 5 and formed.

In the organic light emitting device, when a driving voltage is applied to the anode electrode 2 and the cathode electrode 6, the holes in the hole injection layer 3 and the electrons in the electron injection layer 5 proceed toward the light emitting layer 4, respectively. The light emitting layer 4 is excited to cause the light emitting layer 4 to emit visible light. Thus, an image or an image is displayed by the visible light generated from the light emitting layer 4.

In this case, the anode electrode 2 is composed of the pixel electrodes 107a of FIGS. 12 and 13, and although not shown in the drawing, a hole injection layer, an emission layer, an electron injection layer, and a cathode are sequentially disposed on the pixel electrode 107a. If the electrode is configured, an active matrix organic light emitting device (AM-OLED) is formed.

The reason why the bank region 110 should be formed on the flat portion of the pixel electrode 107a is that when the bank region is formed on the inclined portion of the anode electrode, the hole injection layer, the light emitting layer, the electron injection layer, and the cathode electrode are subsequently stacked. This is because when the electric field is concentrated at the inclined edge portion, the area is easily deteriorated, and thus the lifespan is shortened.

In addition, the pad region for applying signals to the gate line 104 and the data line 108 in the liquid crystal panel has shown two forms that can be implemented in FIG. 13, and two other forms that can be implemented in FIGS. 15 and 16. Indicated.

First, as shown in FIG. 13, a buffer insulating film 101 and a gate insulating film 103 are stacked on an insulating substrate 100, and a first conductive layer 104c is formed in one region of the gate insulating film 103. ) Is patterned, and an interlayer insulating film 105 having first and second pad contact holes 106c and 106d formed in one region of the first conductive layer 104c. The first pad contact hole ( A pad electrode 107b is formed on the insulating layer 105 and the interlayer insulating layer 105 adjacent thereto, and the second conductive layer extending in one direction on the interlayer insulating layer 105 including the second pad contact hole 106c. 108c, and a passivation layer 109 in which the pad electrode 107b is opened in the first pad contact hole 106c so that the pad electrode 107b is exposed.

The pad region described above is configured to be connected to the inside of the liquid crystal panel through the pad electrode 107b, the first conductive layer 104c, and the second conductive layer 108c. That is, the signal is applied to the inside of the liquid crystal panel through the second conductive layer 108c.

In addition to the above configuration, the pad region does not constitute the second conductive layer 108c, but directly forms the first conductive layer 104d connected to the pad electrode 107c into the liquid crystal panel to be connected to the gate line and the data line. You can also

The first conductive layers 104c and 104d are formed of the same material on the same layer as the gate electrode 104a, and the pad electrodes 107b and 107c are formed of the same material on the same layer as the pixel electrode 107a. The second conductive layer 108c is formed of the same material on the same layer as the source / drain electrodes 108a and 108b.

In the above two types of pad regions, the pad open regions are formed so that the inclined sides of the pad electrodes 107b and 107c are exposed. The pad open regions are pad electrodes as shown in FIGS. 15 and 16. The passivation layers 157 and 167 may surround the inclined both sides of the 155 and 166.

For reference, a structure in which the first conductive layer is directly applied to the inside of the liquid crystal panel is stronger than that in the liquid crystal panel through the second conductive layer.

Each pad area may be used as a gate pad or a data pad that applies a signal to a gate line or a data line of the liquid crystal panel.

Next, a method of manufacturing a flat panel display element according to a second embodiment of the present invention having the above configuration will be described.

14A to 14F are cross-sectional views of a flat panel display device according to a second exemplary embodiment of the present invention.

First, as shown in 14a, a buffer layer 101 is formed on an insulating substrate 100 such as glass in which an active region is defined.

The polysilicon layer is deposited on the buffer layer 101 by chemical vapor deposition, and then the polysilicon layer is pattern-etched using the first mask for forming the active region to form the active layer 102.

In this case, the active layer 102 may be formed by crystallizing by irradiating a laser beam or the like after depositing amorphous silicon.

The buffer layer 101 serves to prevent impurities from the insulating substrate 100 from diffusing into the active region and ultimately blocks heat during laser crystallization.                     

At this time, no active layer is formed in the pad region.

As shown in FIG. 14B, a gate insulating film 103 is deposited on the buffer layer 101 including the active layer 102, and a gate forming material such as aluminum or molybdenum is sputtered on the gate insulating film 103. do.

Subsequently, the gate forming material is etched by using a second mask for forming a gate, and the gate electrode 104a protruding from one side of the gate line 104 and the gate line 104 having one direction, and the gate line The storage electrode 104b is formed in a direction parallel to the 104.

In this case, the gate electrode 104a protrudes from one side portion and is formed to cross a predetermined portion of the active layer 102.

In this case, the first conductive layers 104c and 104d are formed in the pad region.

Next, P-type impurity ions are implanted using the gate electrode 104a and the storage electrode 104b as ion blocking masks, so that the source region 102a and the drain region 102b are formed in the active layer 102 on both sides of the gate electrode 104a. ).

Thereafter, as shown in FIG. 14C, an interlayer insulating film 105 is deposited on the gate insulating film 103 including the gate line 104.

Next, first and second contact holes 106a and 106b are formed in the source / drain regions 102a and 102b using the third mask, respectively.

In this case, first and second pad contact holes 106c and 106d are formed in the pad area.

Subsequently, as illustrated in FIG. 14D, after the transparent conductive material is deposited on the entire surface of the insulating substrate 100, the pixel electrode 107a is formed in the pixel region using the fourth mask.

The transparent conductive material may include indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). use.

In this case, pad electrodes 107b and 107c are formed in the pad region on the first pad contact hole 106c and the interlayer insulating layer 105 adjacent thereto.

Next, as shown in FIG. 14E, a metal layer is deposited on the entire surface including the first and second contact holes 106a and 106b, and then the first and second contact holes 106a and 106b are formed using a fifth mask. And a source electrode 108a and a drain electrode 108b are formed on the interlayer insulating layer 105 adjacent thereto, and are integrally formed with the source electrode 108a and intersect the gate line 104 to define a pixel region. The data line 108 (see Fig. 12) is formed.

In this case, the drain electrode 108b is in direct contact with the pixel electrode 107a at one lower side.

As described above, the storage capacitor is disposed between the storage electrode 104b / interlayer insulating film 105 / pixel electrode 107a or the storage electrode 104b / interlayer insulating film 105 / drain electrode 108b. Is formed.

In this case, a second conductive layer 108c is formed on the second pad contact hole 106d and the interlayer insulating layer 105 adjacent thereto.

Next, as shown in FIG. 14F, a protective film 109 is deposited on the entire surface of the substrate 100 including the source / drain electrodes 108a and 108b.

Thereafter, the passivation layer 109 is etched using the sixth mask so that the flat portion of the pixel electrode 107a is exposed to form the bank region 110.

In this case, the pad region is also etched using the sixth mask to form the pad open region by etching the passivation layer 109 so that both inclined sides of the pad electrode 107b are exposed.

The passivation layer 109 is formed of an organic insulating material such as an acryl-based organic compound, benzocyclobutene (BCB), or PFCB.

Although not shown in the drawing, after forming the bank region 110 as described above, an active matrix is formed by laminating a hole injection layer, a light emitting layer, an electron injection layer, and a cathode electrode on the pixel electrode 107a in order. A type organic light emitting element (AM-OLED) is formed.

The reason why the bank region 110 should be formed on the flat portion of the pixel electrode 107a is that when the bank region is formed including the inclined portion of the anode electrode, the hole injection layer, the light emitting layer, the electron injection layer, and the cathode electrode are later formed. This is because the electric field is concentrated at the inclined edge portion after lamination, and the area is easily deteriorated, thereby shortening the lifespan.

In the above-described process, the pad region is formed so that both inclined side surfaces of the pad electrodes 107b and 107c are exposed. As shown in FIGS. 157 and 167 may be formed to be wrapped.

In addition, the structure in which the first conductive layer is directly applied to the liquid crystal panel is stronger than the structure in which the signal is applied to the inside of the liquid crystal panel through the second conductive layer in the pad region. The pad electrodes 155 and 166 The structure surrounding the inclined side is stronger than that of the previous type.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit of the invention.

Accordingly, the technical scope of the present invention should not be limited to the contents described in the above embodiments, but should be determined by the claims.

The flat panel display device and the method of manufacturing the same of the present invention as described above has the following effects.

First, the number of masks can be reduced when manufacturing LCDs and AM-OLEDs, simplifying the process.

Second, the bank area for forming the organic light emitting device of the AM-OLED is flat, so that the life of the device due to the concentration of the electric field can be solved.

Third, the pad area can be configured to effectively cope with the problem of the electrical failure.

Claims (10)

In a flat panel display device in which a cell region and a pad region are defined on a substrate, An active layer formed in one region of the cell region; A gate line formed with a gate electrode on the substrate including the active layer, and a storage electrode formed across the active layer in parallel with the gate line; A source region and a drain region formed in the active layer on both sides of the gate electrode except for the lower portion of the storage electrode; An interlayer insulating layer formed on the substrate and having first and second contact holes in the source and drain regions; A data line crossing the gate line to define a pixel area; A pixel electrode formed in the pixel region; A source electrode contacted to the source region through the first contact hole, a drain electrode contacted to the drain region through the second contact hole and having a side surface directly contacting the side surface of the pixel electrode; A protective film formed on an entire surface of the substrate including the pixel electrode; And a storage capacitor having a first storage capacitor region formed between the storage electrode / interlayer insulating film / pixel electrode and a second storage capacitor region formed between the storage electrode / interlayer insulating film / drain electrode. A flat panel display element. In a flat panel display device in which a cell region and a pad region are defined on a substrate, An active layer formed in one region of the cell region; A gate line formed with a gate electrode on the substrate including the active layer, and a storage electrode formed across the active layer in parallel with the gate line; A source region and a drain region formed in the active layer on both sides of the gate electrode except for the lower portion of the storage electrode; An interlayer insulating layer formed on the substrate and having first and second contact holes in the source and drain regions; A data line crossing the gate line to define a pixel area; A pixel electrode formed in the pixel region; A source electrode contacted to the source region through the first contact hole, a drain electrode contacted to the drain region through the second contact hole and having a side surface directly contacting the side surface of the pixel electrode; A passivation layer in which a bank region is formed to expose a flat portion of the pixel electrode; An organic light emitting element formed in the bank region above the pixel electrode; And a storage capacitor having a first storage capacitor region formed between the storage electrode / interlayer insulating film / pixel electrode and a second storage capacitor region formed between the storage electrode / interlayer insulating film / drain electrode. A flat panel display element characterized by the above-mentioned. The method according to claim 1 or 2, And the interlayer insulating film is formed of a silicon nitride film (SiNx) having a thickness of 2000 to 3000 GPa. delete The method of claim 2, The passivation layer is formed of an acryl-based organic compound, BCB (Benzo Cyclo Butene) or PFCB. The method according to claim 1 or 2, In the pad region of the flat panel display element, Further comprising a gate insulating film on the substrate on which the active layer is formed, The gate insulating film formed on the substrate, a first conductive layer formed on one region of the gate insulating film, the interlayer insulating film formed with a first pad contact hole in the first conductive layer, and the first pad contact hole. And a passivation layer having a pad open region formed around the pad electrode and the pad electrode formed on the interlayer insulating layer. In the method of manufacturing a flat panel display device in which a cell region and a pad region are defined on a substrate, A first step of forming an active layer in one region of the cell region using a first mask; Forming a gate line including a gate electrode on the substrate including the active layer and a storage electrode to cross the active layer in a direction parallel to the gate line by using a second mask, and forming a first conductive layer in the pad region. A second step of forming a layer; Forming a source region and a drain region in the active layer on both sides of the gate electrode except for the lower portion of the storage electrode; A fourth step of forming an interlayer insulating film using a third mask so as to have first and second contact holes in the source and drain regions and a first pad contact hole on the first conductive layer of the pad region; Forming a pixel electrode in the pixel region using a fourth mask and forming a pad electrode in the pad region; A data line crossing the gate line using a fifth mask to define a pixel region, a source electrode contacted to the source region through the first contact hole, and a drain region through the second contact hole; A sixth step of forming a drain electrode to be in contact with a side surface of the pixel electrode; Forming a pad open region in the pad region using a sixth mask, and forming a passivation layer over the cell region including the pixel electrode; And a storage capacitor having a first storage capacitor region formed between the storage electrode / interlayer insulating film / pixel electrode and a second storage capacitor region formed between the storage electrode / interlayer insulating film / drain electrode. A method for manufacturing a flat panel display element. The method of claim 7, wherein The protective film is formed of an inorganic insulating material such as silicon nitride film (SiNx), or an acryl-based organic compound, BCB (Benzo Cyclo Butene), or PFCB. In the method of manufacturing a flat panel display device in which a cell region and a pad region are defined on a substrate, A first step of forming an active layer in one region of the cell region using a first mask; Forming a gate line including a gate electrode on the substrate including the active layer and a storage electrode to cross the active layer in a direction parallel to the gate line by using a second mask, and forming a first conductive layer in the pad region. A second step of forming a layer; Forming a source region and a drain region in the active layer on both sides of the gate electrode except for the lower portion of the storage electrode; A fourth step of forming an interlayer insulating film using a third mask so as to have first and second contact holes in the source and drain regions and a first pad contact hole on the first conductive layer of the pad region; Forming a pixel electrode in the pixel region using a fourth mask and forming a pad electrode in the pad region; A data line crossing the gate line using a fifth mask to define a pixel region, a source electrode contacted to the source region through the first contact hole, and a drain region through the second contact hole; A sixth step of forming a drain electrode to be in contact with a side surface of the pixel electrode; A seventh step of forming a pad open region in the pad region using a sixth mask and forming a protective film on the entire surface of the substrate to have a bank region in a flat portion of the pixel electrode; An eighth step of forming an organic light emitting element in the bank region above the pixel electrode; And a storage capacitor having a first storage capacitor region formed between the storage electrode / interlayer insulating film / pixel electrode and a second storage capacitor region formed between the storage electrode / interlayer insulating film / drain electrode. A method for manufacturing a flat panel display element. The method of claim 9, The protective film is formed of an acryl-based organic compound, BCB (Benzo Cyclo Butene) or PFCB.

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