KR101068047B1 - Producing method for Multi-Layer Deposition Capacitor - Google Patents

Abstract

The present invention relates to a method of manufacturing a high capacity MLDC (Multi-Layer Deposition Capacitor). The present invention discloses an electrode pattern printing step of forming an electrode pattern on a wafer, depositing a dielectric layer for insulation by atomic layer deposition on the electrode pattern, annealing to heat the dielectric layer, deposition of the electrode pattern and the dielectric layer and Laminating the heat treatment repeatedly, cutting the sheet on which the electrode pattern and the dielectric layer are formed; And forming an external electrode on an outer surface of the cut sheet. Since the present invention configured as described above is a method of depositing a metal electrode layer and a dielectric layer only by a dry method, it is possible to minimize defects at the interface between layers by omitting the sintering process, which is absolutely necessary in the wet process, and the expensive Ag, Ag- as internal electrodes. It is possible to replace Pd metal with inexpensive copper (Cu), and it is possible to form an interlayer thin film of precise thickness only by a pure dry method.

Evaporation, alumina, sputtering, annealing, lamination

Description

Producing method for Multi-Layer Deposition Capacitor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer deposition capacitor, and more particularly, to a method for manufacturing a multilayer deposition capacitor, in which a metal electrode and a dielectric (insulation) layer on which an electrode pattern is formed are laminated through a plurality of dry deposition processes.

In general, MLCC (Multi-Layer Ceramic Capacitor) laminates a dielectric sheet produced through a doctor blade wet method and a thin film printed with an internal electrode pattern through screen printing on top thereof. Compressed and manufactured by sintering at high temperature. Here, the doctor blade is a method of applying the slurry to a flat thickness, a method of buried a liquid material in a dense low thickness using a blade called a blade.

MLCC is a capacitor made of a multilayer conductive metal film and is a component capable of temporarily storing electricity. In other words, it is an electronic component that is used for various purposes such as DC-blocking, by-passing, and coupling in electronic devices such as mobile communication devices, digital AV devices, computers, etc. by using an alternating current that does not pass.

The MLCC through the conventional manufacturing method is the same as the configuration in which several capacitors are connected in parallel by stacking a plurality of dielectric sheets, which are green sheets of ceramic material, on which electrode patterns are printed. In this case, the sintering process in which the dielectric sheet is laminated in a multilayer structure by the doctor blade method may cause many defects, and it is difficult to obtain a dielectric layer having a constant thickness.

The general MLCC manufacturing process begins with the manufacture of powder made by the general ceramic manufacturing process. In this case, the powder is prepared by mixing a starting raw material having a predetermined basic composition with distilled water and then calcining (calcination) for a predetermined time at a specific temperature.

In addition, a powder such as PVA is added to the powder to increase moldability, and is made into a slurry, and then cast into a ceramic green sheet by a doctor blade casting method. Then, suitable internal electrodes such as Ag, Pd, Pt, etc. are screen-painted on the sheet. In addition, the green sheets are stacked and cut into chips.

After that, the chip is heated to a constant temperature (about 400 to 500 ° C.) to burn out the binder, and then sintered to a constant temperature of a high temperature, and then the final external electrode is attached to both sides to prepare an MLCC. .

As MLCCs manufactured in this way, the capacity of multilayer ceramic capacitors is increasing as electronic devices become smaller and lighter. At this time, the miniaturization of the multilayer ceramic capacitor is inevitably required for more detailed thinning and multilayering of the laminated sheets to be laminated. In the process of thinning, multilayering and stacking a dielectric sheet according to the manufacture of a high capacity MLCC, the following problems occur.

First, when the MLCC is formed by stacking and compressing a dielectric sheet printed with internal electrodes, a thickness step is formed in a portion where the internal electrodes are printed on the dielectric sheet and where the internal electrodes are not printed. Such thickness step is remarkable when several sheets of dielectric sheets are laminated.

Here, the pressing of the laminated dielectric sheets is performed by a pressing device that presses a predetermined thickness. At this time, the portion where the inner electrode is printed is formed thicker than where the inner electrode is not printed due to the thickness of the inner electrode.

Therefore, even when the laminated dielectric sheet is pressed, the portion on which the internal electrode is printed is convex due to the thickness of the internal electrode. The convex shape of the MLCC is a major cause of pickup failure when the MLCC is mounted on an electronic device or the like.

In addition, in the case of tape casting by a doctor blade method, the thickness variation is severe, and there is a problem in that a crack occurs in the sintering process after lamination and a defect occurs in the internal electrode.

The present invention has been made to solve the above problems of the prior art, to provide a method for manufacturing a multilayer deposition capacitor that can evenly improve the laminated surface by removing the thickness step for the film of the internal electrode.

In addition, the present invention does not require a high temperature sintering, and provides a method for manufacturing a multilayer deposition capacitor capable of minimizing a defect of a ceramic plate generated in a process of compression firing after the operation.

In addition, the present invention provides an in-situ process and a dry process, and provides a method for manufacturing a multilayer deposition capacitor with little generation of pores appearing on the ceramic plate by epitaxial growth through vacuum.

In addition, the present invention is easy to control the deposition rate depending on the time through the atomic layer deposition method, to provide a method for manufacturing a multilayer deposition capacitor that can significantly reduce the thickness of the existing dielectric layer thickness.

According to an aspect of the present invention, there is provided a method of fabricating a multilayer deposition capacitor, including forming an electrode pattern on a wafer, depositing a dielectric layer for insulation by an atomic layer deposition method on the electrode pattern, and heat treating the dielectric layer. An annealing step, a lamination step of repeatedly performing deposition and heat treatment of the electrode pattern and the dielectric layer, and cutting a sheet on which the electrode pattern and the dielectric layer are formed; And forming an external electrode on an outer surface of the cut sheet.

Here, the electrode pattern may be deposited to a thickness of 800 ~ 1000 Å by sputtered copper (Cu).

In addition, the dielectric layer may be configured by depositing alumina.

In addition, it is preferable that TMA (Tri-Methyl-Aluminium) and Iso-prothyle-alchole (IPA) are used as a medium of the reactor for deposition of the alumina.

In addition, TMA (Tri-Methyl-Aluminium) and H ₂ O may be used as a medium of the reactor for the deposition of the alumina.

In addition, the annealing step is preferably heat-treated at 400 ~ 600 ℃ in the atmosphere of Ar or N ₂ .

On the other hand, the external electrode may be formed of any one of Ni, Sn or Sn / Pb plating layer.

In addition, the laminated deposition capacitor manufacturing method according to the present invention includes a sputter chamber for depositing an electrode pattern; An atomic layer deposition chamber capable of temperature control for the deposition of the dielectric layer; A heater chamber for the annealing; And a transfer chamber in charge of the transfer between the chambers.

As described above, the method of manufacturing the multilayer deposition capacitor according to the present invention minimizes the defects between the interlayer interfaces by omitting the sintering process, which is absolutely necessary in the wet process, thereby atomic layer deposition (ALD) instead of the wet method in ceramic lamination. By using a dry method through the method, and also using a silicon wafer in the case of the base material, it is possible to evenly improve the laminated surface by removing the thickness step on the insulating layer using alumina and the film of the internal electrode obtained by depositing copper.

In addition, the multilayer deposition capacitor manufacturing method according to the present invention can obtain an effect that can replace expensive Ag, Ag-Pd metal with low-cost copper (Cu) as an internal electrode.

In addition, in the method of manufacturing a multilayer deposition capacitor according to the present invention, it is possible to form an interlayer thin film of precise thickness only by a pure dry method, thereby easily providing capacitors having different capacities by adjusting the number of cycles.

Hereinafter, with reference to the accompanying drawings a preferred embodiment of a method for manufacturing a multilayer deposition capacitor according to the present invention. In this process, the thickness of the lines or the size of the components shown in the drawings may be exaggerated for clarity and convenience of description. In addition, the terms described below are defined in consideration of the functions of the present invention, which may vary depending on the intention or custom of the user, the operator. Therefore, definitions of these terms should be made based on the contents throughout the specification.

In addition, the following examples are not intended to limit the scope of the invention, but merely illustrative of the components set forth in the claims of the present invention, which are included in the technical spirit throughout the specification of the present invention and components of the claims Embodiments including substitutable components as equivalents in may be included in the scope of the present invention.

The MLDC described as an embodiment of the present invention has the same characteristics as that of MLCC, but the manufacturing method may be regarded as an MLCC manufacturing method using only an Atomic Layer Depositon method, a Sputter method, and a dry method through heat treatment. have.

Example

1 is a flow chart of a method for manufacturing a multilayer deposition capacitor according to an embodiment of the present invention, Figure 2 is a plan view of an atomic layer chamber, a sputter chamber and a transfer chamber performing the procedure of Figure 1, Figure 3 is an atom of Figure 1 Cycle graph for the layer deposition step.

Referring to FIG. 1, a method of manufacturing a multilayer deposition capacitor according to an embodiment of the present invention is a method of manufacturing a high capacity multi-layer deposition capacitor (MLDC) through multilayer deposition using a dry method on a wafer. Step (S1), stacking number setting step (S2) for adjusting the number of stacking of the internal electrode pattern and the dielectric layer, electrode pattern printing step (S3) to form the electrode pattern on the cleaned wafer, atomic layer deposition on the electrode pattern (S4) depositing a dielectric layer for insulation by an Atomic Layer Deposition (ALD) method, annealing step S5 of heat treating the dielectric layer, and stacking step S6 of repeatedly depositing and heat treating the electrode pattern and the dielectric layer. And depositing an external electrode on the laminated sheet (S7), cutting the sheet on which the electrode pattern and the dielectric layer are formed (S8), and testing the cut sheet (S9).

Here, atomic layer deposition (ALD) is a nano thin film deposition technique using a phenomenon of monoatomic layer that is chemically attached during the semiconductor manufacturing process, and the adsorption and substitution of molecules on the wafer surface alternately to increase the atomic layer thickness. Lower temperatures (500) than chemical vapor deposition (CVD) enable fine layer-by-layer deposition, stack thin films of oxides and metals as thin as possible, and deposit particles on the wafer surface formed by chemical reactions of gases It is a technique which can form a film quality in FIG.

According to one embodiment of the present invention configured as described above, the metal electrode layer and the dielectric layer are deposited only by the dry method, thereby minimizing the defect of the interlayer interface by omitting the sintering process, which is necessary in the wet process, and thus forming the interlayer thin film with precise thickness. Do.

Here, the electrode pattern is formed by depositing a thickness of 800 to 1000 Å by copper (Cu) by sputtering on a wafer or a dielectric layer. At this time, since the Ag, Ag-Pd metal used as a conventional internal electrode is replaced with copper (Cu), the production cost of the multilayer capacitor can be reduced, thereby increasing the price competitiveness of the multilayer capacitor as a final product.

Then, as described above, the external electrode pattern is formed through the mask after lamination, and thus external electrodes may be formed at both ends of the dielectric sheet, and heat conduction and bonding to the electrode pattern may be secured by heat treatment. On the other hand, the external electrode of the sheet can be formed of any one of Ni, Sn or Sn / Pb plating layer.

Also, referring to FIGS. 1 and 2, a method of manufacturing a multilayer capacitor according to an embodiment of the present invention includes a sputter chamber 100 for depositing an electrode pattern; An atomic layer deposition chamber 200 capable of temperature control for the deposition of the dielectric layer; A heater chamber 300 for the annealing; And a transfer chamber 400 that is responsible for transferring wafers between the sputter chamber 100, the atomic layer deposition chamber 200, and the heater chamber 300. At this time, the transfer chamber 400 is composed of a load / unload lock chamber (410/420).

Specifically, in the method of manufacturing a multilayer deposition capacitor according to an embodiment of the present invention, after forming an internal electrode (metal conductive film) obtained through a metal mast to a photolithography process (S3) on a silicon wafer, A dielectric (insulation) layer is deposited on the upper surface of the inner electrode sheet by atomic layer deposition (S4).

In this case, the photolithography process uses a principle in which a specific chemical (PR; photo resist) causes a chemical reaction to change when the light is received. That is, a process of forming the same pattern as the pattern of the mask by selectively irradiating light to the photoresist PR using the mask of the pattern to be obtained. The photolithography process is a PR coating process for applying a photoresist corresponding to a film of a general photograph, an exposure process for selectively irradiating light with a mask, and then a portion that receives light with a developer. It is composed of a developing step of forming a pattern by removing PR.

In addition, the atomic layer deposition method (S4) is to form a thin film through a chemical reaction similar to chemical vapor deposition (CVD). That is, alumina growth through the atomic layer deposition method is performed by deposition through the reactivity of the atomic layer on the surface after the reactor precursor, which is an aluminum precursor (Precursor) is supplied to the chamber. In general, chemical vapor deposition (CVD) requires high temperatures (500-700 ° C.), while atomic layer deposition does not require high temperatures (<350 ° C.).

At this time, the Ar or N2 gas is supplied to the atomic layer deposition chamber 200 to exhaust the atomic layer or more. Subsequently, a gas, which is an oxidant precursor, is supplied to the atomic deposition chamber 200, and deposition of alumina is performed through chemical reaction with the previously generated precursor. Again, deposition is repeatedly possible by supplying Ar or N ₂ gas to the atomic layer deposition chamber.

Here, TMA (Tri-Methyl-Aluminium) is used as the aluminum precursor according to an embodiment of the present invention, and H ₂ O is used as the oxidant precursor. The dielectric (insulation) layer through such an atomic layer deposition method has a disadvantage that the thickness of the film is low due to the low rate of thickness generation. However, in an embodiment of the present invention, a dielectric (insulation) layer is formed by repeatedly performing the number of cycles performed in order to form a multilayer dielectric layer in the atomic layer deposition chamber 200 as shown in FIG. 3. . The deposition through the atomic layer deposition method as described above has an advantage that the thickness can be controlled more precisely than the conventional deposition method in terms of thickness control.

The alumina layer corresponding to the dielectric layer obtained through the atomic layer deposition process S4 is transferred to the heater chamber 300 through the transfer chamber 400 shown in FIG. 2 to improve its electrical characteristics. The laminated dielectric layer is subjected to an annealing process (S5) in the heater chamber 300. At this time, the temperature rise condition of the heater chamber 300 is 25 ℃ / sec, the treatment time after raising to 400 ~ 600 ℃ temperature is N ₂ Heat is applied for 6 minutes to the atmosphere.

After the dielectric layer is deposited through the atomic layer deposition method as described above, the wafer is transferred back to the sputter chamber 100 through the transfer chamber 400. Then, the wafer transferred to the sputter chamber 100 is an internal electrode is formed by the deposition of copper of a predetermined thickness (S3), the wafer is transferred to the atomic layer deposition chamber 200 again alumina is deposited process It goes through (S4).

As such, the internal electrode through the sputtering method and the dielectric layer through the atomic layer deposition method are repeatedly formed (S3, S4, S5) to form a multilayer capacitor on the wafer.

In this case, since the deposition (S4) through atomic layer deposition is performed by atomic deposition, unlike the conventional sputtering method, several repetitive cycles shown in FIG. 3 are essential instead of a single deposition. That is, since the dielectric layer must be at least a certain thickness to function as the dielectric layer, atomic layer deposition requires more than 100 cycles.

In addition, the gas used in atomic layer deposition supplies TMA (tetra metyl aluminum) and IPA (Iso Prophyl alchole) to the inner atomic layer deposition chamber 200, and the atomic layer deposition similar to the CVD process in an atmosphere of 300 ~ 380 ℃ This is done to create an insulating layer on the inner electrode.

In addition, the deposition through the atomic layer deposition method can be set to have an average deposition rate of 0.8 ~ 3.2 Å / cycle per cycle (Cycle). At this time, the atomic layer deposition chamber 200 used in the embodiment of the present invention can be repeatedly performed in 100 to 200 cycles after the wafer is charged, thereby controlling the thickness of the dielectric layer.

In addition, the cycle sequence in the atomic layer deposition chamber 200 is, after heating the wafer substrate, as shown in Figure 3, aluminum source (TMA) gas supply, Ar / N ₂ purge, oxidant source ( In order of IPA / H ₂ O) inflow, Ar / N ₂ purge, a series of processes form one cycle as shown in FIG. 3. At this time, the capacity of the MLDC can be increased by increasing the number of stacked dielectric layers.

After the above process, the internal electrode is formed again through copper (Cu) deposition, and the process of FIG. 3 in which the alumina (AL ₂ O _{3 )} is deposited in the atomic layer deposition chamber 200 is repeated 100 times. . Therefore, according to an embodiment of the present invention, the internal electrode and the dielectric (insulation) layer may be cross-laminated, but the capacity of the MLDC may be adjusted and formed by controlling the number of cycles.

Subsequently, the wafer is subjected to a dicing step (S8), and a Sn and Ti metal film is formed as a plating layer on an outer surface to form an external electrode, and the manufacture of MLDC is completed.

This dry method does not require the high temperature sintering required for the production of the MLCC by the wet type, and has the advantage of minimizing the defects of the ceramic plate generated in the compression firing process after the operation.

Process progress according to an embodiment of the present invention is an in-situ process and a dry process, and does not require a sintering process at a high temperature separately, the generation of pores appearing on the ceramic plate by epitaxial growth through vacuum There is little advantage to this.

In addition, it is easy to control the deposition rate depending on time through the atomic layer deposition method, there is an advantage that can significantly reduce the thickness of the existing dielectric layer thickness.

1 is a flow chart of a multilayer deposition capacitor manufacturing method according to an embodiment of the present invention.

2 is a plan view of an atomic layer chamber, a sputter chamber and a transfer chamber performing the sequence of FIG.

3 is a cycle graph of the atomic layer deposition step of FIG.

<Explanation of symbols on main parts of the drawings>

100: sputter chamber 200: atomic layer deposition chamber

300: heater chamber 400: transfer chamber

Claims (8)

Sputter chamber 100 for depositing an electrode pattern, atomic layer deposition chamber 200 for temperature control for the deposition of the dielectric layer, heater chamber 300 for heat treatment, the sputter chamber 100 atomic layer deposition chamber 200 And using a laminated deposition capacitor manufacturing apparatus consisting of a transfer chamber 400 in charge of the transfer of the wafer between the heater chamber 300, An electrode pattern printing step of forming an internal electrode on the silicon wafer through a metal mast sputter process as a step performed in the sputter chamber 100; The atomic layer deposition process is performed in the atomic layer deposition chamber 200 in an Ar or N2 gas atmosphere, and sequentially performs an aluminum source gas supply, an Ar or N ₂ supply, and an oxidant source supply to form a monoatomic dielectric layer. Repeatedly performing a dielectric layer deposition step of forming a dielectric layer having a predetermined thickness;  A step performed in the heater chamber 300, the annealing step of heat treating the dielectric layer; A lamination step of repeatedly performing the electrode pattern printing step, the dielectric layer deposition step, and the annealing step; A wafer cutting step of cutting the wafer having multiple layers by repeating the electrode pattern printing step and the dielectric layer deposition step; An external electrode forming step of forming an external electrode on an outer surface of the wafer cut in the wafer cutting step; Laminated deposition capacitor manufacturing method comprising a. The method of claim 1, The electrode pattern formed in the electrode pattern printing step is a laminated deposition capacitor manufacturing method characterized in that the deposition by a sputtered copper (Cu) to a thickness of 800 ~ 1000 Å. The method of claim 1, The dielectric layer formed in the dielectric layer deposition step is a laminated deposition capacitor manufacturing method, characterized in that formed by alumina is deposited. The method of claim 3, wherein In the deposition of the alumina, Tri-Methyl-Aluminium (TMA) and Iso-prothyle-alchole (IPA) are used as a medium for the reactor. The method of claim 3, wherein In the deposition of the alumina TMA (Tri-Methyl-Aluminium) and H ₂ O is used as a medium of the reactor body, the deposition deposition capacitor manufacturing method characterized in that. The method of claim 1, The annealing step is a laminated deposition capacitor manufacturing method characterized in that the heat treatment at 400 ~ 600 ℃. The method of claim 1, The external electrode used in the external electrode forming step is a method of manufacturing a multilayer deposition capacitor, characterized in that formed with any one of Ni, Sn or Sn / Pb plating layer. delete

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