KR101068018B1 - Method for fabricating of compound semiconductor layer - Google Patents

Abstract

A method of forming a compound semiconductor is provided. The method of forming the compound semiconductor may include providing a group VI substrate from which an oxide film on the surface is removed, forming a group III-V compound seed layer grown horizontally on the substrate, and performing a lattice rearrangement of the seed layer. Rearranging the lattice of the seed layer and forming a III-V compound semiconductor layer made of the same compound as the seed layer on the seed layer.

Compound Semiconductor, Heat Treatment, Wet Etching, Reverse Phase Interface

Description

Method for fabricating of compound semiconductor layer

The present invention relates to a compound semiconductor, and more particularly to a method for forming a compound semiconductor layer.

Group III-V compound semiconductors are one of the fields that are widely studied because they can be applied not only to electronic devices such as diode transistors, but also to photovoltaic devices such as laser diodes, photodiodes or solar cells.

Group VI substrates are commonly used to use such compound semiconductors. However, the materials constituting the group VI substrate and the group III-V compound semiconductors have defects in the internal properties such as crystal structure, lattice constant or coefficient of thermal expansion, so that defects occur inside and surface uniformity is inferior. There is this.

Therefore, in order to solve this problem, a method such as inserting a buffer layer capable of reducing the lattice constant difference between the substrate and the compound semiconductor layer, or growing to a superlattice layer such as InGaAs / GaAs and GaAsP / GaAs has been proposed. . However, such a method causes problems such as enlarging the thickness of the layer, increasing the manufacturing cost, and the like. Accordingly, there is a need for a method of manufacturing a compound semiconductor layer that can reduce the internal defect density using a simple method without inserting a separate buffer layer.

The technical problem to be solved by the present invention is to provide a compound semiconductor manufacturing method that can grow a high quality compound semiconductor using a simple method.

In order to achieve the above technical problem, an aspect of the present invention provides a method of forming a compound semiconductor. The method of forming the compound semiconductor may include providing a group VI substrate from which an oxide film on the surface is removed, forming a group III-V compound seed layer grown horizontally on the substrate, and performing a lattice rearrangement of the seed layer. Rearranging the lattice of the seed layer and forming a III-V compound semiconductor layer made of the same compound as the seed layer on the seed layer.

The oxide layer may be removed by wet etching, and the wet etching may be performed using an etching solution of HF. In addition, the oxide film formed after the wet etching of the oxide film may be removed by heat treatment.

The seed layer may be formed at a temperature less than the temperature at which the chemical bonding is performed, the seed layer is a flow rate of the Group III precursor is 2.325 × 10 ^-5 to 4.186 × 110 ^-5 μmol / min, the flow rate of the Group V precursor Can be formed to be 4.464 × 10 ⁻³ to 8.036 × 10 ⁻³ μmol / min. In addition, the seed layer may be formed using 50 to 350 mol of Group V precursor with respect to 1 mol of the Group III precursor.

Rearranging the lattice of the seed layer may be performed in a group V precursor atmosphere, and the temperature at which the lattice may be rearranged may be 700 ° C. to 800 ° C. FIG.

As described above, since a high quality compound semiconductor layer can be formed by using a simple method and defect density is reduced and surface uniformity can be improved, a buffer layer for reducing the ratio of lattice constant or thermal expansion coefficient can not be inserted. Therefore, there is a feature that can reduce the thickness of the device in addition to reducing the manufacturing cost.

Such high quality compound semiconductors can be applied not only to electronic devices such as diode transistors, but also to optoelectronic devices such as laser diodes, photodiodes or solar cells.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

1A to 1D are cross-sectional views illustrating a method of forming a compound semiconductor layer according to an embodiment of the present invention. 2 is a schematic diagram showing a lattice structure between the substrate and the seed layer according to an embodiment of the present invention.

Referring to FIG. 1A, a substrate 10 is provided. The substrate 10 may be a group VI substrate. Specifically, the substrate 10 may be an Si substrate, an SiC substrate, or a Ge substrate, preferably an Si substrate, and more preferably an Si substrate having an upper surface (100) plane.

The Si substrate having the upper surface of the (100) plane may have a smaller lattice constant difference from the group III-V compound semiconductor than the Si substrate having the upper surface of the (100) plane. Therefore, the compound semiconductor formed using the Si substrate whose upper surface is the (100) surface may have a low internal defect density.

Referring to FIG. 1B, an oxide film existing on the surface of the substrate 10 is removed. On the surface of the substrate 10 may be an oxide film generated by the bonding with the outside oxygen. In the case of forming a layer directly on the oxide film, the interfacial energy between the layers may be increased to cause defects. Therefore, by removing the oxide layer, the interfacial energy between the compound semiconductor layers formed on the substrate 10 may be lowered, and the defect density in the layer may be reduced. The oxide film may be first removed by wet etching. The etchant may be HF. After performing the wet etching, the etching solution may be removed by air blowing using N ₂ .

1C and 2, the seed layer 12 is formed on the substrate 11. The substrate 11 may be accommodated in a chamber to form the seed layer 12. In this case, an oxide layer may be regenerated during the process of moving the substrate 11. This oxide film may be secondarily removed by the first heat treatment. The first heat treatment may be performed in a hydrogen or nitrogen atmosphere. In this case, the surface of the substrate 11 may be converted into a material having a lower melting point than the substrate 10 before wet etching by the following schemes 1 to 3 by the wet etching. Therefore, oxygen combined with the substrate 11 after the wet etching can be easily removed at a lower heat treatment.

<Scheme 1>

_{X + 2HF → XF 2 + 2H} + + 2e -

<Scheme 2>

2XF ₂ → X + XF ₄

<Scheme 3>

XF ₄ + 2HF → H ₂ XF ₆

In Schemes 1-3, X represents the material of the substrate surface.

The seed layer 12 may be a III-V group semiconductor layer grown horizontally. A potential such as an antiphase boundary (APB) may exist in the seed layer 12 due to the lattice constant difference between the substrate 11 and the seed layer 12. Since the dislocation propagates toward the predominant direction of the growth direction of the material, when the seed layer 12 has the vertical growth, the dislocation may propagate to the epi layer. Therefore, when the seed layer 12 is grown to have a dominant horizontal direction, dislocations in the seed layer 12 may be prevented from propagating to the epi layer.

The seed layer 12 may make horizontal growth of the seed layer 12 dominant by changing a growth temperature, a ratio of precursors, or a flow rate of precursors.

Specifically, the seed layer 12 may be formed at a low temperature. That is, the seed layer 12 may be formed at a temperature below the temperature at which chemical bonding between precursors is performed. Generally, when the temperature is higher than or equal to a predetermined temperature, growth perpendicular to the substrate 11 may be predominant because the materials constituting the seed layer 12 are given sufficient time to form chemical bonds by improving mobility.

However, when the seed layer 12 is formed below a predetermined temperature, the mobility of the materials constituting the seed layer 12 is reduced, so that vertical growth due to chemical bonding is sharply reduced, so that the substrate 11 is relatively reduced. ) Horizontal growth prevails. The seed layer 12 may be formed at a temperature of 300 ℃ to 450 ℃. When the growth temperature of the seed layer 12 is set to less than 300 ° C., the formation of the seed layer 12 may be difficult. When the seed layer 12 is set to 450 ° C. or more, the seed layer 12 may be vertically grown.

In addition, the seed layer 12 may be formed using 50 to 350 mol of Group V precursor with respect to 1 mol of the Group III precursor. The Group III precursor has a higher mobility than the Group V precursor. Therefore, in order to form the seed layer 12 using the precursors, the Group V precursor may be injected relatively more than the Group III precursor.

Here, as the group V precursor is closer to 50 moles with respect to 1 mole of the group III precursor, the seed layer 12 having superior horizontal growth may be formed. Specifically, the group III precursor is actively moved onto the substrate 11 while maintaining a constant molar ratio. However, when the molar ratio of the Group V precursor for forming the Group III / V seed layer 12 is reduced, it may be difficult to form a sufficient thickness of the Group III / V seed layer, so that the horizontal growth is relatively higher than the vertical growth. Can prevail.

In addition, when the seed layer 12 has the same ratio of Group III / V precursors and the amount of precursors is the same, the flow rate of the Group III precursors is 2.325 × 10 ⁻⁵ to 4.186 × 10 ⁻⁵ μmol / min. The flow rate of the Group V precursor may be 4.464 × 10 ⁻³ to 8.036 × 10 ⁻³ μmol / min. In this case, the flow rate of the Group III precursor may be set to be close to 4.186 × 110 ⁻⁵ μmol / min, and the flow rate of the Group V precursor may be set to be close to 8.036 × 10 ⁻³ μmol / min.

When the flow rate of the precursors is increased, the growth rate may be faster because the amount of precursors introduced into the chamber per minute is increased. When the growth rate is fast, there is not enough time for the precursors to achieve chemical bonding, so that horizontal growth may be superior to vertical growth.

The seed layer 12 may be a III-V compound semiconductor layer. For example, the seed layer 12 may be a GaAs layer, an InP layer, a GaP layer, a GaAlAs layer, or an InGaP layer. The seed layer 12 may be formed using a MOCVD technique.

After the seed layer 12 is formed, the surface temperature of the seed layer 12 may be raised to a temperature at which lattice rearrangement is possible, thereby rearranging the lattice of the seed layer 12. When the seed layer 12 is exposed to a temperature at which lattice rearrangement is possible, the lattice in the seed layer 12 may be rearranged in a pyramid structure to form an antiphase interfacial dissipation mechanism. Accordingly, the defect density in the seed layer 12 may be reduced.

The temperature at which the lattice arrangement is possible may be 700 ° C. to 800 ° C. When the temperature of the surface of the seed layer 12 is increased, the group V precursor may be volatilized, and thus the temperature increase may be performed in a group V precursor atmosphere.

Referring to FIG. 1D, the seed layer 12 may be subjected to a second heat treatment 13 and grown to form a III-V compound semiconductor layer 14 made of the same compound as the seed layer 12. In this case, the compound semiconductor layer 14 may be maintained at a temperature at which the lattice rearrangement of the seed layer 12 is completed. That is, the second heat treatment may be performed at a temperature in the range of 700 ° C to 800 ° C.

The III-V compound semiconductor layer 14 may be a GaAs layer, an InP layer, a GaP layer, a GaAlAs layer, or an InGaP layer. The compound semiconductor layer 14 may be formed using a MOCVD technique.

Since the compound semiconductor layer 14 is grown using the seed layer 12 having reduced internal defects, the compound semiconductor layer 14 may also have less internal defects. In addition, since the compound semiconductor layer 14 has the same structure as the seed layer 12, no additional defects are generated due to mismatch of the lattice. Therefore, a high quality compound semiconductor with few internal defects can be ensured.

Therefore, as described above, the compound semiconductor layer according to the embodiment of the present invention can reduce the defect density and improve the surface uniformity, so that a buffer layer for reducing the ratio of lattice constant or thermal expansion coefficient can not be inserted. have. Therefore, there is a feature that can reduce the thickness of the device in addition to reducing the manufacturing cost.

Such high quality compound semiconductors can be applied not only to electronic devices such as diode transistors, but also to optoelectronic devices such as laser diodes, photodiodes or solar cells.

Experimental Example 1: Evaluation of Compound Semiconductor Layer Characteristics According to Etching Solution Type

3 is a graph showing the heat treatment temperature for each layer to form a compound semiconductor layer according to Experimental Example 1. FIG.

Referring to FIG. 3, three Si substrates having an upper surface of (100) were prepared, and wet etching was performed for 1 minute using HCl, NaOH, and HF etching solutions, respectively, to remove oxide films on the substrate. After the oxide film was first removed, the etchant was removed using N ₂ blowing. Subsequently, the substrate was accommodated in a chamber, and the oxide film was secondarily removed by performing a first heat treatment at a temperature of 750 ° C. for 20 minutes. At this time, the first heat treatment was performed in a nitrogen atmosphere.

Each substrate from which the oxide film was removed was reduced to 400 ° C., and then a GaAs seed layer was formed for 10 minutes using TMGa and AsH ₃ sources. In this case, the GaAs seed layer was formed by setting AsH ₃ to 192 moles per 1 mole of TMGa and injecting precursors for 30 minutes. The GaAs seed layer was formed using MOCVD techniques. Thereafter, the temperature was raised to a high temperature of 700 ° C. again to rearrange the lattice of the seed layer, and then the GaAs semiconductor layer was grown by MOCVD.

4 to 6 are SEM images, XRD graphs, and PL graphs respectively showing the state of the shape change of the compound semiconductor layer according to the oxide removal efficiency. 4 to 6, (a), (b) and (C) show a case where HCl, NaOH and HF were used as wet etching solutions for removing an oxide film, respectively.

Referring to FIG. 4, the etching solution of HF (c) of the compound semiconductor layers grown on the substrate after wet etching using the etching solution of each of HCl (a), NaOH (b), and HF (c) is used. The surface of the compound semiconductor layer formed on the substrate after removing the oxide film was the most uniform. Through this, it can be seen that the oxide film removal efficiency affects the compound semiconductor layer, and it can be predicted that HF is effective for removing the oxide film among the oxide film removal etching solutions.

Referring to FIG. 5, the compound semiconductor layers formed on the substrate from which the oxide film was removed using the etching solution of HCl (a) and NaOH (b) did not completely form a crystal structure of the compound semiconductor. It can be seen that the compound semiconductor layer formed on the substrate from which the oxide film was removed using the etching solution formed a complete crystal structure of GaAs. Accordingly, it can be confirmed that the presence or absence of the oxide film affects the crystal structure of the compound semiconductor layer.

Referring to FIG. 6, the compound semiconductors formed on the substrates after removing the oxide film using the etching solution of HCl (a) and HF (C) emit infrared light in the infrared wavelength range of 800 ° C. to 900 ° C. It can be expected to be applied to devices such as.

As described above with reference to FIGS. 4 to 6, it may be determined that the compound semiconductor according to the exemplary embodiment of the present invention can reduce defects and improve surface uniformity only by removing the oxide film on the substrate.

Experimental Example 2: Evaluation of Compound Semiconductor Layer Characteristics According to the First Heat Treatment Variation

In the same manner as in Experiment 1, the oxide film was first removed using HF, and the oxide film was secondarily removed by performing the first heat treatment temperature at 780 ° C.

7 to 9 are SEM images, XRD graphs, and PL graphs showing the shapes of the compound semiconductors according to Experimental Example 2;

Referring to FIG. 7, the compound semiconductor layer formed on the substrate from which the oxide film was secondly removed by performing a first heat treatment at 780 ° C. according to Experimental Example 2 was subjected to a first heat treatment at 750 ° C. according to Experimental Example 1 to form an oxide film. It can be seen that the surface uniformity is improved compared to the compound semiconductor layer formed on the substrate (C of FIG. 4) removed second. Through this, it can be seen that the secondary removal of the oxide film is affected by the temperature of the heat treatment in addition to the type of etching solution, and it is determined that the oxide film is easily removed as the temperature is higher.

Referring to FIGS. 8 and 9, as a result of XRD analysis, it may be confirmed that a complete compound semiconductor layer is formed (FIG. 8), and as a result of PL analysis, light emission may be generated in an infrared wavelength region (FIG. 9). Therefore, such compound semiconductors can be applied to devices using infrared wavelengths.

Experimental Example 3: Evaluation of Compound Semiconductor Characteristics According to Seed Layer Formation Conditions

No. TMGa (mol) AsH ₃ (mol) Precursor injection time (minutes) Preparation Example 1 One 57 30 Production Example 2 One 192 30 Production Example 3 One 345 30

Table 1 shows the molar ratio change condition of the precursors for forming the seed layer, Figure 10 shows SEM images showing the surface characteristics of the compound semiconductor according to Preparation Examples 1 to 3.

10 and Table 1, when the seed layer is formed by reducing the mole of AsH ₃ from Preparation Example 3 to Preparation Example 1 with respect to 1 mol of TMGa, the compound semiconductor layer formed on the seed layer has a uniform surface It can be seen that this is improved and there are fewer internal defects. This is because it is difficult to form a sufficient thickness as the Group V precursor relative to the Group III precursor is relatively reduced, and it is considered that the horizontal growth is superior to the vertical growth.

No. TMGa (μmol / min) AsH ₃ (μmol / min) Precursor injection time (minutes) Preparation Example 1 6.976 × 10 ^-6 1.339 × 10 ^-3 100 Production Example 2 2.325 × 10 ^-5 4.464 × 10 ^-3 30 Production Example 3 4.186 × 10 ^-5 8.036 × 10 ^-3 17

Table 2 shows the change conditions of the flow rate of the precursors, Figure 11 shows the SEM images showing the surface characteristics of the compound semiconductor according to Preparation Examples 4-6. At this time, the flow rate of the precursors were changed, but the amount injected was the same.

11 and Table 2, it was found that the compound semiconductor layer grown using the seed layer formed by increasing the flow rates of the TMGa and AsH ₃ precursors from Preparation Example 4 to Preparation Example 6 has a uniform surface and few internal defects. Can be. This is because the increase in the amount of precursors introduced into the chamber for the same time does not give enough time for the chemical bonding of a large amount of precursors, so that the horizontal growth is superior to the vertical growth.

As described above, the compound semiconductor according to the embodiment of the present invention has an internal defect density by using an oxide layer on the substrate using an etching solution, and a seed layer having reduced internal defect density by controlling a ratio of precursors and a flow rate of precursors. A reduced quality compound semiconductor layer can be obtained.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes by those skilled in the art within the spirit and scope of the present invention. This is possible.

1A to 1D are cross-sectional views illustrating a method of forming a compound semiconductor layer according to an embodiment of the present invention.

2 is a schematic diagram showing a lattice structure between the substrate and the seed layer according to an embodiment of the present invention.

3 is a graph showing the heat treatment temperature for each layer to form a compound semiconductor layer according to Experimental Example 1. FIG.

FIG. 4 is an SEM image showing a shape change state of a compound semiconductor layer according to oxide removal efficiency.

FIG. 5 is an XRD graph showing a shape change state of a compound semiconductor layer according to oxide removal efficiency. FIG.

 6 is a PL graph showing a state of changing the shape of a compound semiconductor layer according to oxide removal efficiency.

7 is an SEM image showing the shape of the compound semiconductor according to Experimental Example 2. FIG.

8 is an XRD graph showing a shape of a compound semiconductor according to Experimental Example 2. FIG.

9 is a PL graph showing the shape of the compound semiconductor according to Experimental Example 2. FIG.

10 are SEM images showing surface characteristics of compound semiconductors according to Preparation Examples 1 to 3;

11 are SEM images showing surface characteristics of compound semiconductors according to Preparation Examples 4 to 6. FIG.

Claims (9)

Providing a Group VI substrate from which an oxide film on the surface has been removed; Forming a group III-V compound seed layer grown horizontally on the substrate; Rearranging the lattice of the seed layer by raising the seed layer to a temperature at which lattice rearrangement is possible; And Forming a group III-V compound semiconductor layer formed of the same compound as the seed layer on the seed layer. The method of claim 1, And removing the oxide film by wet etching. The method of claim 2, Wherein the wet etching is performed using an etchant of HF. The method of claim 2, And removing the oxide film formed by wet etching the oxide film by heat treatment. The method of claim 1, The seed layer is a compound semiconductor forming method to form at 300 ℃ to 450 ℃. The method according to claim 1, The seed layer is formed by the flow rate of the Group III precursor is 2.325 × 10 ^-5 to 4.186 × 110 ^-5 μmol / min, the flow rate of the Group V precursor is 4.464 × 10 ^-3 to 8.036 × 10 ^-3 μmol / min Compound semiconductor formation method. The method of claim 1, And the seed layer is formed using 50 to 350 moles of Group V precursor with respect to 1 mole of Group III precursor. The method of claim 1, Rearranging the lattice of the seed layer is performed in a group V precursor atmosphere. The method of claim 1, The temperature at which the lattice rearrangement is possible is 700 to 800 ° C.

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