KR101062290B1 - Method for forming contact plug of semiconductor device - Google Patents

Abstract

The present invention discloses a method for forming a contact plug of a semiconductor device capable of reducing heat treatment time while preventing heterogeneous nucleation upon formation of epi silicon. According to an aspect of the present invention, there is provided a method of forming a contact plug, comprising: providing a silicon substrate having several gate electrodes formed thereon, depositing a gate buffer oxide film and a gate sealing nitride film on the entire surface of the substrate on which the gate electrodes are formed; Forming a junction region in the substrate region between the electrodes, sequentially depositing a gate spacer nitride film and an interlayer insulating film on the substrate resultant, etching the interlayer insulating film, the gate spacer nitride film, the gate sealing nitride film, and the gate buffer oxide film Forming a landing plug contact hole simultaneously exposing several gate electrodes and a substrate junction region therebetween, wherein the epi-silicon is grown on the substrate junction region and the amorphous silicon is grown on the substrate junction region. Growing silicon thin film Removing the amorphous silicon on the gate electrode to remove the nucleation sites at the upper end of the contact, and performing heat treatment on the substrate resultant to convert the remaining amorphous silicon in the landing plug contact hole into epi-silicon. Regrowth.

Description

Method for forming contact plug of semiconductor device

1A to 1F are cross-sectional views illustrating processes for forming a contact plug according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1: silicon substrate 2: device isolation film

3: gate oxide film 4: gate conductive film

4a: polysilicon film 4b: metal film

5: nitride film for hard mask 6: gate electrode

7: gate sealing nitride film 8: junction region

9 gate spacer nitride film 10 interlayer insulating film

11: Landing plug contact hole 13: Epi-silicon

14: amorphous-silicon 15: landing plug

15a: contact plug

The present invention relates to a method for forming a contact plug of a semiconductor device, and more particularly, to a method for forming a contact plug which can reduce heat treatment time while preventing heterogeneous nucleation upon formation of epi silicon.

As the integration of semiconductor devices progresses, the gate length becomes smaller, and accordingly, excessive threshold voltage control ion implantation is inevitably required in order to obtain an appropriate threshold voltage (Vt). In addition, refresh characteristics and current driving force are required. It is essential to reduce the contact resistance and to avoid unwanted diffusion of the dopant to obtain

Here, when polysilicon is used in the plug process as the contact material, it is common to do a phosphorus (P) order of approximately -1E20 order in order to obtain an appropriate contact resistance, and this phosphorus (P) is used in a subsequent thermal process. As a result, diffusion into the junction region or the cell transistor adversely affects the refresh characteristics. On the other hand, if the doping concentration of phosphorus (P) is unconditionally lowered, since the contact resistance increases and the current driving ability is greatly reduced, it is essential to secure appropriate process conditions.

On the other hand, in forming the contact plug, when there is a defect at the interface between the substrate surface and the contact plug, device reliability is lowered.

Therefore, in order to solve such a problem, a method of using epi-silicon (epi-Si) as a contact material has been proposed. When the epi-silicon is used as a plug, even if the doping concentration of phosphorus (P) is low, the contact resistance can be lowered because the interface property is improved. However, since the epitaxial growth process has a high thermal budget, a plug structure having a low thermal budget and excellent interfacial properties between the substrate surface and the contact plug is required.

As one of the methods for forming the epi-silicon, a solid phase epitaxy (SPE) method has been developed. This SPE method is a method of depositing amorphous-silicon at a low temperature of about 500 to 650 ° C., followed by subsequent heat treatment in a temperature range of 500 to 800 ° C. to allow epi-silicon to grow.

However, in the SPE method, in order to recrystallize amorphous silicon deposited through a subsequent heat treatment, epi silicon grows at the contact interface, but nucleation occurs at a portion other than the substrate active region that becomes seed when the heat treatment temperature is high. And it is difficult to improve the contact characteristics because the recrystallization is easily formed partly polysilicon, on the other hand, if the heat treatment temperature is low may be a problem during mass production due to excessive heat treatment time.

In detail, Y. M. Ha et al., J. Elec. Mat., Vol. 23, No. 1 p. 39 (1994), when amorphous-silicon is deposited on a clean silicon (Si) surface, epi-silicon grows to a certain thickness, but then amorphous-silicon grows. Therefore, the amorphous-silicon must be regrown to epi-silicon. For this purpose, if the resultant heat treatment is performed at 500 to 800 ° C., the amorphous-silicon grows to epi-silicon with the epi-silicon as a seed. First of all, when the heat treatment temperature is high, nucleation at these interfaces is related to the presence of heterogeneous interfaces such as deposited amorphous-silicon and contact walls or silicon / silicon oxide films or silicon / silicon nitride films on top of the contacts. This results in the growth of poly-silicon, which causes the plug material to be mixed with epi-silicon and poly-silicon, resulting in high sheet resistance of poly-silicon, which is almost 10 times higher than epi-silicon. It can only be reduced. On the other hand, when the heat treatment temperature is lowered, the heterogeneous nucleation can be suppressed to some extent, but the heat treatment time becomes longer, which leads to a significant decrease in mass productivity.

Therefore, the present invention has been made to solve the above problems, forming a contact plug of a semiconductor device that can reduce the heat treatment time while preventing heterogeneous nucleation in forming a contact plug made of epi-silicon according to the SPE method The purpose is to provide a method.

Another object of the present invention is to provide a method for forming a contact plug of a semiconductor device capable of securing mass productivity through reduction of heat treatment time while securing contact characteristics through prevention of heterogeneous nucleation.

In order to achieve the above object, the present invention comprises the steps of providing a silicon substrate formed with several gate electrodes; Sequentially depositing a gate buffer oxide film and a gate sealing nitride film on the entire surface of the substrate on which the gate electrodes are formed; Forming a junction region in the substrate region between the gate electrodes; Sequentially depositing a gate spacer nitride film and an interlayer insulating film on the substrate resultant; Etching the interlayer insulating film, the gate spacer nitride film, the gate sealing nitride film, and the gate buffer oxide film to form a landing plug contact hole exposing several gate electrodes and a substrate junction region therebetween at the same time; Growing a silicon thin film on the substrate output such that epi-silicon is grown on the substrate junction region and amorphous-silicon is grown thereon; Removing amorphous silicon on the gate electrode such that nucleation sites at the top of the contact are removed; And re-growing the amorphous-silicon remaining in the landing plug contact hole to epi-silicon by performing heat treatment on the substrate resultant.

Here, the growth of the silicon thin film is carried out at a pressure of 1 ~ 100 Torr and a temperature of 550 ~ 650 ℃, heat treatment to regrow the amorphous-silicon into epi-silicon 30 minutes at a temperature of 500 ~ 700 ℃ and nitrogen atmosphere Do more than

In addition, in the method for forming a contact plug of a semiconductor device according to the present invention, after the forming of the landing plug contact hole and before the growing of the silicon thin film, dry and wet cleaning and hydrogen baking are performed to obtain a clean contact surface. It further comprises the step of performing the configured pretreatment process.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention will be described.

When epi-silicon is grown according to the SPE method, the location where heterogeneous nucleation occurs is at the top of the contact. The cause of this is not clear at present, but it is presumed to be due to the activation of the ion implantation damage (implantation damage) relative to the upper end of the contact.

Therefore, by removing the upper end portion of the contact, it is possible to ensure a condition where heterogeneous nucleation does not occur, and also to form a good epi-silicon contact plug while reducing the heat treatment time.

Accordingly, the present invention removes the amorphous-silicon of the gate top with an etch back or CMP, etc. before proceeding with the subsequent thermal process for regrowing the amorphous-silicone into epi-silicon, and then the amorphous-silicone to epi-silicon Regrow.

In this case, since the upper portion of the contact in which the ion implantation damage is generated is removed, the contact characteristics can be secured by restraining heterogeneous nucleation as much as possible in the subsequent thermal process for re-growing amorphous silicon to epi-silicon. By increasing the heat treatment temperature, the heat treatment time can be relatively reduced to improve mass productivity.

1A to 1F are cross-sectional views illustrating processes for forming a contact plug according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, after the device isolation layer 2 is formed in place of the silicon substrate 1 according to a shallow trench isolation (STI) process, ion implantation for well formation and ion implantation and threshold voltage for punchthrough prevention are performed. Ion implantation is performed in order. Then, the gate oxide film 3, the gate conductive film 4, and the hard mask nitride film 5 are sequentially formed on the entire surface of the silicon substrate 1, and then patterned to form the gate electrode 6. do.

The gate conductive film 4 may be formed of a single film of the polysilicon film 4a or the metal film 4b, or may be formed of a laminated film of the polysilicon film 4a and the metal film 4b. As the metal film 4b, tungsten silicide or tungsten having excellent stability at high temperature is preferably used.

Referring to FIG. 1B, a thermal oxidation or CVD process is performed to form a gate buffer oxide film (not shown) on the substrate resultant, followed by primary ion implantation to form a junction region. Thereafter, after the gate sealing nitride film 7 is deposited on the entire surface of the substrate 1, secondary ion implantation is performed to form the junction region 8. At this time, since the formation of the junction region 8 is performed in two times, the impurity doping profile in the junction region 8 is relaxed to reduce the concentration of the electric field at the ends of the gate electrode 6, and thus the junction region 8 is formed. The leakage current at can be reduced.

Subsequently, although not shown, after forming the junction region of the peripheral circuit portion transistor according to a known method, the gate spacer nitride film 9 is deposited on the entire surface of the substrate. Then, after the interlayer insulating film 10 is deposited on the gate spacer nitride film 9, the interlayer insulating film 10, the gate spacer nitride film 9, and the gate sealing nitride film are processed by a landing plug contact process. (7) and the gate buffer oxide film are sequentially etched to form a contact hole, that is, a landing plug contact hole 11, which simultaneously exposes several gate electrodes 6 and the substrate bonding region 8 therebetween.

Referring to FIG. 1C, a pretreatment process, that is, dry and wet cleaning, and hydrogen (H 2) baking are sequentially performed on a substrate resultant in which the landing plug contact hole 11 is formed to obtain a clean contact interface.

Here, the pretreatment process sets the process conditions for the purpose of complete removal of etch residues generated during etching for forming the landing plug contact hole, removal of etch damage, and removal of the natural oxide film of the cell contact surface. Specifically, the removal of the etch residue and the etch damage is performed in the NF3 / He / O2 series, CF4 / O2 series, or Ar / in a remote plasma or low power plasma state after cell contact etching and photoresist removal. It proceeds to light etching by reaction gas, such as O2 series. Such micro-etching process removes polymeric etching residues such as CF, CO, and CC generated during cell contact etching, and after micro-etching, 1 to 4 surfaces on the cell contact silicon due to the oxygen gas supplied during micro-etching. A silicon oxide film of about nm is produced. Therefore, after micro-etching, fluorine-based pre-cleaning such as wet cleaning using HF or BOE solution or steam cleaning using HF steam is performed to remove the silicon oxide film formed on the cell contact silicon surface.

In addition, it is necessary to suppress the contamination or the formation of the interfacial oxide film before the deposition from the time of loading the pre-cleaned substrate into the silicon deposition equipment. Therefore, the substrate which has been pre-cleaned is charged to the deposition equipment within at least 4 hours, and at the time of charging, even if it is kept at a vacuum or charged at atmospheric pressure, it is purged with inert gas such as high purity nitrogen and argon, and the oxygen concentration is 10 ppm or less. Keep it. It is a reaction chamber with a high temperature of 400 ℃ or higher, and when the oxygen concentration in the substrate is 10ppm or more, a surface oxide film of 0.5 nm or more is formed at the contact interface. As a result, the single crystal silicon of the substrate bonding region is seeded during the subsequent thermal process for epi silicon growth. This is because the cell contact landing plugs are all crystallized from polysilicon because they cannot play a role.

Therefore, hydrogen baking is performed at a temperature of 750 ° C. or higher after the loading of the substrate and before the deposition of the amorphous silicon for more reliable removal of the interfacial oxide film, and through this, the interface generated during the transfer to the substrate and the loading into the deposition equipment. Completely remove the oxide film.

Referring to FIG. 1D, a silicon thin film is grown on the interlayer insulating film 10 including the landing plug contact hole 11. At this time, at the contact interface, the single crystal silicon of the substrate junction region 8 acts as a seed, and the epi-silicon 13 is grown, and the amorphous silicon is grown thereon. At this time, the silicon deposition is carried out at a pressure of 1 to 100 Torr and a temperature of 550 to 650 ° C to allow the epi-silicon 13 to be grown on the contact interface and to grow to the amorphous-silicon 14 otherwise. In addition, the phosphorus (P) doping concentration in the thin film is adjusted in the range of 1E19 to 1E20 atoms / cm 3 in consideration of the thermal summation, that is, the thermal budget, which adds up the entire thermal process applied during the subsequent integration process of the device.

Referring to FIG. 1E, the amorphous-silicon 14 is etched back or CMP such that the gate electrode 6 is exposed, thereby primarily forming a bit line on the substrate junction region 8 between the gate electrodes 6. A landing plug 15 that is a contact and a storage node contact is formed. At this time, the ion implantation damage of the upper portion of the contact is removed by performing the etch back or CMP on the amorphous-silicon 14, and thus, nucleation sites are removed so that heterogeneous nucleation does not occur during subsequent thermal processes. Will not.

Referring to FIG. 1F, the substrate resulted to the above step is subjected to a subsequent thermal process at a temperature of 500 to 700 ° C. and a nitrogen atmosphere for at least 30 minutes, through which the epi-silicon grown on the contact interface remains as a seed. The amorphous-silicon thus formed is recrystallized from epi-silicon to form a landing plug, that is, a contact plug 15a, which is finally made of epi-silicon 13.

Here, since the nucleation site is removed through the etch back or CMP in the previous process step, the gate spacer nitride film 9 or the interlayer insulating film 10, which is a wall of the contact, is formed while the amorphous silicon is recrystallized into epi-silicon. Nucleation and crystal growth do not occur at the amorphous-silicon interface, and therefore, recrystallization into poly-silicon at the upper end of the contact can be suppressed to secure contact properties, while heat treatment is performed by increasing the heat treatment temperature. Reduced time can be used to increase productivity.

Subsequently, a series of known subsequent processes are sequentially performed to complete the semiconductor device.

As described above, the present invention removes the nucleation site where heterogeneous nucleation occurs by etch back or CMP after the initial epi-silicon growth in forming the contact plug by applying the SPE method to reduce the heat treatment temperature during the subsequent thermal process. While it is possible to increase the contact characteristics by suppressing heterogeneous nucleation as high as possible, on the other hand, by increasing the heat treatment temperature, heat treatment time can be relatively reduced to improve mass productivity.

Therefore, since the present invention uses the epi silicon layer as the contact material, not only the contact characteristics but also the refresh characteristics can be improved, and the mass productivity can be improved.

Hereinbefore, the specific embodiments of the present invention have been described and illustrated, but modifications and variations can be made by those skilled in the art. It is understood to include variations.

Claims (4)

Providing a silicon substrate having several gate electrodes formed thereon; Forming a gate buffer oxide layer on an entire surface of the substrate on which the gate electrodes are formed; Performing primary ion implantation to form a junction region on the substrate product on which the gate buffer oxide film is formed; Depositing a gate sealing nitride film on the substrate resulted from the primary ion implantation; Performing secondary ion implantation on a substrate resultant on which the gate sealing nitride film is formed to form a junction region in a substrate region between the gate electrodes; Sequentially depositing a gate spacer nitride film and an interlayer insulating film on a substrate resultant in which the junction region is formed in the substrate region between the gate electrodes; Etching the interlayer insulating film, the gate spacer nitride film, the gate sealing nitride film, and the gate buffer oxide film to form a landing plug contact hole exposing several gate electrodes and a substrate junction region therebetween at the same time; Growing a silicon thin film on a substrate product on which the landing plug contact hole is formed such that epi-silicon is grown on the substrate junction region and amorphous silicon is grown thereon; Removing amorphous silicon on the gate electrode such that nucleation sites at the top of the contact are removed; And Performing a heat treatment on the amorphous silicon-substrate substrate on the gate electrode to regrow the amorphous silicon in the landing plug contact hole to epi-silicon; Contact plug forming method of a semiconductor device comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, further comprising performing a pretreatment process consisting of dry and wet cleaning and hydrogen bake to obtain a clean contact surface after forming the landing plug contact hole and before growing the silicon thin film. Method for forming a contact plug of a semiconductor device comprising a. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, wherein the growing of the silicon thin film A contact plug forming method of a semiconductor device, characterized in that carried out at a pressure of 1 ~ 100 Torr and a temperature of 550 ~ 650 ℃. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, wherein the heat treatment for regrowing the amorphous silicon to epi-silicon is performed for 30 minutes or more at a temperature of 500 to 700 ° C. and a nitrogen atmosphere.

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