KR101060692B1 - Method for forming semiconductor device - Google Patents

Abstract

In the method of forming a semiconductor device of the present invention, a first spacer is formed on sidewalls of a vertical pillar on a semiconductor substrate, an ion implantation region is formed on the semiconductor substrate between the vertical pillars, and the ion implantation region is etched to form a trench. And forming a buried bit line by forming a silicide layer in the trench, etching the semiconductor substrate to separate the silicide layer and the ion implantation region, and forming a buried bit line on the sidewall of the vertical pillar. By forming a layer, a gap between the buried bit line and the gate can be prevented from being shorted by forming a silicide layer on the buried bit line after offset with the gate, and damascene after depositing a material having a different interlayer insulating film and selectivity around the pillar. Gate insulating film and gate by self-alignment by removing in word line forming process The process margin is secured by securing a space for depositing a conductive layer.

Vertical transistor

Description

Method for forming semiconductor device

The present invention relates to a method of forming a semiconductor device, and a method of forming a vertical transistor.

As the degree of integration of semiconductor devices improves, the channel length of the transistors decreases as the transistor size decreases to form more devices in a limited region.

As the channel length of the transistor decreases, grooves are formed in the channel region to extend the channel length relatively to solve the problem that the semiconductor device does not operate normally due to an effect such as a short channel effect (SCE). Vertical transistor technology has been developed to form or form a transistor in a vertical structure.

Vertical transistors include a surrounding gate electrode structure with a vertical channel structure in a horizontal channel structure and suitable for integrating a giga bit level transistor in a confined region and surrounding the vertical channel structure. do.

Such vertical transistors are very effective in solving problems such as short channel effects because they can maintain a constant channel length even when the device area is reduced. In particular, the rounding gate can maximize gate controllability, so that not only short channel effects The area through which the current flows is the widest to provide excellent current characteristics.

In order to increase the degree of integration in a limited area, vertical transistors include pillars that are confined within a semiconductor substrate because a long and elongated structure with a high aspect ratio is required.

A brief description will be given of a method of forming a vertical transistor according to the prior art.

First, a vertical pillar is formed by etching a semiconductor substrate using a photolithography process using a mask defining an active region. Next, a surround gate surrounding the vertical pillars is formed, and impurities are implanted into the semiconductor substrate between the surround gates to form bit line impurity regions. Next, the semiconductor substrate between the surround gates is etched to form a separated buried bitline (BBL). At this time, the etching depth of the semiconductor substrate should be greater than or equal to the depth of the bit line impurity region. In other words, the semiconductor substrate must be etched very deeply to prevent short circuit between buried bit lines.

In this case, after the surround gate is formed, the overlap margin between the junction region and the gate is reduced by an impurity ion implantation process, thereby increasing the resistance (Rs) or when the semiconductor substrate is excessively etched to form a separate buried bit line. There is a problem that the resistance of the buried bit line is increased by reducing the absolute volume of the line. In addition, if a high concentration of ion implantation is performed directly on the silicon substrate when the buried bitline is formed, the body floating phenomenon is caused by the diffusion of impurities, and the performance of the transistor is deteriorated. Reducing it increases the resistance of the buried bit line. In addition, as the integration becomes gradually higher, the gap between the pillars and the pillars becomes narrower, causing misalignment during surround gate patterning, thereby increasing the possibility of shorting of adjacent cells.

According to the present invention, in the vertical transistor formation method, as the gap between pillars and pillars is narrowed due to high integration of semiconductor devices, the margin of buried bitlines is reduced, and misalignment occurs when patterning gates and word lines, and thus adjacent cells are formed. It is intended to solve the problem of lowering the semiconductor yield by generating a short and causing a defect.

In the method of forming a semiconductor device of the present invention, forming a first spacer on a vertical pillar sidewall on a semiconductor substrate, forming an ion implantation region on the semiconductor substrate between the vertical pillars, and etching the ion implantation region. Forming a trench, forming a silicide layer in the trench, etching the semiconductor substrate to separate the silicide layer and the ion implantation region, and forming a buried bit line; and forming a gate on the sidewall of the vertical pillar. Forming an insulating film and a gate conductive layer.

At this time. The forming of the first spacer on the sidewalls of the vertical pillars may include forming a pad oxide layer and a hard mask layer on the semiconductor substrate, forming a photoresist pattern defining an active region on the hard mask layer, and forming the photoresist layer. Forming a vertical pillar by etching the hard mask layer, the pad oxide layer, and the semiconductor substrate using an pattern as an etch mask, and oxidizing the semiconductor substrate to form a buffer oxide layer on sidewalls of the vertical pillar and the semiconductor substrate. And forming a capping insulating film on the entire surface and etching the entire surface of the capping insulating film to expose the ion implantation region.

In this case, the capping insulating film is characterized in that the nitride film.

The forming of the trench may include forming the ion implantation region using the first spacer as an etch mask to form a first trench, forming a second spacer on sidewalls of the first trench, and forming the second trench. And etching the first trench using an spacer as an etch mask to form a second trench.

The forming of the second spacer may include forming a second spacer insulating film on the first spacer and etching the entire surface of the second spacer insulating film to expose the ion implantation region. do.

At this time, the second spacer insulating film is characterized in that the liner nitride film.

The second trench may be formed in the ion implantation region.

At this time. The forming of the silicide layer may include forming a metal layer on the trench and performing heat treatment on the metal layer.

And, the metal layer is characterized in that the titanium or cobalt.

The forming of the buried bit line may include forming a sacrificial insulating layer on the entire upper portion including the second trench, forming a photoresist pattern on the sacrificial insulating layer, and using the photoresist pattern as an etch mask. It characterized in that it comprises a step of etching.

After the forming of the buried bit line, the method may further include forming an interlayer insulating film that insulates the buried bit line and removing the interlayer insulating film and the first spacer.

The forming of the interlayer insulating film may include forming an insulating film so that the buried bit line is buried and etching the insulating film so that the second trench in which the silicide layer is formed is not exposed.

The removing of the first spacer may be performed by using a self-aligning method.

The forming of the gate conductive layer may include forming a surround gate and forming a damascene word line connecting the surround gate.

In this case, the gate conductive layer is any one selected from the group consisting of a laminated structure of a titanium nitride (TiN) film, a tantalum nitride (TaN) film and a titanium nitride (TiN) film, and a stacked structure of a titanium nitride (TiN) film and a tungsten (W) film. It is characterized by one.

In the method of forming a vertical transistor, the buried bit line and the gate can be prevented from shorting by forming a silicide layer in the buried bit line after offset with the gate. By depositing the material and removing it in the damascene word line forming process, the process margin is secured by securing a space for depositing the gate insulating film and the gate conductive layer in a self-aligned manner.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

1A to 1M are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

As illustrated in FIG. 1A, a pad oxide film 102, a first hard mask layer 104, and a second hard mask layer 106 are formed. At this time, it is preferable that the first hard mask layer 104 is a nitride film and the second hard mask layer 106 is an oxide film. Here, a hard mask layer may be further formed on the second hard mask layer 106, and the hard mask layer formed on the second hard mask layer 106 may be removed while forming pillars in a subsequent process.

Next, as shown in FIG. 1B, a photoresist pattern (not shown) defining an active region is formed, and the second hard mask layer 106, the first hard mask layer 104, and the pad oxide layer are formed using the photoresist pattern as an etch mask. 102 and the semiconductor substrate 100 are etched to form a second hard mask layer pattern 106a, a first hard mask layer pattern 104a, a pad oxide film pattern 102a, and a pillar 108.

Next, as shown in FIG. 1C, after the semiconductor substrate is oxidized to form the buffer oxide layer 110 on the pillars 108 and the semiconductor substrate 100, the capping nitride layer 114 is deposited on the entire upper portion of the semiconductor substrate. An ion implantation region 112 for forming a buried bit line is formed by implanting impurities into the substrate 100.

Next, as illustrated in FIG. 1D, first cap etching is performed on the capping nitride layer 114 to form the first spacer 115. In this process, the capping nitride layer 114 on the second hard mask layer pattern 106a, the buffer oxide layer 110 and the capping nitride layer 114 on the ion implantation region 112 are etched. Subsequently, a first sub-etch is performed on the exposed ion implantation region 112 using the first spacer 115 as a mask to form a trench in the ion implantation region 112. This becomes part of the region for forming the silicide layer in the ion implantation region 112 connected to the trench by forming a metal layer in a subsequent process.

Next, as shown in FIG. 1E, after forming the liner nitride film over the entire surface, the second spacer 116 is formed by performing full surface etching on the liner nitride film. Accordingly, the second spacer 116 remains on the sidewalls of the capping nitride layer 114 and the ion implantation region 112 etched by the primary subetch. Subsequently, secondary ion etching is performed on the exposed ion implantation region 112 using the second spacer 116 as a mask to further etch the ion implantation region 112. Here, an offset A is formed to prevent the bridge with the damascene word line formed in a subsequent process by allowing the ion implantation region 112 to be further etched by the secondary subetch.

1F, the silicide layer 120 is formed in the ion implantation region 112 in the region where the metal layer 118 and the ion implantation region 112 are in contact with each other after the metal layer 118 is formed over the entire surface. ). In this case, the metal layer 118 is preferably titanium (Ti) or cobalt (Co).

Next, as shown in FIG. 1G, the metal layer 118 and the second spacer 116 are removed. Therefore, the silicide layer 120 formed on the sidewall of the ion implantation region 112 and the ion implantation region 112 is exposed. Here, the exposed sidewall of the ion implantation region 112 is an offset to prevent the bridge with the damascene word line.

Next, as shown in FIG. 1H, a sacrificial insulating film 122 is formed over the entire surface. Subsequently, although not shown, the planarization etching process 122 is performed to planarize the sacrificial insulating layer 122, and then a photoresist film (not shown) is applied on the planarization sacrificial insulation layer 122, followed by an exposure and development process to fill the buried bitline. To form a photoresist pattern (not shown) defining.

Next, as illustrated in FIG. 1I, the ion implantation region 112, the silicide layer 120, and the semiconductor substrate 100 are etched using the aforementioned photoresist pattern (not shown) as an etch mask. The buried bit line 112a is formed by separating the injection region 112.

Next, as shown in FIG. 1J, after forming the interlayer insulating film 124 over the entire surface, the interlayer insulating film 124 is planarized to be equal to the height of the second hard mask layer pattern 104a.

Next, as shown in FIG. 1K, the interlayer insulating layer 124 is removed to define a region where the damascene word line is to be formed. In this case, the interlayer insulating layer 124 may be etched so that the buried bit line 112a is not exposed. Subsequently, the first spacer 115 is removed by the self-alignment method, and the buffer oxide film 110 is removed. In this case, the region secured by removing the capping nitride layer 114 and the buffer oxide layer 110 may be a region where the gate insulating layer and the gate conductive layer to be formed in a subsequent process are formed.

Next, as shown in FIG. 1L, after the gate insulating material is formed on the entire surface, the gate insulating layer is formed on the sidewalls of the pillar 108 including the buried bit line 112a and the pad oxide layer pattern 102a through front etching. 126 is formed.

 Next, as shown in FIG. 1M, the gate electrode 128 and the damascene word line 130 are formed as the gate conductive layer over the entire surface. At this time, the gate conductive layer is any one selected from the group consisting of a laminated structure of a titanium nitride (TiN) film, a tantalum nitride (TaN) film and a titanium nitride (TiN) film, and a stacked structure of a titanium nitride (TiN) film and a tungsten (W) film. Is preferably. Next, after the gate electrode and the damascene word line are etched back, an insulating layer 132 is deposited to insulate the gate conductive layer and the damascene word line from the upper layers.

After forming the buried bit line as described above, the gate is formed, and the interlayer insulating layer is etched to define the gate and the damascene word line region connecting the gate, and then the capping oxide layer and the buffer oxide layer formed on the sidewall are removed. By forming gate and damascene word lines, a process margin can be secured.

1A to 1M are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

Claims (15)

Forming an ion implantation region in the semiconductor substrate between the vertical pillars; Forming a first spacer on sidewalls of the vertical pillars; Etching the ion implantation region to form a trench; Forming a silicide layer in the trench; Forming a buried bit line by etching the semiconductor substrate to separate the silicide layer and the ion implantation region; And Forming a gate insulating film and a gate conductive layer on sidewalls of the vertical pillars. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, Forming a first spacer on the vertical pillar sidewall Forming a pad oxide layer and a hard mask layer on the semiconductor substrate; Forming a photoresist pattern defining an active region on the hard mask layer; Etching the hard mask layer, the pad oxide layer, and the semiconductor substrate using the photoresist pattern as an etch mask to form the vertical pillars; Oxidizing the semiconductor substrate to form a buffer oxide film on the sidewalls of the vertical pillars and the semiconductor substrate; Forming a capping insulating film on the entire surface; And And etching the entire surface of the capping insulation layer so that the ion implantation region is exposed. Claim 3 was abandoned when the setup registration fee was paid. 3. The method of claim 2, And the capping insulating film is a nitride film. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, Forming the trench Etching the ion implantation region by using the first spacer as an etch mask to form a first trench; Forming a second spacer on a sidewall of the first trench; And Forming a second trench by etching the first trench using an etching mask of the second spacer. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, Forming the second spacer Forming a second spacer insulating film on the first spacer; And And etching the entire surface of the second spacer insulating layer to expose the ion implantation region. Claim 6 was abandoned when the registration fee was paid. The method of claim 5, And the second spacer insulating film is a liner nitride film. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 5, And the second trench is formed in the ion implantation region. Claim 8 was abandoned when the registration fee was paid. The method of claim 1, Forming the silicide layer Forming a metal layer on the trench; And And heat-treating the metal layer. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 8, The metal layer is a method of forming a semiconductor device, characterized in that the titanium or cobalt. Claim 10 was abandoned upon payment of a setup registration fee. Forming the buried bit line Forming a sacrificial insulating film over the entirety of the second trench; Forming a photoresist pattern on the sacrificial insulating layer; And And etching the semiconductor substrate with the photoresist pattern as an etch mask. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 1, After forming the buried bit line, Forming an interlayer insulating film insulating the buried bit line; And And removing the interlayer insulating film and the first spacer. Claim 12 was abandoned upon payment of a registration fee. The method of claim 11, Forming the interlayer insulating film Forming an insulating film to fill the buried bit line; And And etching the insulating film so that the second trench in which the silicide layer is formed is not exposed. Claim 13 was abandoned upon payment of a registration fee. The method of claim 11, A method of forming a semiconductor device, characterized in that it is removed by a self-alignment method. Claim 14 was abandoned when the registration fee was paid. The method of claim 1, Forming the gate conductive layer Forming a surround gate; And And forming a damascene word line connecting the surround gates. Claim 15 was abandoned upon payment of a registration fee. 15. The method of claim 14, The gate conductive layer is any one selected from the group consisting of a laminated structure of a titanium nitride (TiN) film, a tantalum nitride (TaN) film, a titanium nitride (TiN) film, and a stacked structure of a titanium nitride (TiN) film and a tungsten (W) film. A method of forming a semiconductor device, characterized in that.

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