KR101060243B1 - Programmable Memory Self-Test Circuit Generator for Dual Port Memory and Its Generation Method - Google Patents

Abstract

The programmable memory self test circuit generator according to an embodiment of the present invention receives a memory setting information and an algorithm information about an algorithm for a dual port memory and configures the library information based on the memory setting information and the algorithm information. And a programmable memory self test circuit generation unit configured to generate a programmable memory self test circuit by loading the library information from the library configuration unit.

The programmable memory self test circuit according to an embodiment of the present invention stores an instruction set for an instruction for implementing the algorithm, and generates test pattern data from the stored instruction set, wherein the instruction set includes incremental information of the instruction address. Increment information on the sequence address of the algorithm, background data information on the test pattern data, read / write operation performance information performed on the dual port memory, and counter information on a counter for counting the dual port memory address. And port selection information for determining one of two ports of the dual port memory.

Description

PROGRAMMABLE MEMORY BUILT IN SELF TEST CIRCUIT GENERATOR FOR DUAL PORT MEMORY AND METHOD THEREOF}

The present invention relates to a programmable memory self test circuit generator for a dual port memory and a method of generating the same, and more particularly, to generate a programmable memory self test circuit which is automatically programmable by receiving dual port memory configuration information and algorithm information. The present invention relates to a programmable memory self test circuit and a method thereof.

The present invention is derived from the research conducted as part of the development of system integrated semiconductor technology by the Ministry of Knowledge Economy [Task Management No .: 2008-8-1773, Task Name: Development of key element IP for high performance, high reliability SoC].

Recent advances in semiconductor processing technology and the increase in integration have resulted in a significant increase in the proportion of embedded memory, which has also made it very complex and difficult to test. The chip design technique using the Design For Testability technique was introduced.

Testability design techniques are designed to improve the observability and controllability of nodes within the chip, and include scan techniques and built-in self tests (BIST).

In particular, the self test technique (BIST) does not require test equipment such as semiconductor automatic test equipment (ATE), and it is possible to perform tests at the operating speed of the chip within the chip, which takes less time to test. Have

On the other hand, in recent years, dual port memory that can process a large amount of data quickly has been widely used as a built-in memory in a system on a chip (SoC). The built-in dual-port memory reads and writes data through two ports instead of one, making it impossible to test using conventional self test techniques (BIST).

The present invention has been made to solve the above technical problem, and more particularly, to provide a programmable memory self test circuit generator for a dual port memory and a method of generating the same.

The memory self test circuit generator according to an embodiment of the present invention receives a memory configuration information for the dual port memory and algorithm information for the algorithm to configure the library information based on the memory configuration information and the algorithm information, the library configuration unit; And a programmable memory self test circuit generation unit configured to generate a programmable memory self test circuit by loading the library information from the library configuration unit, wherein the programmable memory self test circuit generates instructions for instructions for implementing the algorithm. Store a set, and generate test pattern data from the stored instruction set, wherein the instruction set comprises increment information of the instruction address, increment information of the sequence address of the algorithm, Background data information on pattern data, read / write operation performance information performed on the dual port memory, counter information on a counter for counting the dual port memory address, and one of two ports of the dual port memory. Port selection information to determine the port of the.

The programmable memory self test circuit may include an instruction storage unit for storing the instruction set, an algorithm selection signal corresponding to the algorithm for memory self test from a user, A memory self test control unit for controlling an operation, an instruction counter unit for controlling the instruction storage unit to generate the test pattern data, and an instruction decoder for reading and decoding the instruction from the instruction storage unit.

The programmable memory self test circuit may include an address generator configured to generate a memory address of the dual port memory to which the test pattern data for the memory self test is applied, a data generator configured to generate the test pattern data; The apparatus may further include a control signal generator configured to generate a memory control signal for controlling the dual port memory, and a response analyzer configured to determine whether the dual port memory has failed from the result information of the memory self test.

In example embodiments, the memory setting information may include input / output port information for the dual port memory, activation state information of the input / output port, memory size information, timing information during read / write, or memory model number information for the memory self test. Include.

In example embodiments, the library information may include background data information about the test pattern data, control signal information, or structure information about the programmable memory self test circuit.

In an embodiment, the programmable memory self test circuit is a file that can be embedded in a system on a chip (SoC) based on Verilog-HDL code.

In example embodiments, the response analyzer compares the result information corresponding to the test pattern data with the result information read from the dual port memory.

The programmable memory self test circuit generated through the memory self test circuit generator from the library information including the memory setting information for the dual port memory and the algorithm information for the algorithm according to an embodiment of the present invention may be used to execute instructions for implementing the algorithm. An instruction storage unit for storing a set of instructions for a memory, a memory self test controller for receiving an algorithm selection signal corresponding to the algorithm for memory self-test from a user, and controlling an operation of the programmable memory self test circuit, from the stored instruction set An instruction counter that controls the instruction storage to generate test pattern data, and an instruction decoder that reads and decodes the instruction from the instruction storage The instruction set may include: increase / decrease information of an instruction address, increase / decrease information of a sequence address of the algorithm, background data information of the test pattern data, read / write operation performance information performed on the dual port memory, and the double Counter information for a counter for counting port memory addresses, and port selection information for determining one of two ports of the dual port memory.

The programmable memory self test circuit may include an address generator configured to generate a memory address of the dual port memory to which the test pattern data for the memory self test is applied, a data generator configured to generate the test pattern data; The apparatus may further include a control signal generator configured to generate a memory control signal for controlling the dual port memory, and a response analyzer configured to determine whether the dual port memory has failed from the result information of the memory self test.

In the method of generating a programmable memory self test circuit according to an exemplary embodiment of the present disclosure, the method may further include receiving memory setting information and algorithm information on an algorithm for a dual port memory for memory self test, based on the memory setting information and the algorithm information. Constructing library information, and generating and outputting a programmable memory self test circuit by loading the library information, wherein the programmable memory self test circuit stores a set of instructions for instructions to implement the algorithm. And generating test pattern data from the stored instruction set, wherein the instruction set includes increment information of the instruction address, increment information of the sequence address of the algorithm, and background of the test pattern data. Determine data information, read / write operation performance information performed on the dual port memory, counter information on a counter for counting a memory address of the dual port memory, and a port of one of two ports of the dual port memory Contains port selection information.

In example embodiments, the memory setting information may include input / output port information of the dual port memory, activation state information of the input / output port, memory size information, timing information during read / write, or memory model number information for the memory self test. Include.

In example embodiments, the library information may include background data information about the test pattern data, control signal information, or structure information about the programmable memory self test circuit.

In an embodiment, the programmable memory self test circuit is a file that can be embedded in a system on a chip (SoC) based on Verilog-HDL code.

The programmable memory self test circuit according to the present invention creates a programmable memory device test circuit capable of testing dual port memory. Thus, dual port memory can be tested effectively.

In addition, the programmable memory device test circuit according to the present invention has a high failure detection rate because a variety of algorithms can be selected, and a test time can be shortened by selecting and testing a required algorithm. In addition, the programmable memory device test circuit according to the present invention proposes an address generation circuit capable of efficiently generating a multi-loop and various addresses and an optimal instruction structure for implementing an algorithm, thereby minimizing hardware overhead.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

1 is a circuit diagram illustrating a dual port memory cell according to an embodiment of the present invention.

1, two pass transistors for each port are connected to the basic four transistor memory cells. Each port has its own bit line and word line.

In the case of dual port memory, data is written to or read from two ports. Thus, with dual port memory, data can be processed quickly. However, since dual port memory uses two ports, conventional memory self test circuits cannot be applied. In addition, in the case of dual port memory, there are failures that cannot be detected by conventional single port memory test algorithms.

2 and 3 illustrate a failure model that may occur in a dual port memory according to an embodiment of the present invention. Specifically, Figure 2 shows a failure model associated with a single port that can occur in dual port memory. 3 shows a failure model associated with dual ports that can occur in dual port memory.

Referring to FIG. 2, failure models 1PFs associated with a single port that can occur in the dual port memory are classified into failures 1PF1 associated with one cell and failures 1PF2 associated with two cells. A fault associated with one cell is caused by a faulty connection or disconnection between nodes within a cell. A fault associated with two cells is a fault caused by a faulty connection or interference between nodes within two cells. In this case, there are a combined cell causing a failure and a coupled cell causing the failure.

Some types of failure models shown in FIG. 2 are as follows.

1) Stuck-at Fault (SAF)-A fault in which the value of a memory cell or signal line is always logically fixed to zero or one. There are two types of SAF faults: SA0 fault fixed to zero and SA1 fault fixed to one. .

2) Transition Fault (TF)-A fault in which the memory cell does not transition. There are two types of TFs in which a cell transitions to (1 → 0) or (0 → 1) when a write operation is performed on the cell.

3) Read Disturb Fault (RDF)-When a read operation is performed on a memory cell, the cell's data is changed and an incorrect value is returned. In particular, it is caused by the low voltage of the internal point of the cell being read when the memory cell of the SRAM is read. The cause of the RDF is due to the voltage division according to the resistance between the pass transistor and the on-transistor, so if the resistance of the on-transistor becomes too large due to a certain defect, the cell changes value when it is read.

4) Deceptive Read Disturb Fault (DRDF)-When a read operation is performed on a memory cell, the cell's data initially returns the correct value, but the cell's value changes slowly.

5) State Coupling Fault (CFst)-If a combined cell has a specific value without applying any action to the coupled cell, it is a fault that causes the coupled cell to change to a compulsory specific logic value (0 or 1).

6) Incorrect Read Coupling Fault (CFir)-A fault that returns an incorrect logic value when a read operation is applied to a combined cell when the combined cell has a specific value.

7) Deceptive Read Destructive Coupling Fault (CFdr)-If the combined cell is in a given state, when the read operation is applied to the combined cell, the data of the combined cell is changed and returns an inaccurate result.

8) Transition Coupling Fault (CFtr)-If the combined cell is in a given state, the combined cell is a fault that has a non-transitioned logical value when the transitioned write operation is performed.

Referring to FIG. 3, failure models 2PFs related to dual ports that may occur in the dual port memory are classified into failures 2PF1 associated with one cell and failures 2PF2 associated with two cells.

Some types of failure models shown in FIG. 3 are as follows.

1) wDRDF & wDRDF-When two read operations are applied to one cell at the same time, the value of that cell changes. This fault initially returns the correct value but slowly changes the value of the cell.

2) wRDF & wTF-This error occurs when read and write operations are applied to the same cell at the same time. This failure is caused by a faulty connection of the same row of cells or bit lines of different ports.

3) wCFds & wCFds-When two operations are simultaneously applied to a combined cell through two ports, the combined cell value changes.

4) wCFrd & wRDF-when the combined cell is in a specific state and two read operations are applied to the target cell at the same time, the target cell is switched. A read operation will return an incorrect value.

5) wCFds & wRDF-When a write operation is applied to a combined cell and a read operation is simultaneously applied to the combined cell, the value of the combined cell is changed and an incorrect value is returned.

6) wCFds & wIRF-When you apply a write operation to a combined cell and at the same time a read operation on a combined cell, an incorrect value is returned. It should be noted that the state of the cell to be bound does not change.

FIG. 4 illustrates some of the March-based algorithms capable of detecting the failure model described in FIG. 2.

Referring to FIG. 4, in the case of a memory self test circuit for testing an embedded memory, failure detection rates vary according to the type of test algorithm to be implemented. This is because the failure model that can be detected for each memory test algorithm is different. Using the algorithm of FIG. 4, failures associated with a single port that can occur in dual port memory can be detected. However, in the case of the algorithm of Fig. 4, the failure associated with the dual port cannot be detected. Therefore, an algorithm for detecting a failure associated with the dual port of FIG. 3 is separately required.

FIG. 5 illustrates some of the algorithms capable of detecting the failure model described in FIG. 3.

Referring to FIG. 5, the test algorithm for the dual port memory is different for each failure model.

6 illustrates a failure model that can be detected for each test algorithm.

Referring to FIG. 6, the length of the algorithm and the detectable failure model are different for each test algorithm. Therefore, if an effective algorithm is selected according to the failure model to be detected, the test time can be shortened.

Existing memory self test circuits are based on the FSM method and generate only fixed sequences and fixed patterns. In this case, the failure detection rate is limited because a test pattern is generated by selecting a test algorithm to be implemented to implement a memory self test circuit. Even if a plurality of algorithms are selected to implement the memory self test circuit, a specific desired algorithm cannot be selected and tested, and test patterns must be sequentially generated in the order implemented by the FSM. Therefore, an unnecessary test pattern is generated and a test takes a long time.

In addition, the conventional programmable memory self test circuit has a disadvantage in that hardware overhead is greater than that of the memory self test circuit because the test sequence and the pattern can be changed. In addition, conventional programmable memory self test circuits relate to single port memory and cannot be applied to dual port memory.

Therefore, in the following, a method of generating a programmable memory self test circuit and a programmable memory self test circuit for a dual port memory according to the present invention will be described in detail.

7 is a block diagram illustrating a programmable memory self test circuit generator according to an embodiment of the present invention.

Referring to FIG. 7, the programmable memory self test circuit generator 100 according to an embodiment of the present invention includes a library configuration unit 110 and a circuit generation unit 120.

The library construction unit 110 receives the memory setting information for the target memory and the algorithm information for the algorithm for the memory self test. The library construction unit 110 configures library information based on memory setting information and algorithm information.

The memory setting information may include input / output port information of the target memory, activation state information of the input / output port, memory size information, timing information during read / write, and memory model number information for the memory self test. The library information may include background data information about the test pattern data, control signal information, or structure information about the programmable memory self test circuit.

The circuit generator 120 loads the library information from the library component 110 to generate and output a programmable memory built-in self test IP (PMBIST IP) 130.

The programmable memory self test circuit 130 stores an instruction set for instructions for implementing the algorithm, and generates test pattern data from the stored instruction set. In addition, the programmable memory self test circuit 130 may be a file type that may be embedded in a system on a chip (SoC) based on Verilog-HDL code.

The programmable memory self test circuit generator according to an embodiment of the present invention may store information of an instruction set for a March-based algorithm.

In addition, the programmable memory self test circuit generator according to an embodiment of the present invention may store information of an instruction set for an algorithm capable of detecting a failure model related to the dual port memory of FIG. 5.

In addition, the programmable memory self test circuit generator according to an embodiment of the present invention is a non-March such as a checkerboard algorithm, a marching algorithm, a walking algorithm, and a galloping algorithm. It can store the information of the instruction set for the based algorithm.

From the algorithm information selected by the user, the library constructing unit 110 constructs library information based on the algorithm information. The circuit generator 120 automatically generates a programmable memory self test circuit (PMBIST IP) in which an instruction set for an instruction corresponding to the algorithm information is stored. Hereinafter, the configuration of the programmable memory self test circuit 130 will be described in detail.

8 is a block diagram illustrating a programmable memory self test circuit generated through a programmable memory self test circuit generator according to an exemplary embodiment of the present invention.

Referring to FIG. 8, the programmable memory self test circuit 130 stores an instruction set for an instruction for implementing an algorithm and generates test pattern data from the stored instruction set. do. To this end, the programmable memory self test circuit 130 includes an instruction storage unit 210, a memory self test control unit 220, an instruction counter unit 230, and an instruction decoder 240.

The instruction storage unit 210 stores the instruction set. The instruction set according to an embodiment of the present invention includes a bit structure capable of implementing a March-based algorithm and a Non_March-based algorithm. In addition, the instruction set according to an embodiment of the present invention includes a bit structure that can implement an algorithm for detecting a failure associated with a dual port and a failure associated with a single port. This will be described in more detail in FIG. 9 below.

The memory self test controller 220 receives an algorithm selection signal corresponding to an algorithm for memory self test from a user and controls the operation of the programmable memory self test circuit.

The instruction counter unit 230 controls the instruction storage unit 210 to generate test pattern data.

The instruction decoder 240 reads and decodes an instruction corresponding to the instruction set from the instruction storage unit 210.

In addition, the programmable memory self test circuit 130 according to an embodiment of the present invention includes an address generator 250 for generating a memory address of the target memory to which test pattern data for the memory self test is applied, and the memory self test. A data generator 260 for generating the test pattern data of the target memory; a control signal generator 270 for generating a memory control signal for controlling the target memory; and result information of the memory self test. It may further include a reaction analysis unit 280 for determining whether or not a failure.

The address generator 250 receives a signal generated from the memory self test controller 220 and a signal generated from the instruction decoder 240 in the test mode. The address generator 250 has a counter for generating an address so that the test data value can be written and read in the correct location. The structure of the address generator 250 will be described in more detail later with reference to FIG. 11.

The data generator 260 generates the test pattern data according to a control signal received from the memory self test controller 220. That is, the data generator 260 generates a test data pattern by receiving a signal from the instruction decoder 240 that decodes the command output from the instruction storage 210. The generated data pattern is used as an expected value during a read operation and used to determine whether there is a failure by comparing with the data read from the memory. In addition, background data generated during a write operation may be written to a memory currently being tested.

The reaction analyzer 280 may compare the value obtained from the target memory with the test pattern data generated by the data generator 260 to determine whether there is a failure.

When the memory self test controller 220 receives a start signal for the memory self test and the algorithm selection signal from the outside, the memory self test controller 220 selects a start address of the instruction set stored in the instruction storage unit 210 to generate test pattern data. do. That is, the memory self test controller 220 controls the memory itself to be performed by applying a control signal to each component of the programmable memory self test circuit 130.

In addition, the memory self test controller 220 determines an overall test start and end time, and controls the address generator 250 to generate an address so that test data can be written to and read from the correct address of the memory. That is, the memory self test controller 220 analyzes the algorithm information and the background data information and repeats the algorithm corresponding to the algorithm information step by step until the address allocated to the target memory is terminated, so that the test pattern data is stored in the target memory. It may be controlled to be applied, and the address generator 250 may be controlled so that the test pattern data may perform a read / write operation to the correct address of the target memory.

In addition, the instruction set includes increment information of the instruction address, increment information of the sequence address of the algorithm, background data information of the test pattern data, read / write operation performance information performed on the target memory, and the memory address. Counter information for the counter for counting may include. This will be described in more detail with reference to FIGS. 9 and 10 below.

9 and 10 show an instruction set according to an embodiment of the present invention. 9 is a table illustrating a set of instructions stored in a programmable memory self test circuit according to an embodiment of the present invention. FIG. 10 is a table showing a detailed description of each bit of the instruction set of FIG. 9.

9 and 10, an instruction set according to an embodiment of the present invention consists of 10 bits. The instruction set according to an embodiment of the present invention can implement all of the algorithm based on March, and can implement the algorithm based on non-linear March. In addition, the instruction set according to an embodiment of the present invention may implement a test algorithm for testing a dual port memory and a single port memory. Instruction sets also implement instructions with minimal bits, minimizing hardware overhead. The structure of the command is as follows.

Hold / Increment field: Specifies the operation status of the instruction to implement the algorithm.

Hold continues executing the current command

Increment executes the following command

Branch allows you to jump to the specified instruction

Address Up / Down field: March, non-linear March, Dual port memory test algorithm

Background True / Inv. field: Determines the inversion of the background data

▶ Port select field: Select a port among two ports A and B

Memory operation field: Determining the read / write operation command of March, non-linear March, dual port memory test algorithm

▶ Counter operation field: March, non-linear March, Dual port memory test algorithms decide whether to use A counter or B counter in address generation circuit when generating address

Counter out field: March, non-linear March, When generating the address of the dual port memory test algorithm, the address generation circuit decides whether to export the address of the A counter or the B counter.

▶ Branch control field: Set option for branch operation.

"A <-B + 1" is an option to put A counter plus 1 in B counter, and "B <-A + 1" is an option to put B counter plus 1 in A counter.

On the other hand, the reason for controlling two counters in an instruction set is to implement a non-linear March algorithm to implement another loop in the loop when generating an address.

FIG. 11 is a block diagram illustrating the address generator 250 of FIG. 8, according to an exemplary embodiment.

Referring to FIG. 11, the address generator 250 may include two counters to support multi-loops, and counting may be performed using counter output values.

In detail, the address generator 250 receives a signal from the instruction decoder 240 that decodes a signal generated from the memory self test controller 220 and an instruction from the instruction storage unit 210 in the test mode, and receives test data. It includes a counter that generates an address so that the value can be written and read in the correct location.

For example, a March-based algorithm counts a single counter to increment and decrement it sequentially from address 0 to the last address. However, non-linear March-based algorithms do not count sequentially when address counting, but generate addresses through various loops. Therefore, an address cannot be generated with one counter. Accordingly, referring to the counter of FIG. 11, each counter may increase / decrease in units of 2 and 3 without counting only one, thereby generating various address values.

12 shows an example of implementing an algorithm using the instruction set of FIG. 9 according to an embodiment of the present invention.

Referring to FIG. 12, the March C + algorithm, which is one of based algorithms, may be implemented using the instruction set of FIG. 9. Referring to FIG. 3, the March C + algorithm consists of 14 machi elements. Therefore, if the March C + algorithm is implemented with the proposed instruction set, it can be represented by 14 instructions as shown in FIG. The proposed instruction can be implemented as one 10 bits instruction for each gusset element. Also, if there is a branch in the algorithm implementation, refer to the register that stores the internal branch address. Therefore, March C + algorithm can be composed of 14bits by adding branch address (4bits) to 10bits.

FIG. 13 is a diagram illustrating pattern generation of a galloping algorithm, which is one of non-linear March-based algorithms. 14 shows an example of implementing a galloping algorithm as an instruction set.

13 and 14, the galloping algorithm may be implemented with 12 instructions. 12 and 14, the algorithm composed of instructions are stored in the instruction storage unit 210, the user selects the required algorithm to generate a test pattern to test the memory. March-based algorithms can be implemented with one instruction for each element, while non-linear March-based algorithms create a program because no elements are determined.

FIG. 15 is a table showing information on input and output pins of the programmable memory self test circuit of FIG. 8.

Referring to FIG. 15, 'Alg_select' is an externally applied input pin for selecting a built-in test algorithm to execute, and 'MTestH' is an input pin externally applied to an execution signal for starting a programmable memory self test circuit. Selecting an algorithm and giving the MTestH signal generates a pattern of the selected algorithm.

'Oe_A', 'oe_B', 'web_A', 'web_B', 'csb_A' and 'csb_B' of the control signal generator are memory control signals applied to the memory to be tested and are output pins generated by DPMBIST. The reason that oe, web, and csb are two A and B, respectively, is because dual port memory has two ports, and each has a signal to control each port. 'Oe_A' and 'oe_B' are read_enable signals, 'web_A' and 'web_B' are write_enable signals, and 'csb_A' and 'csb_B' are chip_select signals.

'Data_out_A' and 'data_out_B' of the data generation circuit are the generated data patterns to be written to the memory, and 'address_out_A' and 'address_out_B' of the address generation circuit are the output pins generated by DPMBIST as addresses of the memory. 'End_A' and 'End_B' are signals that are generated to control the internal operation generated by counting addresses as much as the size of the memory to be tested. The 'End_A' and 'End_B' signals have two counters that generate addresses in the address generator circuit, generating a signal for each counter.

'Read_data_in_A' and 'read_data_in_B' of the data comparison circuit are input pins that receive data values read from the memory. 'Send results to the output pin.

The 'hold', 'inc' and 'branch' of the command decoder are signals generated by decoding the command and are internal signals used as control signals to select the command stored in the command memory at the command counter. "Inc" means to increment the instruction in the instruction memory to the next instruction, "hold" means to hold the current instruction, and "branch" to move the instruction to the instruction in the specific instruction memory. 'Inc' means to increment the command address in the command counter, and 'hold' means to keep the current command address. If 'hold' the instruction counter is 111... 111 to 000... When updated to 000, the address generation circuit receives the 'End_A' or 'End_B' signal and increments it with the next command. And 'branch' means to jump to the instruction address stored in the branch register.

'Inst_addr' of the instruction counter is an internal signal that selects the instructions of the algorithm stored in the instruction memory. Each command structure is stored at a specific address, so "inst_addr" picks up this address and exports the command to create a pattern.

16 is a flowchart illustrating a method of generating a programmable memory self test circuit performed by a programmable memory self test circuit generator according to an exemplary embodiment of the present invention.

The method of generating a programmable memory self test circuit according to an exemplary embodiment of the present invention receives memory setting information about a target memory and algorithm information about an algorithm for a memory self test (step S110).

In addition, the method of generating a programmable memory self test circuit according to an embodiment of the present invention configures library information based on the memory setting information and the algorithm information (step S130).

In addition, the method of generating a programmable memory self test circuit according to an embodiment of the present invention loads the library information to generate and output a programmable memory self test circuit (step S150).

As described above, the programmable memory device test circuit according to the present invention can effectively test the dual port memory. The programmable memory device test circuit according to the present invention may incorporate a plurality of test algorithms. In this case, all of the plurality of algorithms may be selected and tested, or the algorithm selected by the user may be selected and tested.

The programmable memory device test circuit according to the present invention can select various algorithms and has a high failure detection rate. In addition, since the required algorithm can be selected and tested, test time can be shortened. In addition, it is very effective in dealing with unforeseen faults due to its various algorithms. In addition, we propose an optimal instruction structure for the implementation of address generation circuits and algorithms that can effectively generate multiple loops and various addresses, minimizing the hardware overhead.

The method of generating a programmable memory self test circuit according to the present invention may be implemented in the form of program instructions that can be executed by various computer means and recorded in a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. Program instructions recorded on the media may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks. Magneto-optical media, and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. The medium may be a transmission medium such as an optical or metal line, a wave guide, or the like, including a carrier wave for transmitting a signal designating a program command, a data structure, or the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software layers to perform the operations of the present invention, and vice versa.

As described above, although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited to the above-described embodiments, which can be variously modified and modified by those skilled in the art to which the present invention pertains. Modifications are possible. Accordingly, the spirit of the present invention should be understood only by the claims set forth below, and all equivalent or equivalent modifications thereof will belong to the scope of the present invention.

1 is a circuit diagram illustrating a dual port memory cell according to an embodiment of the present invention.

2 shows a failure model associated with a single port that can occur in dual port memory.

3 shows a failure model associated with dual ports that can occur in dual port memory.

FIG. 4 illustrates some of the March-based algorithms capable of detecting the failure model described in FIG. 2.

FIG. 5 illustrates some of the algorithms capable of detecting the failure model described in FIG. 3.

6 illustrates a failure model that can be detected for each test algorithm.

7 is a block diagram illustrating a programmable memory self test circuit generator according to an embodiment of the present invention.

8 is a block diagram illustrating a programmable memory self test circuit generated through a programmable memory self test circuit generator according to an exemplary embodiment of the present invention.

9 is a table illustrating a set of instructions stored in a programmable memory self test circuit according to an embodiment of the present invention.

FIG. 10 is a table showing a detailed description of each bit of the instruction set of FIG. 9.

FIG. 11 is a block diagram illustrating the address generator 250 of FIG. 8, according to an exemplary embodiment.

12 shows an example of implementing an algorithm using the instruction set of FIG. 9 according to an embodiment of the present invention.

FIG. 13 is a diagram illustrating pattern generation of a galloping algorithm, which is one of non-linear March-based algorithms.

14 shows an example of implementing a galloping algorithm as an instruction set.

FIG. 15 is a table showing information on input and output pins of the programmable memory self test circuit of FIG. 8.

16 is a flowchart illustrating a method of generating a programmable memory self test circuit performed by a programmable memory self test circuit generator according to an exemplary embodiment of the present invention.

Claims (17)

A library configuration unit configured to receive the memory setting information for the dual port memory and the algorithm information for the algorithm and configure the library information based on the memory setting information and the algorithm information; And A programmable memory self test circuit generation unit configured to generate a programmable memory self test circuit by loading the library information from the library configuration unit, The programmable memory self test circuit stores an instruction set for instructions for implementing the algorithm, and generates test pattern data from the stored instruction set, The instruction set includes port selection information for determining one of two ports of the dual port memory for performing a memory self test using a March-based or non-linear March-based algorithm. Contains port selection information that determines the two ports in dual-port memory to perform memory self tests. In the case of performing a memory self test by determining two ports of the dual port memory, when two ports of the dual port memory read simultaneously and one port performs a read operation, At the same time, the other port is a programmable memory self-test circuit generator, characterized in that all the memory can be self-test when performing a write operation. The method of claim 1, The instruction set includes increment information of the instruction address, increment information of the sequence address of the algorithm, background data information of the test pattern data, read / write operation performance information performed on the dual port memory, and the dual port memory. And a counter information for the counter for counting addresses. The method of claim 1, The programmable memory self test circuit, An instruction storage unit for storing the instruction set; A memory self test controller configured to receive an algorithm selection signal corresponding to the algorithm for memory self test from a user and to control an operation of the programmable memory self test circuit; An instruction counter unit configured to control the instruction storage unit to generate the test pattern data; And And an instruction decoder that reads and decodes the instruction from the instruction storage unit. The method of claim 3, wherein The programmable memory self test circuit, An address generator configured to generate a memory address of the dual port memory to which the test pattern data for the memory self test is to be applied; A data generator for generating the test pattern data; A control signal generator configured to generate a memory control signal for controlling the dual port memory; And And a response analyzer configured to determine whether the dual port memory has failed from the result information of the memory self test. The method of claim 1, The memory setting information is Programmable memory self test circuit generator including input / output port information for the dual-port memory, activation state information of the input / output port, memory size information, timing information at the time of reading / writing, or information on the number of memory models for the memory self-test. The method of claim 1, The library information is And a background data information for the test pattern data, control signal information, or structure information for the programmable memory self test circuit. The method of claim 1, The programmable memory self test circuit is a programmable memory self test circuit generator that is a file that can be embedded in a Verilog-HDL code-based system on chip (SoC). The method of claim 4, wherein And the reaction analyzer compares the result information corresponding to the test pattern data with the result information read from the dual port memory. In the programmable memory self test circuit generated from the memory self test circuit generator from the library information including the memory setting information for the dual port memory and the algorithm information for the algorithm, An instruction storage unit for storing an instruction set for instructions for implementing the algorithm; A memory self test controller configured to receive an algorithm selection signal corresponding to the algorithm for memory self test from a user and to control an operation of the programmable memory self test circuit; An instruction counter unit controlling the instruction storage unit to generate test pattern data from the stored instruction set; And Instruction decoder for reading and decoding the command from the instruction storage, The instruction set includes port selection information for determining one of two ports of the dual port memory for performing a memory self test using a March-based or non-linear March-based algorithm. Contains port selection information that determines the two ports in dual-port memory to perform memory self tests. In the case of performing a memory self test by determining two ports of the dual port memory, when two ports of the dual port memory read simultaneously and one port performs a read operation, At the same time, the other port is a programmable memory self test circuit, characterized in that the memory self test is possible when performing a write operation. The method of claim 9, The instruction set includes increment information of the instruction address, increment information of the sequence address of the algorithm, background data information of the test pattern data, read / write operation performance information performed on the dual port memory, and the dual port memory address. The programmable memory self test circuit further comprising counter information for a counter for counting of the number. The method of claim 9, The programmable memory self test circuit, An address generator configured to generate a memory address of the dual port memory to which the test pattern data for the memory self test is to be applied; A data generator for generating the test pattern data; A control signal generator configured to generate a memory control signal for controlling the dual port memory; And And a response analyzer configured to determine whether the dual port memory has failed from the result information of the memory self test. Receiving memory setting information for the dual port memory and algorithm information for the algorithm for the memory self test; Constructing library information based on the memory setting information and the algorithm information; And And generating and outputting a programmable memory self test circuit by loading the library information. The programmable memory self test circuit stores an instruction set for instructions for implementing the algorithm, generates test pattern data from the stored instruction set, The instruction set includes port selection information for determining one of two ports of the dual port memory for performing a memory self test using a March-based or non-linear March-based algorithm. Contains port selection information that determines the two ports in dual-port memory to perform memory self tests. In the case of performing a memory self test by determining two ports of the dual port memory, when two ports of the dual port memory read simultaneously and one port performs a read operation, At the same time, the other port is a method of generating a programmable memory self-test circuit, characterized in that all the memory self test is possible when performing a write operation. 13. The method of claim 12, The instruction set includes increment information of the instruction address, increment information of the sequence address of the algorithm, background data information of the test pattern data, read / write operation performance information performed on the dual port memory, and the dual port memory. A method of generating a programmable memory self test circuit further comprising counter information for a counter for counting memory addresses. 13. The method of claim 12, The memory setting information includes input / output port information of the dual port memory, activation state information of the input / output port, memory size information, timing information during read / write, or memory model number information for the memory self test. How to create a self test circuit. 13. The method of claim 12, And the library information includes background data information for the test pattern data, control signal information, or structure information for the programmable memory self test circuit. 13. The method of claim 12, The programmable memory self test circuit is a file that can be embedded in a system-on-chip (SoC) based Verilog-HDL code. A computer-readable recording medium having recorded thereon a program for performing the method of claim 12.

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