KR101046980B1 - Modular burn-in board system for high speed test - Google Patents

Abstract

According to the present invention, a high-temperature FPGA can be used to directly generate a test signal for a device test during a read / write cycle in an individual connection method, and detect technology information of a DIMM from a burn-in board equipped with a plurality of DIMM sockets. The present invention relates to a high speed test module burn-in board system for implementing a high speed test on a large number of DIMMs by applying a VDD level based on detected technology information. A control device for setting a control signal for testing a semiconductor device and a voltage corresponding to the semiconductor device; And an FPGA module connected to the control device and generating a test pattern for burn-in testing the semiconductor device using a voltage set through the control device in response to a control signal of the control device, and a test pattern of the FPGA module. The burn-in board is provided with a semiconductor device of the DIMM type is tested according to.

High Speed, Module, Burn-in Board, DIMM, FPGA, ALPG, TG, FC

Description

Module burn-in board system for high speed test {Module TDBI Board System for High Speed}

The present invention relates to a module burn-in board system for high speed test.

More specifically, the built-in high-temperature FPGA allows for direct generation of test signals for individual device testing during read / write cycles, internally, and detects technology information for DIMMs from burn-in boards with multiple DIMM sockets. In addition, the present invention relates to a high speed test module burn-in board system capable of implementing high speed tests on a plurality of DIMMs by applying a VDD level based on detected technology information.

The semiconductor manufacturing process is largely divided into a preprocess called FAB and a postprocess called packaging / test.

The preceding process is a process of mounting a circuit device to be manufactured through various processes (diffusion, photo, etching, ion implanting, and thin film) on a silicon oxide thin film called a wafer, and the post process is performed on a wafer manufactured through the previous process. After a specific test (probe / test) for each device, sawing and packaging (bonding, molding, trim / form) by device, the final shipment test (burn-in test and final) for the finished individual devices test) process.

Among these, the burn-in test in the post-process is a test performed to increase the productivity of the final test. The burn-in test is performed to raise the temperature to 125 ° C. at room temperature, and the temperature after the burn-in test is 60 ~. The pattern test was lowered to 75 ° C., and the test result was returned to room temperature and sorted. At this time, the burn-in time is set differently according to the use.

The semiconductor equipment for this burn-in test is divided into the first generation memory burn-in test (MBT), the second generation MBT, and the third generation MBT.The first generation MBT is a monitoring burn-in tester capable of monitoring burn-in results, and the second generation MBT. Is a tester equipment with faster processing speed and data management capability than the first generation, and the third generation is a TDBI (Test During Burn-in) that has the functions of the first and second generations and can test the characteristics of the device itself.

1 is a configuration diagram showing a burn-in test apparatus of a conventional semiconductor device.

As shown in FIG. 1, the TDBI, which is a burn-in test device, includes a clock generator 10 including an algorithm pattern generator (ALPG) or a tachometer generator (TGG) for downloading and generating a test pattern for burn-in test, and the clock generator 10. Receive a signal for testing the device 60 from the set to a voltage suitable for the device to send to each device 60 through a connection (FT) 30, to the test signal through the connection (30) The control device 20 is configured to receive the output result of the device 60 and determine pass / fail.

In this case, the device 60 is present in a burn-in board (BIB) 50 inserted into a plurality of slots.

The burn-in test apparatus of the conventional semiconductor device is manufactured for 10 MHz, and when time-induced time delay is applied during burn-in test to eliminate distortion of signal lines generated in each board, connector and cable in the burn-in test apparatus. As the test time becomes longer, there is a problem that the test performance is degraded.

In addition, as shown in FIGS. 2A and 2B, devices inserted into a plurality of slots in the burn-in board 50 are connected in parallel, so that when a test signal is applied to the arranged devices, the vertical and horizontal arrangement of the corresponding devices is performed. After designating each group, test is performed by sequentially performing write operation for storing test data and read operation for reading test data.

That is, since the semiconductor devices are connected in parallel, in the write operation, all are written at the same time at the same time as in the graph of FIG. 2A, whereas a read result of outputting a test result value from the device 60 is read. In operation, as shown in the graph of FIG. 2B, the individual selection reads result in different service information (SI) at the time of writing and reading. This causes a problem that cannot be tested at the same frequency.

On the other hand, in order to solve the problem caused by the parallel connection of the device, when the connection of the device is not connected in parallel, there is a problem that the number of devices that can be tested per burn-in board is reduced.

Therefore, while eliminating the parallel connection in the burn-in board 50 as another way to solve the problem of the parallel connection of the device, it is possible to increase the number of devices that can be tested by increasing the number of channels. However, the increase in the number of channels increases the cost of the system. In addition, a number of connectors must be used to satisfy the high-speed test according to the increase in the number of channels. As the size of the burn-in board 50 is limited, the number of connectors that can be configured in the burn-in board 50 is limited, effectively A problem arises in which the number cannot be increased.

The burn-in system having the above-described problems is a system in which a single device is mounted on a plurality of burn-in boards 50 to perform a batch test.

The present invention has been made to solve the above problems, by embedding a high-temperature FPGA to generate a test signal for the device test during the read / write cycle directly in an individual connection method and has a plurality of DIMM sockets Provides module burn-in board system for high speed test which detects technology information of DIMM from burn-in board and implements high speed test on multiple DIMMs by applying VDD level based on detected technology information. Its purpose is to.

Another object of the present invention is a high speed test module burn-in board system that implements the write and read operation of the device using the same frequency is formed integrally FPGA (ALPG, TG, FC) inside the burn-in board To provide.

Another object of the present invention is that the FPGA (ALPG, TG, FC) is integrally formed inside the burn-in board, so that the impedance of the burn-in board, the connector and the cable do not have to be considered, and the connector according to the increase of the channel It provides a modular burn-in board system for high speed test that does not require additional use and additional cost.

One embodiment of the high speed test module burn-in board system according to the present invention for achieving the above object, in the high speed test module burn-in test system, the control signal for testing a semiconductor device and the semiconductor device A control device for setting a corresponding voltage; And an FPGA module connected to the control device and generating a test pattern for burn-in testing the semiconductor device using a voltage set in response to a control signal of the control device, and a test is performed according to a test pattern of the FPGA module. The burn-in board is provided with a semiconductor device of the DIMM type.

The FPGA module includes at least one of an Algorithm Pattern Generator (ALPG), a Timing Generator (TG), and a Format Controller (FC), wherein the FPGA module detects technology information of the semiconductor device of the DIMM type and controls the control device. And the controller controls the VDD level to be applied to the FPGA module based on the technology information.

The control device is configured to download different test patterns for each of the DIMM type semiconductor devices, so that the semiconductor device of the DIMM type can be tested under different test conditions, and the same test condition for the semiconductor device of the same DIMM type. Characterized in that the test is made.

The control device is connected to the CPU for controlling the ALPG, the PPS for supplying power to each of the plurality of DIMM type semiconductor elements, and are individually connected to each of the plurality of DIMM type semiconductor elements. And a VIH for improving a high level characteristic of the test pattern data applied to the DIMM type semiconductor device.

The ALPG of the FPGA module receives a control signal input from the control device to generate an address pattern, a data pattern, a control pattern, a timing control signal, and an embedded clock generation control signal, and the TG controls timing generated by the ALPG. A timing clock signal CLK is generated in response to a signal, and the FC allocates a channel of an address pattern, a data pattern, a control pattern, and an insertion clock generation control signal generated in the ALPG, and generates a timing clock signal (generated from the TG). The test pattern data is applied to each of the DIMM type semiconductor elements in synchronization with CLK).

The FC may be individually connected to a plurality of DIMM type semiconductor devices.

The FPGA module is characterized in that capable of operating at a temperature of 125 ℃.

The FPGA module is characterized in that for outputting a high speed signal of 400MHz or more.

The FPGA module is characterized in that integrally attached to the bottom (bottom) of the burn-in board.

The FPGA module is configured in a board type, and is connected to each other through a socket included in a bottom of the burn-in board and a connector included in the FPGA module.

The high speed test module burn-in board system includes placing the FPGA module in the center of the burn-in board, placing a plurality of DIMM-type semiconductor devices on both sides of the burn-in board, and a plurality of FCs through the FC in the FPGA module. It is characterized in that configured to be connected to each of the semiconductor device of the DIMM type.

The FPGA module is configured in a structure in which a plurality of FCs are connected in parallel to each other to configure tens or hundreds of I / Os in one FPGA module.

The high speed test burn-in board system according to the present invention as described above has the following effects.

First, by embedding a high-temperature FPGA, it is possible to directly generate internal test signals for the device test during the read / write cycles through the individual connection method, and to detect the technology information of the DIMM from a burn-in board equipped with multiple DIMM sockets. By applying the VDD level based on the detected technology information, a high speed test may be implemented for a plurality of DIMMs in a batch.

Second, the FPGA (ALPG, TG, FC) is formed inside the burn-in board to write and read the device using the same frequency to prevent distortion of the signal line with cables or connectors, thus enabling high speed test. Can be implemented.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments with reference to the accompanying drawings.

A preferred embodiment of the high speed test burn-in board system according to the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiments of the present invention and do not represent all of the technical idea of the present invention, various equivalents that may be substituted for them at the time of the present application It should be understood that there may be water and variations.

3 is a block diagram showing the structure of a high speed test module burn-in board system according to an embodiment of the present invention.

As shown in FIG. 3, the module burn-in test system for high speed test uses a control signal for testing a DIMM type semiconductor device 60 (see FIG. 8) and a voltage corresponding to the DIMM type semiconductor device 60. The semiconductor device 60 is connected to the control device 20 to be set and the control device 20, using the voltage set through the control device 20 in response to a control signal of the control device 20. The FPGA module 100 generates a test pattern for burn-in test, and the burn-in board 50 in which the semiconductor device 60 of the DIMM type is tested according to the test pattern of the FPGA module 100 is mounted.

The FPGA module 100 includes at least one of an Algorithm Pattern Generator (ALPG) 110, a Timing Generator (TG) 120, and a Format Controller (FC) 130, and the FPGA module 100 is a semiconductor of the DIMM type. Technology information of the device 50 is detected and output to the control device 20, and the control device 20 controls the VDD level to be applied to the FPGA module 100 based on the technology information.

The control device 20 allows different test patterns to be downloaded for each of the DIMM type semiconductor devices 60, so that the semiconductor device 60 of the DIMM type can be tested under different test conditions, and the same DIMM type. The semiconductor device 60 is tested under the same test conditions.

In this case, the control device 20 is a CPU 22 for controlling the ALPG 110, and a PPS 21 for supplying power to each of the plurality of DIMM type semiconductor elements 60 are formed to be individually connected, A VIH 23 that is individually connected to a plurality of DIMM type semiconductor elements 60 to improve high level characteristics of pattern data applied to each of the DIMM type semiconductor elements 60, and the CPU 21 and Connected between the VIH (23), it is composed of a CLPD (Complex Programmable Logic Device, 24) for outputting the control signal of the CPU 21 to the VIH (23).

The FPGA module 100 receives the control signal input from the control device 20 and generates an address pattern, a data pattern, a control pattern, a timing control signal, and an insertion clock generation control signal, and the ALPG 110. The TG 120 generating the timing clock signal CLK in response to the timing control signal generated at 110, and the address pattern, data pattern, control pattern, and insertion clock generation control signal generated by the ALPG 110. Allocating a channel and synchronizing with the timing clock signal CLK generated from the TG 120 to the FC 130 to apply pattern data for testing the semiconductor device of the DIMM type to the semiconductor device 60 of each DIMM type. It is composed. In this case, the FC 130 is configured to be individually connected to each of the plurality of DIMM type semiconductor device 60.

On the other hand, since the burn-in board 50 to test the device to raise the temperature to 125 ℃ at room temperature during the test, the FPGA module 100 located in the burn-in board 50 can be used at a high temperature of 125 ℃ High temperature chips should be used. FPGAs currently used in the market are classified into general use, industrial use, and military use. In general, general operation is possible at a temperature of 85 ° C, industrial use is possible at a temperature of 100 ° C, and military use 125 It has the ability to operate even at a temperature of ℃. Therefore, the FPGA module 100 formed in the burn-in board 50 preferably uses a military FPGA that can be used at a high temperature to enable operation at 125 ° C. For reference, it should be noted that the military FPGA used as the high-temperature chip is for the purpose of describing embodiments for the specific technology herein and is not intended to be limiting. Therefore, those of ordinary skill in the art will appreciate that various embodiments are possible within the scope of the technical idea of the present invention.

By placing the FPGA module 100 integrally on the burn-in board 50 as described above, the distortion of the connector can be eliminated, and time delay and time skew caused by the cable or the connector can be prevented. Speed signal output is enabled.

On the other hand, the FPGA module 100 is preferably integrally attached to the bottom (bottom) of the burn-in board (50). Since the DIMM type semiconductor device socket is located on the top of the burn-in board, the FPGA module 100 is located on the bottom surface of the burn-in board 50 to prevent mutual interference with the socket for the semiconductor device of the DIMM type. By simplifying the structure, the size of the equipment can be reduced.

Alternatively, the FPGA module 100 is configured as a board type including a connector 140, as shown in Figure 8, the socket formed on the bottom (bottom) of the burn-in board 50 and the connector 140 to each other It may be configured to be fastened.

FIG. 4 is a configuration diagram illustrating the structure of the FC of FIG. 3 in more detail. As shown in FIG. 4, each FC 130 individually selects a plurality of DIMM types of semiconductor devices 60. The timing clock signal CLK generated at 120 is synchronized. Then, the pattern data output from the ALPG 110 is applied to the semiconductor device 60 of the DIMM type connected in parallel to each other to separately test the semiconductor devices 60 of the DIMM type.

5 and 6 are diagrams illustrating the structure of the FPGA module of the high speed test module burn-in board system according to the present invention. As shown in FIGS. 5 and 6, the FPGA module 100 includes a plurality of FCs 130. It is structured in parallel with each other, allowing hundreds of I / Os to be used in one FPGA module. It can be connected to several DIMM-type semiconductor devices per FPGA module to improve service information (SI). In FIG. 5, reference numeral 25 denotes a digital-to-analog converter (DAC), which converts a digital signal input from the CPLD 24 into an analog signal and outputs the analog signal to the PPS 22 and VIH 23. Power supply) to the semiconductor device 60 of the DIMM type, reference numeral 27 denotes BOOST, reference numeral 28 denotes an I / F, an interface unit, reference numeral 29 denotes an ADC, which is input from the FPGA module 100. The analog signal is converted into a digital signal and output to the CPLD 24.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a configuration diagram showing a burn-in test apparatus of a conventional semiconductor chip

2A and 2B are diagrams for explaining a structure in which chips inserted into a plurality of slots in a conventional burn-in board are connected in parallel, and a delay time generated during a write / read cycle in such a structure.

Figure 3 is a block diagram showing the structure of a high speed test module burn-in board system according to an embodiment of the present invention

Figure 4 is a configuration diagram for explaining in more detail the structure of the FC FC burn-in board system for a high speed test according to the present invention

5 and 6 is a configuration diagram showing the structure of the FPGA module of the high speed test module burn-in board system according to the present invention

7 is a diagram showing the configuration of a semiconductor device of the DIMM type applied to the present invention;

8 is a configuration diagram for explaining the structure of the FPGA module of the high speed test module burn-in board system according to the present invention in more detail

DESCRIPTION OF THE REFERENCE NUMERALS

10: clock generator 20: control device

21: PPS 22: CPU

23: VIH 30: connection

40: chamber 50: burn-in board

60: DIMM type semiconductor device 100: FPGA module

110: ALPG 120: TG

130: FC 140: Connector

Claims (12)

delete delete delete A control device for setting a control signal for testing a semiconductor device and a voltage corresponding to the semiconductor device; And an FPGA module connected to the control device and generating a test pattern for burn-in testing the semiconductor device using a voltage set through the control device in response to a control signal of the control device, and a test pattern of the FPGA module. The burn-in board is provided with a semiconductor device of the DIMM type is tested according to; The control device may be configured to download different test patterns for each of the DIMM type semiconductor devices, so that the DIMM type semiconductor devices may be tested under different test conditions, and for the same DIMM type semiconductor devices. In the high speed test module burn-in board system where the test is performed under the same test conditions, The control device includes a CPU for controlling the ALPG, a PPS configured to be connected to a plurality of DIMM types of semiconductor elements, and supplying power, and a plurality of DIMM types of semiconductor elements, each individually connected to each DIMM type. And a VIH for improving a high level characteristic of test pattern data applied to a semiconductor device. A control device for setting a control signal for testing a semiconductor device and a voltage corresponding to the semiconductor device; And an FPGA module connected to the control device and generating a test pattern for burn-in testing the semiconductor device using a voltage set through the control device in response to a control signal of the control device, and a test pattern of the FPGA module. The burn-in board is provided with a semiconductor device of the DIMM type is tested according to; The FPGA module may include at least one of an Algorithm Pattern Generator (ALPG), a Timing Generator (TG), and a Format Controller (FC), and the FPGA module may detect technology information of the semiconductor device of the DIMM type. In the high speed test module burn-in board system for outputting to the control device, the control device is controlled to apply the VDD level to the FPGA module based on the technology information, The ALPG of the FPGA module receives a control signal input from the control device to generate an address pattern, a data pattern, a control pattern, a timing control signal, and an embedded clock generation control signal, and the TG controls timing generated by the ALPG. A timing clock signal CLK is generated in response to a signal, and the FC allocates a channel of an address pattern, a data pattern, a control pattern, and an insertion clock generation control signal generated in the ALPG, and generates a timing clock signal (generated from the TG). And a test pattern data applied to each of the DIMM type semiconductor elements in synchronization with CLK. The method of claim 5, The FC is a burn-in board system for a high speed test, characterized in that connected to each of a plurality of DIMM type semiconductor devices individually. delete delete delete A control device for setting a control signal for testing a semiconductor device and a voltage corresponding to the semiconductor device; And an FPGA module connected to the control device and generating a test pattern for burn-in testing the semiconductor device using a voltage set through the control device in response to a control signal of the control device, and a test pattern of the FPGA module. The burn-in board is provided with a semiconductor device of the DIMM type is tested according to; In the high speed test module burn-in board system, The FPGA module is configured as a board type, high speed test module burn-in board system, characterized in that fastening to each other through a socket included in the bottom (bottom) of the burn-in board and a connector included in the FPGA module. A control device for setting a control signal for testing a semiconductor device and a voltage corresponding to the semiconductor device; And an FPGA module connected to the control device and generating a test pattern for burn-in testing the semiconductor device using a voltage set through the control device in response to a control signal of the control device, and a test pattern of the FPGA module. The burn-in board is provided with a semiconductor device of the DIMM type is tested according to; The FPGA module may include at least one of an Algorithm Pattern Generator (ALPG), a Timing Generator (TG), and a Format Controller (FC), and the FPGA module may detect technology information of the semiconductor device of the DIMM type. In the high speed test module burn-in board system for outputting to the control device, the control device is controlled to apply the VDD level to the FPGA module based on the technology information, The high speed test module burn-in board system includes placing the FPGA module at the center of the burn-in board, placing a plurality of DIMM-type semiconductor elements on both sides of the burn-in board, and a plurality of FCs through the FC in the FPGA module. Module burn-in board system for high speed test, characterized in that configured to be connected to each of the semiconductor device of the DIMM type. A control device for setting a control signal for testing a semiconductor device and a voltage corresponding to the semiconductor device; And an FPGA module connected to the control device and generating a test pattern for burn-in testing the semiconductor device using a voltage set through the control device in response to a control signal of the control device, and a test pattern of the FPGA module. The burn-in board is provided with a semiconductor device of the DIMM type is tested according to; The FPGA module may include at least one of an Algorithm Pattern Generator (ALPG), a Timing Generator (TG), and a Format Controller (FC), and the FPGA module may detect technology information of the semiconductor device of the DIMM type. In the high speed test module burn-in board system for outputting to the control device, the control device is controlled to apply the VDD level to the FPGA module based on the technology information, The FPGA module has a structure in which a plurality of FCs are connected in parallel to each other to configure tens or hundreds of I / Os in one FPGA module.

Images