KR101046379B1 - Semiconductor package and manufacturing method thereof - Google Patents

Semiconductor package and manufacturing method thereof Download PDF

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KR101046379B1
KR101046379B1 KR1020080013694A KR20080013694A KR101046379B1 KR 101046379 B1 KR101046379 B1 KR 101046379B1 KR 1020080013694 A KR1020080013694 A KR 1020080013694A KR 20080013694 A KR20080013694 A KR 20080013694A KR 101046379 B1 KR101046379 B1 KR 101046379B1
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semiconductor chip
connection terminal
abandoned
semiconductor package
substrate
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Korean (ko)
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KR20090088265A (en
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유종우
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주식회사 하이닉스반도체
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/45001—Core members of the connector
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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Abstract

반도체 패키지는, 다수의 접속 패드를 구비된 기판; 상기 접속 패드 상에 형성된 연결단자; 상기 기판 상에 배치되고 상면에 다수의 본딩 패드가 구비된 반도체 칩; 상기 기판 상에 상기 반도체 칩과 상기 연결단자의 측면을 감싸도록 형성된 절연막; 상기 반도체 칩의 본딩 패드와 상기 연결단자 간을 연결하는 금속와이어; 및 상기 연결단자, 반도체 칩, 절연막 및 금속와이어를 덮도록 형성된 캡핑막을 포함한다.The semiconductor package includes a substrate having a plurality of connection pads; A connection terminal formed on the connection pad; A semiconductor chip disposed on the substrate and having a plurality of bonding pads disposed on an upper surface thereof; An insulating layer formed on the substrate to surround side surfaces of the semiconductor chip and the connection terminal; A metal wire connecting the bonding pad of the semiconductor chip and the connection terminal; And a capping film formed to cover the connection terminal, the semiconductor chip, the insulating film, and the metal wire.

Description

반도체 패키지 및 그의 제조 방법{Semiconductor package and method for fabricating of the same}Semiconductor package and method for fabrication thereof

본 발명은 반도체 패키지 및 그의 제조 방법에 관한 것으로서, 보다 상세하게는, 와이어 스위핑 현상을 방지하고 전체 두께를 줄일 수 있는 반도체 패키지 및 그의 제조 방법에 관한 것이다.The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package and a method for manufacturing the same that can prevent the wire sweeping phenomenon and reduce the overall thickness.

오늘날 전자 산업의 추세는 경량화, 소형화, 고속화, 다기능화, 고성능화되고 높은 신뢰성을 갖는 제품을 저렴하게 제조하는 것이다. 이와 같은 제품 설계의 목표 달성을 가능하게 하는 중요한 기술 중의 하나가 바로 반도체 패키지 조립 기술이다.The trend in today's electronics industry is to make products that are lighter, smaller, faster, more versatile, more powerful and more reliable. One of the key technologies that enables this product design goal is semiconductor package assembly technology.

상기 반도체 패키지 조립 기술은 웨이퍼 조립 공정을 거쳐 집적회로가 형성된 반도체 칩을 외부 환경으로부터 보호하고, 기판 상에 용이하게 실장되도록 하여 반도체 칩의 동작 신뢰성 확보하기 위한 기술이다.The semiconductor package assembly technology is a technology for securing operational reliability of a semiconductor chip by protecting the semiconductor chip on which an integrated circuit is formed through an wafer assembly process from an external environment and being easily mounted on a substrate.

일반적인 반도체 패키지 공정은 칩 부착, 와이어 본딩, 몰딩, 트림/포밍 등의 공정들을 포함하여 이루어지며, 반도체 패키지 공정은 웨이퍼를 절단하여 개개의 반도체 칩들로 분리시킨 다음 개개의 반도체 칩 별로 패키징 공정을 실시하는 방식 또는 웨이퍼에 일체로 패키징 공정을 수행한 후 개개의 반도체 칩으로 분리하는 방법으로 수행한다.The general semiconductor package process includes processes such as chip attaching, wire bonding, molding, trimming and forming, and the semiconductor package process cuts the wafer into separate semiconductor chips, and then packages the individual semiconductor chips. It is carried out by a packaging process or integrally to the wafer and then separated into individual semiconductor chips.

한편, 일반적인 반도체 패키지는 반도체 칩과 기판 또는 리드프레임과 같은 외부회로를 금속와이어를 이용하여 전기적으로 연결한다. Meanwhile, a general semiconductor package electrically connects a semiconductor chip and an external circuit such as a substrate or a lead frame using metal wires.

그러나, 상기 금속와이어를 이용한 반도체 패키지는 상기 금속와이어가 루프(Loop)의 형태를 갖도록 형성되기 때문에 반도체 패키지의 전체 두께가 증가하게 된다. However, in the semiconductor package using the metal wire, since the metal wire is formed to have a loop shape, the overall thickness of the semiconductor package is increased.

또한, 상기 금속와이어를 이용한 반도체 패키지는 패키지가 미세화 및 고집적화됨에 따라 금속와이어 간의 간격이 줄어들고, 반도체 패키지에 센터 패드 형의 반도체 칩을 사용하거나 반도체 패키지가 스택된 경우 금속 와이어의 길이가 길어져 와이어 스위핑(Sweeping) 현상이 발생한다.In addition, in the semiconductor package using the metal wire, the spacing between the metal wires decreases as the package becomes finer and more highly integrated, and when the center pad type semiconductor chip is used for the semiconductor package or when the semiconductor package is stacked, the length of the metal wire is increased so that the wire sweeping is performed. (Sweeping) phenomenon occurs.

본 발명은 와이어 스위핑 현상을 방지하고 전체 두께를 줄일 수 있는 반도체 패키지 및 그의 제조 방법을 제공한다.The present invention provides a semiconductor package and a method of manufacturing the same that can prevent the wire sweeping phenomenon and reduce the overall thickness.

본 발명에 따른 반도체 패키지는, 다수의 접속 패드를 구비된 기판; 상기 접속 패드 상에 형성된 연결단자; 상기 기판 상에 배치되고 상면에 다수의 본딩 패드가 구비된 반도체 칩; 상기 기판 상에 상기 반도체 칩과 상기 연결단자의 측면을 감싸도록 형성된 절연막; 상기 반도체 칩의 본딩 패드와 상기 연결단자 간을 연결 하는 금속와이어; 및 상기 연결단자, 반도체 칩, 절연막 및 금속와이어를 덮도록 형성된 캡핑막을 포함한다.A semiconductor package according to the present invention includes a substrate having a plurality of connection pads; A connection terminal formed on the connection pad; A semiconductor chip disposed on the substrate and having a plurality of bonding pads disposed on an upper surface thereof; An insulating layer formed on the substrate to surround side surfaces of the semiconductor chip and the connection terminal; A metal wire connecting the bonding pad of the semiconductor chip and the connection terminal; And a capping film formed to cover the connection terminal, the semiconductor chip, the insulating film, and the metal wire.

상기 금속와이어는 상기 반도체 칩에 대하여 수평방향으로 직선의 형태를 갖는다.The metal wire has a straight line shape in a horizontal direction with respect to the semiconductor chip.

상기 연결단자는 상면이 상기 반도체 칩의 상면과 동일한 높이를 갖는다.The connection terminal has an upper surface the same height as the upper surface of the semiconductor chip.

상기 연결단자는 구리(Cu), 니켈(Ni) 및 금(Au) 중 어느 하나로 이루어지거나 이들을 포함하는 합금으로 이루어진다.The connection terminal is made of any one of copper (Cu), nickel (Ni) and gold (Au) or made of an alloy containing them.

상기 절연막은 상면에 상기 연결단자 및 상기 반도체 칩의 상면과 동일하거나 낮은 높이를 갖는다.The insulating layer has a height equal to or lower than an upper surface of the connection terminal and the semiconductor chip on an upper surface thereof.

상기 절연막은 솔더 레지스트로 이루어진다.The insulating film is made of a solder resist.

상기 기판의 하면에 부착된 외부접속단자를 더 포함한다.It further includes an external connection terminal attached to the lower surface of the substrate.

또한, 본 발명에 따른 반도체 패키지의 제조 방법은, 다수의 접속 패드를 구비하고, 반도체 칩 부착 영역을 갖는 기판의 상기 접속 패드 상에 다수의 연결단자를 형성하는 단계; 상기 기판 상에 상기 반도체 칩 부착 영역을 노출시키도록 함과 아울러 상기 연결단자의 측면을 감싸도록 절연막을 형성하는 단계; 상기 기판의 반도체 칩 부착 영역에 상면에 다수의 본딩 패드를 갖는 반도체 칩을 부착하는 단계; 상기 반도체 칩의 본딩 패드와 상기 연결단자 간에 금속와이어를 형성하는 단계; 및 상기 반도체 칩, 연결단자, 절연막 및 금속와이어를 덮도록 캡핑막을 형성하는 단계를 포함한다.In addition, the method of manufacturing a semiconductor package according to the present invention comprises the steps of: forming a plurality of connection terminals on the connection pad of the substrate having a plurality of connection pads and having a semiconductor chip attachment region; Forming an insulating layer on the substrate to expose the semiconductor chip attachment region and to surround the side surface of the connection terminal; Attaching a semiconductor chip having a plurality of bonding pads on an upper surface of the semiconductor chip attaching region of the substrate; Forming a metal wire between a bonding pad of the semiconductor chip and the connection terminal; And forming a capping layer to cover the semiconductor chip, the connection terminal, the insulating layer, and the metal wire.

상기 연결단자를 형성하는 단계는, 상기 기판 상에 금속씨드막을 형성하는 단계; 상기 금속씨드막 상에 상기 접속 패드 상부 부분을 노출시키는 마스크패턴을 형성하는 단계; 상기 연결단자를 형성하는 단계; 상기 마스크패턴을 제거하는 단계; 및 상기 연결단자 하부에만 상기 금속씨드막이 잔류하도록 상기 기판 상의 금속씨드막을 제거하는 단계를 포함한다.The forming of the connection terminal may include forming a metal seed film on the substrate; Forming a mask pattern exposing an upper portion of the connection pad on the metal seed layer; Forming the connection terminal; Removing the mask pattern; And removing the metal seed film on the substrate such that the metal seed film remains only under the connection terminal.

상기 연결단자는 도금 공정으로 형성한다.The connection terminal is formed by a plating process.

상기 연결단자는 구리(Cu), 니켈(Ni) 및 금(Au) 중 어느 하나로 형성하거나 이들을 포함하는 합금으로 형성한다.The connection terminal may be formed of any one of copper (Cu), nickel (Ni), and gold (Au), or an alloy including the same.

상기 금속와이어는 상기 반도체 칩에 대하여 수평방향으로 직선의 형태를 갖도록 형성한다.The metal wire is formed to have a straight line shape in a horizontal direction with respect to the semiconductor chip.

상기 연결단자는 상면이 상기 반도체 칩의 상면과 동일한 높이를 갖도록 형성한다.The connection terminal may be formed such that an upper surface thereof has the same height as an upper surface of the semiconductor chip.

상기 절연막은 상면이 상기 연결단자 및 상기 반도체 칩의 상면과 동일하거나 낮은 높이를 갖도록 형성한다.The insulating layer is formed such that an upper surface thereof has a height equal to or lower than an upper surface of the connection terminal and the semiconductor chip.

상기 절연막은 스크린 프린팅 방법으로 형성한다.The insulating film is formed by a screen printing method.

상기 절연막은 솔더 레지스트로 형성한다.The insulating film is formed of a solder resist.

상기 캡핑막을 형성하는 단계 후, 상기 기판의 하면에 외부접속단자를 부착하는 단계를 더 포함한다.After forming the capping layer, the method further includes attaching an external connection terminal to a lower surface of the substrate.

본 발명은 반도체 패키지의 전기적인 연결을 위한 금속와이어를 루프가 없도록 직선의 형태로 형성함으로써 반도체 패키지의 전체 두께를 줄일 수 있고, 와이 어의 스위핑 현상과 같은 불량을 원천적으로 방지할 수 있다.The present invention can reduce the overall thickness of the semiconductor package by forming a metal wire for the electrical connection of the semiconductor package in a straight line so that there is no loop, it is possible to prevent defects such as the sweeping phenomenon of the wire.

본 발명은 전체 반도체 패키지의 두께를 줄이고, 반도체 패키지의 형성 공정에서 발생하는 와이어의 스위핑 현상을 방지하기 위하여 전기적인 연결을 위한 금속와이어를 직선의 형태로 형성한다.The present invention forms a metal wire for the electrical connection in the form of a straight line in order to reduce the thickness of the entire semiconductor package, and to prevent the sweeping phenomenon of the wire generated in the semiconductor package forming process.

자세하게, 본 발명은 기판 상에 배치되는 반도체 칩의 상면과 동일한 높이를 갖도록 기판 상에 연결단자를 형성하고, 상기 반도체 칩과 상기 연결단자 간에 전기적인 연결을 위한 금속와이어를 루프가 없도록 직선의 형태로 형성한다. In detail, the present invention forms a connection terminal on the substrate to have the same height as the upper surface of the semiconductor chip disposed on the substrate, and a straight form so that there is no loop of metal wire for electrical connection between the semiconductor chip and the connection terminal To form.

따라서, 금속와이어를 루프가 없이 직선의 형태로 형성함으로써 종래에 비하여 반도체 패키지의 전체 두께를 줄일 수 있으며, 금속와이어가 직선의 형태를 가지고 몰딩부 형성 공정을 수행하지 않음으로써 와이어의 스위핑 현상과 같은 불량을 원천적으로 방지할 수 있다.Therefore, the overall thickness of the semiconductor package can be reduced by forming a metal wire in a straight line without a loop, and the metal wire has a straight shape and does not perform a molding part forming process. Defects can be prevented at the source.

이하에서는 본 발명의 실시예에 따른 반도체 패키지 및 그의 제조 방법을 상세히 설명하도록 한다.Hereinafter, a semiconductor package and a manufacturing method thereof according to an embodiment of the present invention will be described in detail.

도 1은 본 발명의 실시예에 따른 반도체 패키지를 도시한 도면이다.1 is a diagram illustrating a semiconductor package according to an embodiment of the present invention.

도시된 바와 같이, 본 발명에 따른 반도체 패키지는 금속와이어(120)의 루프(Loop) 높이를 낮추어 반도체 패키지의 두께를 줄이기 위해 상기 금속와이어(120)가 직선의 형태를 갖는다.As shown, in the semiconductor package according to the present invention, the metal wire 120 has a straight shape in order to reduce the thickness of the semiconductor package by lowering the loop height of the metal wire 120.

자세하게, 상면에 보호막(104)에 의해 구획된 다수의 접속 패드(102)를 갖는 기판(100)의 접속 패드(102) 상에 금속씨드막(106)을 포함하는 연결단자(110)가 형 성된다. 상기 연결단자(110)는 구리(Cu), 니켈(Ni) 및 금(Au) 중 어느 하나로 이루어지거나 이들을 포함하는 합금으로 이루어진다. In detail, the connection terminal 110 including the metal seed film 106 is formed on the connection pad 102 of the substrate 100 having the plurality of connection pads 102 partitioned by the protective film 104 on the upper surface thereof. do. The connection terminal 110 is made of one of copper (Cu), nickel (Ni), and gold (Au) or made of an alloy including them.

상기 기판(100) 상에는 상면이 상기 연결단자(110)의 상면과 동일한 높이를 갖도록 상면에 다수의 본딩 패드(118)가 구비된 반도체 칩(116)이 페이스 업(Face up) 타입으로 배치되며, 상기 기판(100) 상에는 상기 반도체 칩(116)과 상기 연결단자(110)의 측면을 감싸도록 절연막(114)이 형성된다. On the substrate 100, a semiconductor chip 116 having a plurality of bonding pads 118 is disposed in a face up type such that an upper surface thereof has the same height as the upper surface of the connection terminal 110. An insulating layer 114 is formed on the substrate 100 to surround side surfaces of the semiconductor chip 116 and the connection terminal 110.

상기 절연막(114)은 솔더 레지스트(Solder resist)로 이루어지며, 상기 절연막(114)은 상면이 상기 연결단자(110) 및 상기 반도체 칩(116)의 상면과 동일하거나 낮은 높이를 갖는다. The insulating layer 114 is formed of a solder resist, and the upper surface of the insulating layer 114 has the same or lower height than the upper surface of the connection terminal 110 and the semiconductor chip 116.

즉, 상기 연결단자(110), 절연막(114) 및 반도체 칩(116)은 상면이, 바람직하게, 동일한 높이를 갖도록 형성되며, 이는, 직선의 형태를 루프 없이 금속와이어(120)를 형성하기 위함이다. That is, the connection terminal 110, the insulating film 114 and the semiconductor chip 116 is formed so that the upper surface, preferably, have the same height, which is to form a metal wire 120 without a loop in the form of a straight line to be.

상기 반도체 칩(116)의 각 본딩 패드(118)와 대응하는 상기 연결단자(110) 간에는 상기 반도체 칩(116)에 대하여 수평 방향으로 직선의 형태를 갖는 금속와이어(120)가 구비된다. A metal wire 120 having a straight line shape in a horizontal direction with respect to the semiconductor chip 116 is provided between the bonding pads 118 of the semiconductor chip 116 and the connection terminal 110 corresponding to each other.

상기 연결단자(110), 절연막(114), 반도체 칩(116) 및 금속와이어를 상면에는 전기적인 절연 및 보호를 위하여 캡핑막(122)이 형성되며, 상기 기판(100)의 하면에는 솔더볼과 같은 외부접속단자(124)가 부착된다. A capping layer 122 is formed on the connection terminal 110, the insulating layer 114, the semiconductor chip 116, and the metal wire to electrically insulate and protect the upper surface of the connection terminal 110. An external connection terminal 124 is attached.

아울러, 상기 연결단자(110) 및 반도체 칩(116)의 상면은 공정상의 이유로 일부 다른 높이로 형성될 수 있으나, 상기 일부 높이가 다르더라도 이로 인해 발생 하는 금속와이어(120)의 루프 높이를 최소화할 수 있어 반도체 패키지의 높이를 낮출 수 있다.In addition, although the upper surface of the connection terminal 110 and the semiconductor chip 116 may be formed at a different height for process reasons, the height of the loops of the metal wires 120 generated due to this may be minimized even if the height is different. This can lower the height of the semiconductor package.

한편, 본 발명에 따른 반도체 패키지는 도 2a 내지 도 2g에 도시된 바와 같은 방법으로 형성한다.Meanwhile, the semiconductor package according to the present invention is formed by the method shown in FIGS. 2A to 2G.

도 2a를 참조하면, 상면에 보호막(104)에 의해 구획된 다수의 접속 패드(102)를 구비하고, 반도체 칩 부착 영역을 갖는 기판(100) 상에 도금 공정을 위한 금속씨드막(106)을 형성한다. Referring to FIG. 2A, a metal seed film 106 for a plating process is formed on a substrate 100 having a plurality of connection pads 102 partitioned by a protective film 104 on an upper surface thereof, and having a semiconductor chip attachment region. Form.

그런 다음, 상기 금속씨드막(106) 상에 상기 접속 패드(102)의 상부 부분을 노출시키는 마스크패턴(108)을 형성한다.Next, a mask pattern 108 is formed on the metal seed layer 106 to expose an upper portion of the connection pad 102.

도 2b를 참조하면, 상기 금속씨드막(106)이 노출된 기판에 전해 도금 공정을 수행하여 구리(Cu), 니켈(Ni) 및 금(Au) 중 어느 하나로 이루어지거나 또는 이들을 포함하는 합금으로 이루어진 연결단자(110)를 형성한다. Referring to FIG. 2B, an electroplating process is performed on a substrate on which the metal seed film 106 is exposed, and is made of one of copper (Cu), nickel (Ni), and gold (Au), or an alloy including the same. The connection terminal 110 is formed.

상기 연결단자(110)는 상부 표면이 후속 공정에서 부착되는 반도체 칩의 상면과 동일한 높이를 갖도록 반도체 칩의 높이를 고려하여 형성한다.The connection terminal 110 is formed in consideration of the height of the semiconductor chip so that the upper surface has the same height as the upper surface of the semiconductor chip to be attached in a subsequent process.

도 2c를 참조하면, 상기 마스크패턴을 제거한 후, 상기 연결단자(110)와 상기 접속 패드(102) 사이에만 금속씨드막(106)이 잔류하도록, 즉, 상기 접속 패드(102) 간의 전기적인 연결이 끊어지도록 상기 금속씨드막(106)을 제거한다. Referring to FIG. 2C, after removing the mask pattern, the metal seed layer 106 remains only between the connection terminal 110 and the connection pad 102, that is, the electrical connection between the connection pads 102. The metal seed film 106 is removed so that it is cut off.

도 2d를 참조하면, 상기 기판(100)의 상부에 스크린 프린팅 방법으로 상기 반도체 칩 부착 영역을 노출시킴과 아울러 상기 연결단자(110)의 측면을 감싸도록 절연막(114)을 형성한다. Referring to FIG. 2D, an insulating layer 114 is formed on the substrate 100 to expose the semiconductor chip attaching region by a screen printing method and to cover the side surface of the connection terminal 110.

즉, 상기 기판(100) 상에 상기 반도체 칩 부착 영역 및 연결단자(110)를 가리는 스텐실 마스크(112)를 배치시킨 후, 상기 노출된 부분에 스퀴지(Squeegee : 미도시)를 이용하여 솔더 레지스트로 이루어진 절연막(114)을 형성한다. That is, after placing the stencil mask 112 covering the semiconductor chip attachment region and the connection terminal 110 on the substrate 100, a squeegee (not shown) on the exposed portion is used as a solder resist. An insulating film 114 is formed.

상기 절연막(114)은 상기 연결단자(110)과 동일한 높이를 갖도록 형성되거나 또는 상기 연결단자(110)보다 낮은 높이를 갖도록 형성한다. The insulating layer 114 is formed to have the same height as the connection terminal 110 or to have a height lower than that of the connection terminal 110.

도 2e를 참조하면, 상기 스텐실 마스크를 제거한 후, 상기 기판(100)의 반도체 칩 부착 영역에 상면에 다수의 본딩 패드(118)를 구비한 반도체 칩(116)을 페이스 업 타입으로 부착한다. Referring to FIG. 2E, after removing the stencil mask, a semiconductor chip 116 having a plurality of bonding pads 118 is attached to the semiconductor chip attaching region of the substrate 100 as a face up type.

이때, 상기 반도체 칩(116)의 상면은 상기 연결단자(110)의 형성 공정에 의해 상기 연결단자(110)와 동일한 높이를 갖는다. In this case, the upper surface of the semiconductor chip 116 has the same height as the connection terminal 110 by the forming process of the connection terminal 110.

도 2f를 참조하면, 상기 반도체 칩(116)의 각 본딩 패드(118)와 상기 각 본딩 패드(118)와 대응하는 상기 연결단자(110) 사이에 직선의 형태를 갖는 금속와이어(120)를 형성한다.Referring to FIG. 2F, a metal wire 120 having a straight line is formed between each bonding pad 118 of the semiconductor chip 116 and the connection terminal 110 corresponding to each bonding pad 118. do.

상기 금속와이어(120)는 상기 반도체 칩(116), 절연막(114) 및 연결단자(110)의 상면이 동일한 높이를 가짐에 따라 루프 없이 직선의 형태로 형성되며, 상기 반도체 칩(116) 및 연결단자(110)가 공정상의 이유로 일부 다른 높이를 갖더라도 루프 높이가 최소화되도록 형성한다. As the upper surface of the semiconductor chip 116, the insulating layer 114, and the connection terminal 110 have the same height, the metal wire 120 is formed in a straight line without a loop, and the semiconductor chip 116 and the connection Although the terminal 110 has some other height for process reasons, the loop height is formed to be minimized.

도 2g를 참조하면, 상기 연결단자(110), 절연막(114), 반도체 칩(116) 및 금속와이어를 상면에 전기적인 절연 및 보호를 위하여 상기 연결단자(110), 절연막(114), 반도체 칩(116) 및 금속와이어를 덮도록 캡핑막(122)을 형성한다. Referring to FIG. 2G, the connection terminal 110, the insulating layer 114, and the semiconductor chip are electrically connected to the upper surface of the connection terminal 110, the insulating layer 114, the semiconductor chip 116, and the metal wire. A capping film 122 is formed to cover 116 and the metal wires.

그런 다음, 상기 기판(100)의 하면에 솔더볼과 같은 외부접속단자(124)가 부착하여 반도체 패키지의 제조를 완료한다.Then, an external connection terminal 124 such as a solder ball is attached to the lower surface of the substrate 100 to complete the manufacture of the semiconductor package.

이상에서와 같이, 본 발명은 패키지의 전기적인 연결을 위한 금속와이어를 루프 없도록 형성하기 위하여 반도체 칩의 상면과 대응하는 높이를 갖도록 기판 상에 연결단자를 형성하고 상기 반도체 칩과 연결단자 간에 직선의 형태를 갖는 금속와이어를 형성한다. As described above, the present invention is to form a connection terminal on the substrate to have a height corresponding to the upper surface of the semiconductor chip in order to form a loop of the metal wire for the electrical connection of the package and a straight line between the semiconductor chip and the connection terminal A metal wire having a shape is formed.

따라서, 금속와이어를 루프가 없이 직선의 형태로 형성함으로써 종래에 비하여 반도체 패키지의 전체 두께를 줄일 수 있다.Accordingly, by forming the metal wires in a straight line without a loop, the overall thickness of the semiconductor package can be reduced as compared with the conventional art.

또한, 금속와이어가 직선의 형태를 가지고 몰딩부 형성 공정을 수행하지 않음으로써 와이어의 스위핑 현상과 같은 불량을 원천적으로 방지할 수 있다.In addition, since the metal wire has a straight shape and does not perform the molding part forming process, defects such as a wire sweeping phenomenon may be prevented at the source.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

도 1은 본 발명의 실시예에 따른 반도체 패키지를 도시한 도면.1 illustrates a semiconductor package according to an embodiment of the present invention.

도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체 패키지의 제조 방법을 설명하기 위한 공정별 도면.2A to 2G are process-specific diagrams for describing a method of manufacturing a semiconductor package according to an embodiment of the present invention.

Claims (17)

다수의 접속 패드를 구비된 기판;A substrate having a plurality of connection pads; 상기 접속 패드 상에 형성된 연결단자;A connection terminal formed on the connection pad; 상기 기판 상에 배치되고 상면에 다수의 본딩 패드가 구비된 반도체 칩; A semiconductor chip disposed on the substrate and having a plurality of bonding pads disposed on an upper surface thereof; 상기 기판 상에 상기 반도체 칩과 상기 연결단자의 측면을 감싸도록 형성된 절연막; An insulating layer formed on the substrate to surround side surfaces of the semiconductor chip and the connection terminal; 상기 반도체 칩의 본딩 패드와 상기 연결단자 간을 연결하는 금속와이어; 및A metal wire connecting the bonding pad of the semiconductor chip and the connection terminal; And 상기 연결단자, 반도체 칩, 절연막 및 금속와이어를 덮도록 형성된 캡핑막;A capping film formed to cover the connection terminal, the semiconductor chip, the insulating film, and the metal wire; 을 포함하는 것을 특징으로 하는 반도체 패키지.A semiconductor package comprising a. 청구항 2은(는) 설정등록료 납부시 포기되었습니다.Claim 2 has been abandoned due to the setting registration fee. 제 1 항에 있어서,The method of claim 1, 상기 금속와이어는 상기 반도체 칩에 대하여 수평방향으로 직선의 형태를 갖는 것을 특징으로 하는 반도체 패키지.The metal wire is a semiconductor package, characterized in that the straight shape in the horizontal direction with respect to the semiconductor chip. 청구항 3은(는) 설정등록료 납부시 포기되었습니다.Claim 3 was abandoned when the setup registration fee was paid. 제 1 항에 있어서,The method of claim 1, 상기 연결단자는 상면이 상기 반도체 칩의 상면과 동일한 높이를 갖는 것을 특징으로 하는 반도체 패키지.The connecting terminal has a semiconductor package, characterized in that the upper surface has the same height as the upper surface of the semiconductor chip. 청구항 4은(는) 설정등록료 납부시 포기되었습니다.Claim 4 was abandoned when the registration fee was paid. 제 1 항에 있어서,The method of claim 1, 청구항 5은(는) 설정등록료 납부시 포기되었습니다.Claim 5 was abandoned upon payment of a set-up fee. 제 1 항에 있어서,The method of claim 1, 상기 절연막은 상면에 상기 연결단자 및 상기 반도체 칩의 상면과 동일하거나 낮은 높이를 갖는 것을 특징으로 하는 반도체 패키지.And the insulating layer has a height equal to or lower than an upper surface of the connection terminal and the semiconductor chip on an upper surface thereof. 청구항 6은(는) 설정등록료 납부시 포기되었습니다.Claim 6 was abandoned when the registration fee was paid. 제 1 항에 있어서,The method of claim 1, 상기 절연막은 솔더 레지스트(Solder resist)로 이루어진 것을 특징으로 하는 반도체 패키지.The insulating film is a semiconductor package, characterized in that consisting of a solder resist (Solder resist). 청구항 7은(는) 설정등록료 납부시 포기되었습니다.Claim 7 was abandoned upon payment of a set-up fee. 제 1 항에 있어서,The method of claim 1, 상기 기판의 하면에 부착된 외부접속단자를 더 포함하는 것을 특징으로 하는 반도체 패키지.The semiconductor package further comprises an external connection terminal attached to the lower surface of the substrate. 다수의 접속 패드를 구비하고, 반도체 칩 부착 영역을 갖는 기판의 상기 접속 패드 상에 다수의 연결단자를 형성하는 단계;Forming a plurality of connection terminals on the connection pad of the substrate having a plurality of connection pads and having a semiconductor chip attachment region; 상기 기판 상에 상기 반도체 칩 부착 영역을 노출시키도록 함과 아울러 상기 연결단자의 측면을 감싸도록 절연막을 형성하는 단계; Forming an insulating layer on the substrate to expose the semiconductor chip attachment region and to surround the side surface of the connection terminal; 상기 기판의 반도체 칩 부착 영역에 상면에 다수의 본딩 패드를 갖는 반도체 칩을 부착하는 단계; Attaching a semiconductor chip having a plurality of bonding pads on an upper surface of the semiconductor chip attaching region of the substrate; 상기 반도체 칩의 본딩 패드와 상기 연결단자 간에 금속와이어를 형성하는 단계; 및Forming a metal wire between a bonding pad of the semiconductor chip and the connection terminal; And 상기 반도체 칩, 연결단자, 절연막 및 금속와이어를 덮도록 캡핑막을 형성하는 단계;Forming a capping layer to cover the semiconductor chip, the connection terminal, the insulating layer, and the metal wire; 를 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.Method of manufacturing a semiconductor package comprising a. 청구항 9은(는) 설정등록료 납부시 포기되었습니다.Claim 9 was abandoned upon payment of a set-up fee. 제 8 항에 있어서,The method of claim 8, 상기 연결단자를 형성하는 단계는,Forming the connection terminal, 상기 기판 상에 금속씨드막을 형성하는 단계;Forming a metal seed film on the substrate; 상기 금속씨드막 상에 상기 접속 패드 상부 부분을 노출시키는 마스크패턴을 형성하는 단계; Forming a mask pattern exposing an upper portion of the connection pad on the metal seed layer; 상기 연결단자를 형성하는 단계; Forming the connection terminal; 상기 마스크패턴을 제거하는 단계; 및Removing the mask pattern; And 상기 연결단자 하부에만 상기 금속씨드막이 잔류하도록 상기 기판 상의 금속씨드막을 제거하는 단계;를Removing the metal seed film on the substrate such that the metal seed film remains only under the connection terminal; 를 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.Method of manufacturing a semiconductor package comprising a. 청구항 10은(는) 설정등록료 납부시 포기되었습니다.Claim 10 was abandoned upon payment of a setup registration fee. 제 8 항에 있어서,The method of claim 8, 상기 연결단자는 도금 공정으로 형성하는 것을 특징으로 하는 반도체 패키지 의 제조 방법.The connecting terminal is a manufacturing method of the semiconductor package, characterized in that formed by the plating process. 청구항 11은(는) 설정등록료 납부시 포기되었습니다.Claim 11 was abandoned upon payment of a setup registration fee. 제 8 항에 있어서,The method of claim 8, 상기 연결단자는 구리(Cu), 니켈(Ni) 및 금(Au) 중 어느 하나로 형성하거나 이들을 포함하는 합금으로 형성하는 것을 특징으로 하는 반도체 패키지의 제조 방법.The connecting terminal is formed of any one of copper (Cu), nickel (Ni) and gold (Au) or a method of manufacturing a semiconductor package, characterized in that formed by an alloy containing them. 청구항 12은(는) 설정등록료 납부시 포기되었습니다.Claim 12 was abandoned upon payment of a registration fee. 제 8 항에 있어서,The method of claim 8, 상기 금속와이어는 상기 반도체 칩에 대하여 수평방향으로 직선의 형태를 갖도록 형성하는 것을 특징으로 하는 반도체 패키지의 제조 방법.The metal wire is a semiconductor package manufacturing method characterized in that it is formed to have a straight line in the horizontal direction with respect to the semiconductor chip. 청구항 13은(는) 설정등록료 납부시 포기되었습니다.Claim 13 was abandoned upon payment of a registration fee. 제 8 항에 있어서,The method of claim 8, 상기 연결단자는 상면이 상기 반도체 칩의 상면과 동일한 높이를 갖도록 형성하는 것을 특징으로 하는 반도체 패키지의 제조 방법.The connecting terminal is a manufacturing method of a semiconductor package, characterized in that the upper surface is formed to have the same height as the upper surface of the semiconductor chip. 청구항 14은(는) 설정등록료 납부시 포기되었습니다.Claim 14 was abandoned when the registration fee was paid. 제 8 항에 있어서,The method of claim 8, 상기 절연막은 상면이 상기 연결단자 및 상기 반도체 칩의 상면과 동일하거나 낮은 높이를 갖도록 형성하는 것을 특징으로 하는 반도체 패키지의 제조 방법.The insulating film is a semiconductor package manufacturing method, characterized in that the upper surface is formed to have the same or lower height than the upper surface of the connecting terminal and the semiconductor chip. 청구항 15은(는) 설정등록료 납부시 포기되었습니다.Claim 15 was abandoned upon payment of a registration fee. 제 8 항에 있어서,The method of claim 8, 청구항 16은(는) 설정등록료 납부시 포기되었습니다.Claim 16 was abandoned upon payment of a setup registration fee. 제 8 항에 있어서,The method of claim 8, 상기 절연막은 솔더 레지스트로 형성하는 것을 특징으로 하는 반도체 패키지의 제조 방법.The insulating film is a manufacturing method of a semiconductor package, characterized in that formed with a solder resist. 청구항 17은(는) 설정등록료 납부시 포기되었습니다.Claim 17 has been abandoned due to the setting registration fee. 제 8 항에 있어서,The method of claim 8, 상기 캡핑막을 형성하는 단계 후, 상기 기판의 하면에 외부접속단자를 부착하는 단계를 더 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.And after the forming of the capping film, attaching an external connection terminal to a lower surface of the substrate.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001267351A (en) 2000-03-17 2001-09-28 Fujitsu General Ltd Wire-bonding structure
JP2003188314A (en) 2001-12-20 2003-07-04 Sony Corp Method of manufacturing substrate with built-in element and substrate with built-in element
KR20030080187A (en) * 2002-04-05 2003-10-11 미쓰비시덴키 가부시키가이샤 Semiconductor device
JP2007242773A (en) 2006-03-07 2007-09-20 Seiko Epson Corp Semiconductor device and its manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001267351A (en) 2000-03-17 2001-09-28 Fujitsu General Ltd Wire-bonding structure
JP2003188314A (en) 2001-12-20 2003-07-04 Sony Corp Method of manufacturing substrate with built-in element and substrate with built-in element
KR20030080187A (en) * 2002-04-05 2003-10-11 미쓰비시덴키 가부시키가이샤 Semiconductor device
JP2007242773A (en) 2006-03-07 2007-09-20 Seiko Epson Corp Semiconductor device and its manufacturing method

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